/* * Copyright 2013 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * Authors: Christian König <christian.koenig@amd.com> */ #include <linux/firmware.h>#include <linux/module.h>#include <drm/drmP.h>#include <drm/drm.h> #include "amdgpu.h"#include "amdgpu_pm.h"#include "amdgpu_vce.h"#include "cikd.h" /* 1 second timeout */#define VCE_IDLE_TIMEOUT_MS	1000 /* Firmware Names */#ifdef CONFIG_DRM_AMDGPU_CIK#define FIRMWARE_BONAIRE	"radeon/bonaire_vce.bin"#define FIRMWARE_KABINI 	"radeon/kabini_vce.bin"#define FIRMWARE_KAVERI 	"radeon/kaveri_vce.bin"#define FIRMWARE_HAWAII 	"radeon/hawaii_vce.bin"#define FIRMWARE_MULLINS	"radeon/mullins_vce.bin"#endif#define FIRMWARE_TONGA		"amdgpu/tonga_vce.bin"#define FIRMWARE_CARRIZO	"amdgpu/carrizo_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIKMODULE_FIRMWARE(FIRMWARE_BONAIRE);MODULE_FIRMWARE(FIRMWARE_KABINI);MODULE_FIRMWARE(FIRMWARE_KAVERI);MODULE_FIRMWARE(FIRMWARE_HAWAII);MODULE_FIRMWARE(FIRMWARE_MULLINS);#endifMODULE_FIRMWARE(FIRMWARE_TONGA);MODULE_FIRMWARE(FIRMWARE_CARRIZO); static void amdgpu_vce_idle_work_handler(struct work_struct *work); /** * amdgpu_vce_init - allocate memory, load vce firmware * * @adev: amdgpu_device pointer * * First step to get VCE online, allocate memory and load the firmware */int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size){	const char *fw_name;	const struct common_firmware_header *hdr;	unsigned ucode_version, version_major, version_minor, binary_id;	int i, r; 	INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler); 	switch (adev->asic_type) {#ifdef CONFIG_DRM_AMDGPU_CIK	case CHIP_BONAIRE:		fw_name = FIRMWARE_BONAIRE;		break;	case CHIP_KAVERI:		fw_name = FIRMWARE_KAVERI;		break;	case CHIP_KABINI:		fw_name = FIRMWARE_KABINI;		break;	case CHIP_HAWAII:		fw_name = FIRMWARE_HAWAII;		break;	case CHIP_MULLINS:		fw_name = FIRMWARE_MULLINS;		break;#endif	case CHIP_TONGA:		fw_name = FIRMWARE_TONGA;		break;	case CHIP_CARRIZO:		fw_name = FIRMWARE_CARRIZO;		break; 	default:		return -EINVAL;	} 	r = request_firmware(&adev->vce.fw, fw_name, adev->dev);	if (r) {		dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",			fw_name);		return r;	} 	r = amdgpu_ucode_validate(adev->vce.fw);	if (r) {		dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",			fw_name);		release_firmware(adev->vce.fw);		adev->vce.fw = NULL;		return r;	} 	hdr = (const struct common_firmware_header *)adev->vce.fw->data; 	ucode_version = le32_to_cpu(hdr->ucode_version);	version_major = (ucode_version >> 20) & 0xfff;	version_minor = (ucode_version >> 8) & 0xfff;	binary_id = ucode_version & 0xff;	DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",		version_major, version_minor, binary_id);	adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |				(binary_id << 8)); 	/* allocate firmware, stack and heap BO */ 	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,			     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo);	if (r) {		dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);		return r;	} 	r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);	if (r) {		amdgpu_bo_unref(&adev->vce.vcpu_bo);		dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);		return r;	} 	r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,			  &adev->vce.gpu_addr);	amdgpu_bo_unreserve(adev->vce.vcpu_bo);	if (r) {		amdgpu_bo_unref(&adev->vce.vcpu_bo);		dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);		return r;	} 	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {		atomic_set(&adev->vce.handles[i], 0);		adev->vce.filp[i] = NULL;	} 	return 0;} /** * amdgpu_vce_fini - free memory * * @adev: amdgpu_device pointer * * Last step on VCE teardown, free firmware memory */int amdgpu_vce_sw_fini(struct amdgpu_device *adev){	if (adev->vce.vcpu_bo == NULL)		return 0; 	amdgpu_bo_unref(&adev->vce.vcpu_bo); 	amdgpu_ring_fini(&adev->vce.ring[0]);	amdgpu_ring_fini(&adev->vce.ring[1]); 	release_firmware(adev->vce.fw); 	return 0;} /** * amdgpu_vce_suspend - unpin VCE fw memory * * @adev: amdgpu_device pointer * */int amdgpu_vce_suspend(struct amdgpu_device *adev){	int i; 	if (adev->vce.vcpu_bo == NULL)		return 0; 	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)		if (atomic_read(&adev->vce.handles[i]))			break; 	if (i == AMDGPU_MAX_VCE_HANDLES)		return 0; 	/* TODO: suspending running encoding sessions isn't supported */	return -EINVAL;} /** * amdgpu_vce_resume - pin VCE fw memory * * @adev: amdgpu_device pointer * */int amdgpu_vce_resume(struct amdgpu_device *adev){	void *cpu_addr;	const struct common_firmware_header *hdr;	unsigned offset;	int r; 	if (adev->vce.vcpu_bo == NULL)		return -EINVAL; 	r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);	if (r) {		dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);		return r;	} 	r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);	if (r) {		amdgpu_bo_unreserve(adev->vce.vcpu_bo);		dev_err(adev->dev, "(%d) VCE map failed\n", r);		return r;	} 	hdr = (const struct common_firmware_header *)adev->vce.fw->data;	offset = le32_to_cpu(hdr->ucode_array_offset_bytes);	memcpy(cpu_addr, (adev->vce.fw->data) + offset,		(adev->vce.fw->size) - offset); 	amdgpu_bo_kunmap(adev->vce.vcpu_bo); 	amdgpu_bo_unreserve(adev->vce.vcpu_bo); 	return 0;} /** * amdgpu_vce_idle_work_handler - power off VCE * * @work: pointer to work structure * * power of VCE when it's not used any more */static void amdgpu_vce_idle_work_handler(struct work_struct *work){	struct amdgpu_device *adev =		container_of(work, struct amdgpu_device, vce.idle_work.work); 	if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&	    (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {		if (adev->pm.dpm_enabled) {			amdgpu_dpm_enable_vce(adev, false);		} else {			amdgpu_asic_set_vce_clocks(adev, 0, 0);		}	} else {		schedule_delayed_work(&adev->vce.idle_work,				      msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));	}} /** * amdgpu_vce_note_usage - power up VCE * * @adev: amdgpu_device pointer * * Make sure VCE is powerd up when we want to use it */static void amdgpu_vce_note_usage(struct amdgpu_device *adev){	bool streams_changed = false;	bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);	set_clocks &= schedule_delayed_work(&adev->vce.idle_work,					    msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS)); 	if (adev->pm.dpm_enabled) {		/* XXX figure out if the streams changed */		streams_changed = false;	} 	if (set_clocks || streams_changed) {		if (adev->pm.dpm_enabled) {			amdgpu_dpm_enable_vce(adev, true);		} else {			amdgpu_asic_set_vce_clocks(adev, 53300, 40000);		}	}} /** * amdgpu_vce_free_handles - free still open VCE handles * * @adev: amdgpu_device pointer * @filp: drm file pointer * * Close all VCE handles still open by this file pointer */void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp){	struct amdgpu_ring *ring = &adev->vce.ring[0];	int i, r;	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {		uint32_t handle = atomic_read(&adev->vce.handles[i]);		if (!handle || adev->vce.filp[i] != filp)			continue; 		amdgpu_vce_note_usage(adev); 		r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);		if (r)			DRM_ERROR("Error destroying VCE handle (%d)!\n", r); 		adev->vce.filp[i] = NULL;		atomic_set(&adev->vce.handles[i], 0);	}} /** * amdgpu_vce_get_create_msg - generate a VCE create msg * * @adev: amdgpu_device pointer * @ring: ring we should submit the msg to * @handle: VCE session handle to use * @fence: optional fence to return * * Open up a stream for HW test */int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,			      struct amdgpu_fence **fence){	const unsigned ib_size_dw = 1024;	struct amdgpu_ib ib;	uint64_t dummy;	int i, r; 	r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib);	if (r) {		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);		return r;	} 	dummy = ib.gpu_addr + 1024; 	/* stitch together an VCE create msg */	ib.length_dw = 0;	ib.ptr[ib.length_dw++] = 0x0000000c; /* len */	ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */	ib.ptr[ib.length_dw++] = handle; 	ib.ptr[ib.length_dw++] = 0x00000030; /* len */	ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */	ib.ptr[ib.length_dw++] = 0x00000000;	ib.ptr[ib.length_dw++] = 0x00000042;	ib.ptr[ib.length_dw++] = 0x0000000a;	ib.ptr[ib.length_dw++] = 0x00000001;	ib.ptr[ib.length_dw++] = 0x00000080;	ib.ptr[ib.length_dw++] = 0x00000060;	ib.ptr[ib.length_dw++] = 0x00000100;	ib.ptr[ib.length_dw++] = 0x00000100;	ib.ptr[ib.length_dw++] = 0x0000000c;	ib.ptr[ib.length_dw++] = 0x00000000; 	ib.ptr[ib.length_dw++] = 0x00000014; /* len */	ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */	ib.ptr[ib.length_dw++] = upper_32_bits(dummy);	ib.ptr[ib.length_dw++] = dummy;	ib.ptr[ib.length_dw++] = 0x00000001; 	for (i = ib.length_dw; i < ib_size_dw; ++i)		ib.ptr[i] = 0x0; 	r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);	if (r) {		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);	} 	if (fence)		*fence = amdgpu_fence_ref(ib.fence); 	amdgpu_ib_free(ring->adev, &ib); 	return r;} /** * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg * * @adev: amdgpu_device pointer * @ring: ring we should submit the msg to * @handle: VCE session handle to use * @fence: optional fence to return * * Close up a stream for HW test or if userspace failed to do so */int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,			       struct amdgpu_fence **fence){	const unsigned ib_size_dw = 1024;	struct amdgpu_ib ib;	uint64_t dummy;	int i, r; 	r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib);	if (r) {		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);		return r;	} 	dummy = ib.gpu_addr + 1024; 	/* stitch together an VCE destroy msg */	ib.length_dw = 0;	ib.ptr[ib.length_dw++] = 0x0000000c; /* len */	ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */	ib.ptr[ib.length_dw++] = handle; 	ib.ptr[ib.length_dw++] = 0x00000014; /* len */	ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */	ib.ptr[ib.length_dw++] = upper_32_bits(dummy);	ib.ptr[ib.length_dw++] = dummy;	ib.ptr[ib.length_dw++] = 0x00000001; 	ib.ptr[ib.length_dw++] = 0x00000008; /* len */	ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */ 	for (i = ib.length_dw; i < ib_size_dw; ++i)		ib.ptr[i] = 0x0; 	r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);	if (r) {		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);	} 	if (fence)		*fence = amdgpu_fence_ref(ib.fence); 	amdgpu_ib_free(ring->adev, &ib); 	return r;} /** * amdgpu_vce_cs_reloc - command submission relocation * * @p: parser context * @lo: address of lower dword * @hi: address of higher dword * @size: minimum size * * Patch relocation inside command stream with real buffer address */static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,			       int lo, int hi, unsigned size, uint32_t index){	struct amdgpu_bo_va_mapping *mapping;	struct amdgpu_ib *ib = &p->ibs[ib_idx];	struct amdgpu_bo *bo;	uint64_t addr; 	if (index == 0xffffffff)		index = 0; 	addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |	       ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;	addr += ((uint64_t)size) * ((uint64_t)index); 	mapping = amdgpu_cs_find_mapping(p, addr, &bo);	if (mapping == NULL) {		DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",			  addr, lo, hi, size, index);		return -EINVAL;	} 	if ((addr + (uint64_t)size) >	    ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {		DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",			  addr, lo, hi);		return -EINVAL;	} 	addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;

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