/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */#include <drm/drmP.h>#include <drm/amdgpu_drm.h>#include "amdgpu.h"#include "amdgpu_trace.h" /* * GPUVM * GPUVM is similar to the legacy gart on older asics, however * rather than there being a single global gart table * for the entire GPU, there are multiple VM page tables active * at any given time. The VM page tables can contain a mix * vram pages and system memory pages and system memory pages * can be mapped as snooped (cached system pages) or unsnooped * (uncached system pages). * Each VM has an ID associated with it and there is a page table * associated with each VMID. When execting a command buffer, * the kernel tells the the ring what VMID to use for that command * buffer. VMIDs are allocated dynamically as commands are submitted. * The userspace drivers maintain their own address space and the kernel * sets up their pages tables accordingly when they submit their * command buffers and a VMID is assigned. * Cayman/Trinity support up to 8 active VMs at any given time; * SI supports 16. */ /* Special value that no flush is necessary */#define AMDGPU_VM_NO_FLUSH (~0ll) /** * amdgpu_vm_num_pde - return the number of page directory entries * * @adev: amdgpu_device pointer * * Calculate the number of page directory entries. */static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev){ return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;} /** * amdgpu_vm_directory_size - returns the size of the page directory in bytes * * @adev: amdgpu_device pointer * * Calculate the size of the page directory in bytes. */static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev){ return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);} /** * amdgpu_vm_get_pd_bo - add the VM PD to a validation list * * @vm: vm providing the BOs * @validated: head of validation list * @entry: entry to add * * Add the page directory to the list of BOs to * validate for command submission. */void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, struct amdgpu_bo_list_entry *entry){ entry->robj = vm->page_directory; entry->priority = 0; entry->tv.bo = &vm->page_directory->tbo; entry->tv.shared = true; entry->user_pages = NULL; list_add(&entry->tv.head, validated);} /** * amdgpu_vm_get_bos - add the vm BOs to a duplicates list * * @vm: vm providing the BOs * @duplicates: head of duplicates list * * Add the page directory to the BO duplicates list * for command submission. */void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates){ unsigned i; /* add the vm page table to the list */ for (i = 0; i <= vm->max_pde_used; ++i) { struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; if (!entry->robj) continue; list_add(&entry->tv.head, duplicates); } } /** * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail * * @adev: amdgpu device instance * @vm: vm providing the BOs * * Move the PT BOs to the tail of the LRU. */void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, struct amdgpu_vm *vm){ struct ttm_bo_global *glob = adev->mman.bdev.glob; unsigned i; spin_lock(&glob->lru_lock); for (i = 0; i <= vm->max_pde_used; ++i) { struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; if (!entry->robj) continue; ttm_bo_move_to_lru_tail(&entry->robj->tbo); } spin_unlock(&glob->lru_lock);} /** * amdgpu_vm_grab_id - allocate the next free VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to * @sync: sync object where we add dependencies * @fence: fence protecting ID from reuse * * Allocate an id for the vm, adding fences to the sync obj as necessary. */int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync, struct fence *fence, unsigned *vm_id, uint64_t *vm_pd_addr){ uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); struct amdgpu_device *adev = ring->adev; struct amdgpu_vm_id *id = &vm->ids[ring->idx]; struct fence *updates = sync->last_vm_update; int r; mutex_lock(&adev->vm_manager.lock); /* check if the id is still valid */ if (id->mgr_id) { struct fence *flushed = id->flushed_updates; bool is_later; long owner; if (!flushed) is_later = true; else if (!updates) is_later = false; else is_later = fence_is_later(updates, flushed); owner = atomic_long_read(&id->mgr_id->owner); if (!is_later && owner == (long)id && pd_addr == id->pd_gpu_addr) { r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); if (r) { mutex_unlock(&adev->vm_manager.lock); return r; } fence_put(id->mgr_id->active); id->mgr_id->active = fence_get(fence); list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); *vm_id = id->mgr_id - adev->vm_manager.ids; *vm_pd_addr = AMDGPU_VM_NO_FLUSH; trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); mutex_unlock(&adev->vm_manager.lock); return 0; } } id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru, struct amdgpu_vm_manager_id, list); r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); if (!r) { fence_put(id->mgr_id->active); id->mgr_id->active = fence_get(fence); fence_put(id->flushed_updates); id->flushed_updates = fence_get(updates); id->pd_gpu_addr = pd_addr; list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); atomic_long_set(&id->mgr_id->owner, (long)id); *vm_id = id->mgr_id - adev->vm_manager.ids; *vm_pd_addr = pd_addr; trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); } mutex_unlock(&adev->vm_manager.lock); return r;} /** * amdgpu_vm_flush - hardware flush the vm * * @ring: ring to use for flush * @vm_id: vmid number to use * @pd_addr: address of the page directory * * Emit a VM flush when it is necessary. */void amdgpu_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size){ struct amdgpu_device *adev = ring->adev; struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; bool gds_switch_needed = ring->funcs->emit_gds_switch && ( mgr_id->gds_base != gds_base || mgr_id->gds_size != gds_size || mgr_id->gws_base != gws_base || mgr_id->gws_size != gws_size || mgr_id->oa_base != oa_base || mgr_id->oa_size != oa_size); if (ring->funcs->emit_pipeline_sync && ( pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) amdgpu_ring_emit_pipeline_sync(ring); if (pd_addr != AMDGPU_VM_NO_FLUSH) { trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); } if (gds_switch_needed) { mgr_id->gds_base = gds_base; mgr_id->gds_size = gds_size; mgr_id->gws_base = gws_base; mgr_id->gws_size = gws_size; mgr_id->oa_base = oa_base; mgr_id->oa_size = oa_size; amdgpu_ring_emit_gds_switch(ring, vm_id, gds_base, gds_size, gws_base, gws_size, oa_base, oa_size); }} /** * amdgpu_vm_reset_id - reset VMID to zero * * @adev: amdgpu device structure * @vm_id: vmid number to use * * Reset saved GDW, GWS and OA to force switch on next flush. */void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id){ struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; mgr_id->gds_base = 0; mgr_id->gds_size = 0; mgr_id->gws_base = 0; mgr_id->gws_size = 0; mgr_id->oa_base = 0; mgr_id->oa_size = 0;} /** * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo * * @vm: requested vm * @bo: requested buffer object * * Find @bo inside the requested vm. * Search inside the @bos vm list for the requested vm * Returns the found bo_va or NULL if none is found * * Object has to be reserved! */struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, struct amdgpu_bo *bo){ struct amdgpu_bo_va *bo_va; list_for_each_entry(bo_va, &bo->va, bo_list) { if (bo_va->vm == vm) { return bo_va; } } return NULL;} /** * amdgpu_vm_update_pages - helper to call the right asic function * * @adev: amdgpu_device pointer * @gtt: GART instance to use for mapping * @gtt_flags: GTT hw access flags * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: hw access flags * * Traces the parameters and calls the right asic functions * to setup the page table using the DMA. */static void amdgpu_vm_update_pages(struct amdgpu_device *adev, struct amdgpu_gart *gtt, uint32_t gtt_flags, struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags){ trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); if ((gtt == &adev->gart) && (flags == gtt_flags)) { uint64_t src = gtt->table_addr + (addr >> 12) * 8; amdgpu_vm_copy_pte(adev, ib, pe, src, count); } else if (gtt) { dma_addr_t *pages_addr = gtt->pages_addr; amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, count, incr, flags); } else if (count < 3) { amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, count, incr, flags); } else { amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags); }} /** * amdgpu_vm_clear_bo - initially clear the page dir/table * * @adev: amdgpu_device pointer * @bo: bo to clear * * need to reserve bo first before calling it. */static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo *bo){ struct amdgpu_ring *ring; struct fence *fence = NULL; struct amdgpu_job *job; unsigned entries; uint64_t addr; int r; ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); r = reservation_object_reserve_shared(bo->tbo.resv); if (r) return r; r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); if (r) goto error; addr = amdgpu_bo_gpu_offset(bo); entries = amdgpu_bo_size(bo) / 8; r = amdgpu_job_alloc_with_ib(adev, 64, &job); if (r) goto error; amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries, 0, 0); amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > 64); r = amdgpu_job_submit(job, ring, &vm->entity, AMDGPU_FENCE_OWNER_VM, &fence); if (r) goto error_free; amdgpu_bo_fence(bo, fence, true); fence_put(fence); return 0; error_free: amdgpu_job_free(job); error: return r;} /** * amdgpu_vm_map_gart - Resolve gart mapping of addr * * @pages_addr: optional DMA address to use for lookup * @addr: the unmapped addr * * Look up the physical address of the page that the pte resolves * to and return the pointer for the page table entry. */uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr){ uint64_t result; if (pages_addr) { /* page table offset */ result = pages_addr[addr >> PAGE_SHIFT]; /* in case cpu page size != gpu page size*/ result |= addr & (~PAGE_MASK); } else { /* No mapping required */ result = addr; } result &= 0xFFFFFFFFFFFFF000ULL; return result;} /** * amdgpu_vm_update_pdes - make sure that page directory is valid * * @adev: amdgpu_device pointer * @vm: requested vm * @start: start of GPU address range * @end: end of GPU address range * * Allocates new page tables if necessary * and updates the page directory. * Returns 0 for success, error for failure. */int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, struct amdgpu_vm *vm){ struct amdgpu_ring *ring; struct amdgpu_bo *pd = vm->page_directory; uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; uint64_t last_pde = ~0, last_pt = ~0; unsigned count = 0, pt_idx, ndw; struct amdgpu_job *job; struct amdgpu_ib *ib; struct fence *fence = NULL; int r; ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); /* padding, etc. */ ndw = 64; /* assume the worst case */ ndw += vm->max_pde_used * 6; Lines 1–500 of 1466. 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/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include <drm/drmP.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h" #include "amdgpu_trace.h" /* * GPUVM * GPUVM is similar to the legacy gart on older asics, however * rather than there being a single global gart table * for the entire GPU, there are multiple VM page tables active * at any given time. The VM page tables can contain a mix * vram pages and system memory pages and system memory pages * can be mapped as snooped (cached system pages) or unsnooped * (uncached system pages). * Each VM has an ID associated with it and there is a page table * associated with each VMID. When execting a command buffer, * the kernel tells the the ring what VMID to use for that command * buffer. VMIDs are allocated dynamically as commands are submitted. * The userspace drivers maintain their own address space and the kernel * sets up their pages tables accordingly when they submit their * command buffers and a VMID is assigned. * Cayman/Trinity support up to 8 active VMs at any given time; * SI supports 16. */ /* Special value that no flush is necessary */ #define AMDGPU_VM_NO_FLUSH (~0ll) /** * amdgpu_vm_num_pde - return the number of page directory entries * * @adev: amdgpu_device pointer * * Calculate the number of page directory entries. */ static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) { return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; } /** * amdgpu_vm_directory_size - returns the size of the page directory in bytes * * @adev: amdgpu_device pointer * * Calculate the size of the page directory in bytes. */ static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) { return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); } /** * amdgpu_vm_get_pd_bo - add the VM PD to a validation list * * @vm: vm providing the BOs * @validated: head of validation list * @entry: entry to add * * Add the page directory to the list of BOs to * validate for command submission. */ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, struct amdgpu_bo_list_entry *entry) { entry->robj = vm->page_directory; entry->priority = 0; entry->tv.bo = &vm->page_directory->tbo; entry->tv.shared = true; entry->user_pages = NULL; list_add(&entry->tv.head, validated); } /** * amdgpu_vm_get_bos - add the vm BOs to a duplicates list * * @vm: vm providing the BOs * @duplicates: head of duplicates list * * Add the page directory to the BO duplicates list * for command submission. */ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) { unsigned i; /* add the vm page table to the list */ for (i = 0; i <= vm->max_pde_used; ++i) { struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; if (!entry->robj) continue; list_add(&entry->tv.head, duplicates); } } /** * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail * * @adev: amdgpu device instance * @vm: vm providing the BOs * * Move the PT BOs to the tail of the LRU. */ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct ttm_bo_global *glob = adev->mman.bdev.glob; unsigned i; spin_lock(&glob->lru_lock); for (i = 0; i <= vm->max_pde_used; ++i) { struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; if (!entry->robj) continue; ttm_bo_move_to_lru_tail(&entry->robj->tbo); } spin_unlock(&glob->lru_lock); } /** * amdgpu_vm_grab_id - allocate the next free VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to * @sync: sync object where we add dependencies * @fence: fence protecting ID from reuse * * Allocate an id for the vm, adding fences to the sync obj as necessary. */ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync, struct fence *fence, unsigned *vm_id, uint64_t *vm_pd_addr) { uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); struct amdgpu_device *adev = ring->adev; struct amdgpu_vm_id *id = &vm->ids[ring->idx]; struct fence *updates = sync->last_vm_update; int r; mutex_lock(&adev->vm_manager.lock); /* check if the id is still valid */ if (id->mgr_id) { struct fence *flushed = id->flushed_updates; bool is_later; long owner; if (!flushed) is_later = true; else if (!updates) is_later = false; else is_later = fence_is_later(updates, flushed); owner = atomic_long_read(&id->mgr_id->owner); if (!is_later && owner == (long)id && pd_addr == id->pd_gpu_addr) { r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); if (r) { mutex_unlock(&adev->vm_manager.lock); return r; } fence_put(id->mgr_id->active); id->mgr_id->active = fence_get(fence); list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); *vm_id = id->mgr_id - adev->vm_manager.ids; *vm_pd_addr = AMDGPU_VM_NO_FLUSH; trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); mutex_unlock(&adev->vm_manager.lock); return 0; } } id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru, struct amdgpu_vm_manager_id, list); r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); if (!r) { fence_put(id->mgr_id->active); id->mgr_id->active = fence_get(fence); fence_put(id->flushed_updates); id->flushed_updates = fence_get(updates); id->pd_gpu_addr = pd_addr; list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); atomic_long_set(&id->mgr_id->owner, (long)id); *vm_id = id->mgr_id - adev->vm_manager.ids; *vm_pd_addr = pd_addr; trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); } mutex_unlock(&adev->vm_manager.lock); return r; } /** * amdgpu_vm_flush - hardware flush the vm * * @ring: ring to use for flush * @vm_id: vmid number to use * @pd_addr: address of the page directory * * Emit a VM flush when it is necessary. */ void amdgpu_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) { struct amdgpu_device *adev = ring->adev; struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; bool gds_switch_needed = ring->funcs->emit_gds_switch && ( mgr_id->gds_base != gds_base || mgr_id->gds_size != gds_size || mgr_id->gws_base != gws_base || mgr_id->gws_size != gws_size || mgr_id->oa_base != oa_base || mgr_id->oa_size != oa_size); if (ring->funcs->emit_pipeline_sync && ( pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) amdgpu_ring_emit_pipeline_sync(ring); if (pd_addr != AMDGPU_VM_NO_FLUSH) { trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); } if (gds_switch_needed) { mgr_id->gds_base = gds_base; mgr_id->gds_size = gds_size; mgr_id->gws_base = gws_base; mgr_id->gws_size = gws_size; mgr_id->oa_base = oa_base; mgr_id->oa_size = oa_size; amdgpu_ring_emit_gds_switch(ring, vm_id, gds_base, gds_size, gws_base, gws_size, oa_base, oa_size); } } /** * amdgpu_vm_reset_id - reset VMID to zero * * @adev: amdgpu device structure * @vm_id: vmid number to use * * Reset saved GDW, GWS and OA to force switch on next flush. */ void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) { struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; mgr_id->gds_base = 0; mgr_id->gds_size = 0; mgr_id->gws_base = 0; mgr_id->gws_size = 0; mgr_id->oa_base = 0; mgr_id->oa_size = 0; } /** * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo * * @vm: requested vm * @bo: requested buffer object * * Find @bo inside the requested vm. * Search inside the @bos vm list for the requested vm * Returns the found bo_va or NULL if none is found * * Object has to be reserved! */ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, struct amdgpu_bo *bo) { struct amdgpu_bo_va *bo_va; list_for_each_entry(bo_va, &bo->va, bo_list) { if (bo_va->vm == vm) { return bo_va; } } return NULL; } /** * amdgpu_vm_update_pages - helper to call the right asic function * * @adev: amdgpu_device pointer * @gtt: GART instance to use for mapping * @gtt_flags: GTT hw access flags * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: hw access flags * * Traces the parameters and calls the right asic functions * to setup the page table using the DMA. */ static void amdgpu_vm_update_pages(struct amdgpu_device *adev, struct amdgpu_gart *gtt, uint32_t gtt_flags, struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags) { trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); if ((gtt == &adev->gart) && (flags == gtt_flags)) { uint64_t src = gtt->table_addr + (addr >> 12) * 8; amdgpu_vm_copy_pte(adev, ib, pe, src, count); } else if (gtt) { dma_addr_t *pages_addr = gtt->pages_addr; amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, count, incr, flags); } else if (count < 3) { amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, count, incr, flags); } else { amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags); } } /** * amdgpu_vm_clear_bo - initially clear the page dir/table * * @adev: amdgpu_device pointer * @bo: bo to clear * * need to reserve bo first before calling it. */ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo *bo) { struct amdgpu_ring *ring; struct fence *fence = NULL; struct amdgpu_job *job; unsigned entries; uint64_t addr; int r; ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); r = reservation_object_reserve_shared(bo->tbo.resv); if (r) return r; r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); if (r) goto error; addr = amdgpu_bo_gpu_offset(bo); entries = amdgpu_bo_size(bo) / 8; r = amdgpu_job_alloc_with_ib(adev, 64, &job); if (r) goto error; amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries, 0, 0); amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > 64); r = amdgpu_job_submit(job, ring, &vm->entity, AMDGPU_FENCE_OWNER_VM, &fence); if (r) goto error_free; amdgpu_bo_fence(bo, fence, true); fence_put(fence); return 0; error_free: amdgpu_job_free(job); error: return r; } /** * amdgpu_vm_map_gart - Resolve gart mapping of addr * * @pages_addr: optional DMA address to use for lookup * @addr: the unmapped addr * * Look up the physical address of the page that the pte resolves * to and return the pointer for the page table entry. */ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) { uint64_t result; if (pages_addr) { /* page table offset */ result = pages_addr[addr >> PAGE_SHIFT]; /* in case cpu page size != gpu page size*/ result |= addr & (~PAGE_MASK); } else { /* No mapping required */ result = addr; } result &= 0xFFFFFFFFFFFFF000ULL; return result; } /** * amdgpu_vm_update_pdes - make sure that page directory is valid * * @adev: amdgpu_device pointer * @vm: requested vm * @start: start of GPU address range * @end: end of GPU address range * * Allocates new page tables if necessary * and updates the page directory. * Returns 0 for success, error for failure. */ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct amdgpu_ring *ring; struct amdgpu_bo *pd = vm->page_directory; uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; uint64_t last_pde = ~0, last_pt = ~0; unsigned count = 0, pt_idx, ndw; struct amdgpu_job *job; struct amdgpu_ib *ib; struct fence *fence = NULL; int r; ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); /* padding, etc. */ ndw = 64; /* assume the worst case */ ndw += vm->max_pde_used * 6;