// SPDX-License-Identifier: GPL-2.0-only#include <linux/device.h>#include <linux/cpu.h>#include <linux/smp.h>#include <linux/percpu.h>#include <linux/init.h>#include <linux/sched.h>#include <linux/export.h>#include <linux/nodemask.h>#include <linux/cpumask.h>#include <linux/notifier.h> #include <asm/current.h>#include <asm/processor.h>#include <asm/cputable.h>#include <asm/hvcall.h>#include <asm/prom.h>#include <asm/machdep.h>#include <asm/smp.h>#include <asm/pmc.h>#include <asm/firmware.h>#include <asm/idle.h>#include <asm/svm.h> #include "cacheinfo.h"#include "setup.h" #ifdef CONFIG_PPC64#include <asm/paca.h>#include <asm/lppaca.h>#endif static DEFINE_PER_CPU(struct cpu, cpu_devices); #ifdef CONFIG_PPC64 /* * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle: * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in * 2014: * *  "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean *  up the kernel code." * * powerpc-utils stopped using it as of 1.3.8. At some point in the future this * code should be removed. */ static ssize_t store_smt_snooze_delay(struct device *dev,				      struct device_attribute *attr,				      const char *buf,				      size_t count){	pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",		     current->comm, current->pid);	return count;} static ssize_t show_smt_snooze_delay(struct device *dev,				     struct device_attribute *attr,				     char *buf){	pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",		     current->comm, current->pid);	return sprintf(buf, "100\n");} static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,		   store_smt_snooze_delay); static int __init setup_smt_snooze_delay(char *str){	if (!cpu_has_feature(CPU_FTR_SMT))		return 1; 	pr_warn("smt-snooze-delay command line option has no effect\n");	return 1;}__setup("smt-snooze-delay=", setup_smt_snooze_delay); #endif /* CONFIG_PPC64 */ #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \static void read_##NAME(void *val) \{ \	*(unsigned long *)val = mfspr(ADDRESS);	\} \static void write_##NAME(void *val) \{ \	EXTRA; \	mtspr(ADDRESS, *(unsigned long *)val);	\} #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \static ssize_t show_##NAME(struct device *dev, \			struct device_attribute *attr, \			char *buf) \{ \	struct cpu *cpu = container_of(dev, struct cpu, dev); \	unsigned long val; \	smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);	\	return sprintf(buf, "%lx\n", val); \} \static ssize_t __used \	store_##NAME(struct device *dev, struct device_attribute *attr, \			const char *buf, size_t count) \{ \	struct cpu *cpu = container_of(dev, struct cpu, dev); \	unsigned long val; \	int ret = sscanf(buf, "%lx", &val); \	if (ret != 1) \		return -EINVAL; \	smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \	return count; \} #define SYSFS_PMCSETUP(NAME, ADDRESS) \	__SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \	__SYSFS_SPRSETUP_SHOW_STORE(NAME)#define SYSFS_SPRSETUP(NAME, ADDRESS) \	__SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \	__SYSFS_SPRSETUP_SHOW_STORE(NAME) #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \	__SYSFS_SPRSETUP_SHOW_STORE(NAME) #ifdef CONFIG_PPC64 /* * This is the system wide DSCR register default value. Any * change to this default value through the sysfs interface * will update all per cpu DSCR default values across the * system stored in their respective PACA structures. */static unsigned long dscr_default; /** * read_dscr() - Fetch the cpu specific DSCR default * @val:	Returned cpu specific DSCR default value * * This function returns the per cpu DSCR default value * for any cpu which is contained in it's PACA structure. */static void read_dscr(void *val){	*(unsigned long *)val = get_paca()->dscr_default;}  /** * write_dscr() - Update the cpu specific DSCR default * @val:	New cpu specific DSCR default value to update * * This function updates the per cpu DSCR default value * for any cpu which is contained in it's PACA structure. */static void write_dscr(void *val){	get_paca()->dscr_default = *(unsigned long *)val;	if (!current->thread.dscr_inherit) {		current->thread.dscr = *(unsigned long *)val;		mtspr(SPRN_DSCR, *(unsigned long *)val);	}} SYSFS_SPRSETUP_SHOW_STORE(dscr);static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr); static void add_write_permission_dev_attr(struct device_attribute *attr){	attr->attr.mode |= 0200;} /** * show_dscr_default() - Fetch the system wide DSCR default * @dev:	Device structure * @attr:	Device attribute structure * @buf:	Interface buffer * * This function returns the system wide DSCR default value. */static ssize_t show_dscr_default(struct device *dev,		struct device_attribute *attr, char *buf){	return sprintf(buf, "%lx\n", dscr_default);} /** * store_dscr_default() - Update the system wide DSCR default * @dev:	Device structure * @attr:	Device attribute structure * @buf:	Interface buffer * @count:	Size of the update * * This function updates the system wide DSCR default value. */static ssize_t __used store_dscr_default(struct device *dev,		struct device_attribute *attr, const char *buf,		size_t count){	unsigned long val;	int ret = 0; 	ret = sscanf(buf, "%lx", &val);	if (ret != 1)		return -EINVAL;	dscr_default = val; 	on_each_cpu(write_dscr, &val, 1); 	return count;} static DEVICE_ATTR(dscr_default, 0600,		show_dscr_default, store_dscr_default); static void sysfs_create_dscr_default(void){	if (cpu_has_feature(CPU_FTR_DSCR)) {		int cpu; 		dscr_default = spr_default_dscr;		for_each_possible_cpu(cpu)			paca_ptrs[cpu]->dscr_default = dscr_default; 		device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);	}}#endif /* CONFIG_PPC64 */ #ifdef CONFIG_PPC_FSL_BOOK3E#define MAX_BIT				63 static u64 pw20_wt;static u64 altivec_idle_wt; static unsigned int get_idle_ticks_bit(u64 ns){	u64 cycle; 	if (ns >= 10000)		cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;	else		cycle = div_u64(ns * tb_ticks_per_usec, 1000); 	if (!cycle)		return 0; 	return ilog2(cycle);} static void do_show_pwrmgtcr0(void *val){	u32 *value = val; 	*value = mfspr(SPRN_PWRMGTCR0);} static ssize_t show_pw20_state(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	unsigned int cpu = dev->id; 	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 	value &= PWRMGTCR0_PW20_WAIT; 	return sprintf(buf, "%u\n", value ? 1 : 0);} static void do_store_pw20_state(void *val){	u32 *value = val;	u32 pw20_state; 	pw20_state = mfspr(SPRN_PWRMGTCR0); 	if (*value)		pw20_state |= PWRMGTCR0_PW20_WAIT;	else		pw20_state &= ~PWRMGTCR0_PW20_WAIT; 	mtspr(SPRN_PWRMGTCR0, pw20_state);} static ssize_t store_pw20_state(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 value;	unsigned int cpu = dev->id; 	if (kstrtou32(buf, 0, &value))		return -EINVAL; 	if (value > 1)		return -EINVAL; 	smp_call_function_single(cpu, do_store_pw20_state, &value, 1); 	return count;} static ssize_t show_pw20_wait_time(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	u64 tb_cycle = 1;	u64 time; 	unsigned int cpu = dev->id; 	if (!pw20_wt) {		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);		value = (value & PWRMGTCR0_PW20_ENT) >>					PWRMGTCR0_PW20_ENT_SHIFT; 		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));		/* convert ms to ns */		if (tb_ticks_per_usec > 1000) {			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);		} else {			u32 rem_us; 			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,						&rem_us);			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;		}	} else {		time = pw20_wt;	} 	return sprintf(buf, "%llu\n", time > 0 ? time : 0);} static void set_pw20_wait_entry_bit(void *val){	u32 *value = val;	u32 pw20_idle; 	pw20_idle = mfspr(SPRN_PWRMGTCR0); 	/* Set Automatic PW20 Core Idle Count */	/* clear count */	pw20_idle &= ~PWRMGTCR0_PW20_ENT; 	/* set count */	pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT); 	mtspr(SPRN_PWRMGTCR0, pw20_idle);} static ssize_t store_pw20_wait_time(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 entry_bit;	u64 value; 	unsigned int cpu = dev->id; 	if (kstrtou64(buf, 0, &value))		return -EINVAL; 	if (!value)		return -EINVAL; 	entry_bit = get_idle_ticks_bit(value);	if (entry_bit > MAX_BIT)		return -EINVAL; 	pw20_wt = value; 	smp_call_function_single(cpu, set_pw20_wait_entry_bit,				&entry_bit, 1); 	return count;} static ssize_t show_altivec_idle(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	unsigned int cpu = dev->id; 	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 	value &= PWRMGTCR0_AV_IDLE_PD_EN; 	return sprintf(buf, "%u\n", value ? 1 : 0);} static void do_store_altivec_idle(void *val){	u32 *value = val;	u32 altivec_idle; 	altivec_idle = mfspr(SPRN_PWRMGTCR0); 	if (*value)		altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;	else		altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN; 	mtspr(SPRN_PWRMGTCR0, altivec_idle);} static ssize_t store_altivec_idle(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 value;	unsigned int cpu = dev->id; 	if (kstrtou32(buf, 0, &value))		return -EINVAL; 	if (value > 1)		return -EINVAL; 	smp_call_function_single(cpu, do_store_altivec_idle, &value, 1); 	return count;} static ssize_t show_altivec_idle_wait_time(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	u64 tb_cycle = 1;	u64 time; 	unsigned int cpu = dev->id; 	if (!altivec_idle_wt) {		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);		value = (value & PWRMGTCR0_AV_IDLE_CNT) >>					PWRMGTCR0_AV_IDLE_CNT_SHIFT; 		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));		/* convert ms to ns */		if (tb_ticks_per_usec > 1000) {			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);		} else {			u32 rem_us; 			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,						&rem_us);			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;		}	} else {		time = altivec_idle_wt;	} 	return sprintf(buf, "%llu\n", time > 0 ? time : 0);} static void set_altivec_idle_wait_entry_bit(void *val){	u32 *value = val;	u32 altivec_idle; 	altivec_idle = mfspr(SPRN_PWRMGTCR0); 	/* Set Automatic AltiVec Idle Count */	/* clear count */	altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT; 	/* set count */	altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT); 	mtspr(SPRN_PWRMGTCR0, altivec_idle);} static ssize_t store_altivec_idle_wait_time(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 entry_bit;	u64 value; 	unsigned int cpu = dev->id; 	if (kstrtou64(buf, 0, &value))		return -EINVAL; 	if (!value)		return -EINVAL; 	entry_bit = get_idle_ticks_bit(value);	if (entry_bit > MAX_BIT)		return -EINVAL; 	altivec_idle_wt = value; 	smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,				&entry_bit, 1); 	return count;

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