/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include <linux/string_helpers.h>#include <linux/uaccess.h> #include "dc.h"#include "amdgpu.h"#include "amdgpu_dm.h"#include "amdgpu_dm_debugfs.h"#include "dm_helpers.h"#include "dmub/dmub_srv.h"#include "resource.h"#include "dsc.h"#include "dc_link_dp.h"#include "link_hwss.h"#include "dc/dc_dmub_srv.h" #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY#include "amdgpu_dm_psr.h"#endif struct dmub_debugfs_trace_header {	uint32_t entry_count;	uint32_t reserved[3];}; struct dmub_debugfs_trace_entry {	uint32_t trace_code;	uint32_t tick_count;	uint32_t param0;	uint32_t param1;}; static const char *const mst_progress_status[] = {	"probe",	"remote_edid",	"allocate_new_payload",	"clear_allocated_payload",}; /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array * * Function takes in attributes passed to debugfs write entry * and writes into param array. * The user passes max_param_num to identify maximum number of * parameters that could be parsed. * */static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,					  long *param, const char __user *buf,					  int max_param_num,					  uint8_t *param_nums){	char *wr_buf_ptr = NULL;	uint32_t wr_buf_count = 0;	int r;	char *sub_str = NULL;	const char delimiter[3] = {' ', '\n', '\0'};	uint8_t param_index = 0; 	*param_nums = 0; 	wr_buf_ptr = wr_buf; 	/* r is bytes not be copied */	if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {		DRM_DEBUG_DRIVER("user data could not be read successfully\n");		return -EFAULT;	} 	/* check number of parameters. isspace could not differ space and \n */	while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {		/* skip space*/		while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {			wr_buf_ptr++;			wr_buf_count++;			} 		if (wr_buf_count == wr_buf_size)			break; 		/* skip non-space*/		while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {			wr_buf_ptr++;			wr_buf_count++;		} 		(*param_nums)++; 		if (wr_buf_count == wr_buf_size)			break;	} 	if (*param_nums > max_param_num)		*param_nums = max_param_num; 	wr_buf_ptr = wr_buf; /* reset buf pointer */	wr_buf_count = 0; /* number of char already checked */ 	while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {		wr_buf_ptr++;		wr_buf_count++;	} 	while (param_index < *param_nums) {		/* after strsep, wr_buf_ptr will be moved to after space */		sub_str = strsep(&wr_buf_ptr, delimiter); 		r = kstrtol(sub_str, 16, &(param[param_index])); 		if (r)			DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 		param_index++;	} 	return 0;} /* function description * get/ set DP configuration: lane_count, link_rate, spread_spectrum * * valid lane count value: 1, 2, 4 * valid link rate value: * 06h = 1.62Gbps per lane * 0Ah = 2.7Gbps per lane * 0Ch = 3.24Gbps per lane * 14h = 5.4Gbps per lane * 1Eh = 8.1Gbps per lane * * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings * * --- to get dp configuration * * cat /sys/kernel/debug/dri/0/DP-x/link_settings * * It will list current, verified, reported, preferred dp configuration. * current -- for current video mode * verified --- maximum configuration which pass link training * reported --- DP rx report caps (DPCD register offset 0, 1 2) * preferred --- user force settings * * --- set (or force) dp configuration * * echo <lane_count>  <link_rate> > link_settings * * for example, to force to  2 lane, 2.7GHz, * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings * * spread_spectrum could not be changed dynamically. * * in case invalid lane count, link rate are force, no hw programming will be * done. please check link settings after force operation to see if HW get * programming. * * cat /sys/kernel/debug/dri/0/DP-x/link_settings * * check current and preferred settings. * */static ssize_t dp_link_settings_read(struct file *f, char __user *buf,				 size_t size, loff_t *pos){	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;	struct dc_link *link = connector->dc_link;	char *rd_buf = NULL;	char *rd_buf_ptr = NULL;	const uint32_t rd_buf_size = 100;	uint32_t result = 0;	uint8_t str_len = 0;	int r; 	if (*pos & 3 || size & 3)		return -EINVAL; 	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);	if (!rd_buf)		return 0; 	rd_buf_ptr = rd_buf; 	str_len = strlen("Current:  %d  0x%x  %d  ");	snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",			link->cur_link_settings.lane_count,			link->cur_link_settings.link_rate,			link->cur_link_settings.link_spread);	rd_buf_ptr += str_len; 	str_len = strlen("Verified:  %d  0x%x  %d  ");	snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",			link->verified_link_cap.lane_count,			link->verified_link_cap.link_rate,			link->verified_link_cap.link_spread);	rd_buf_ptr += str_len; 	str_len = strlen("Reported:  %d  0x%x  %d  ");	snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",			link->reported_link_cap.lane_count,			link->reported_link_cap.link_rate,			link->reported_link_cap.link_spread);	rd_buf_ptr += str_len; 	str_len = strlen("Preferred:  %d  0x%x  %d  ");	snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",			link->preferred_link_setting.lane_count,			link->preferred_link_setting.link_rate,			link->preferred_link_setting.link_spread); 	while (size) {		if (*pos >= rd_buf_size)			break; 		r = put_user(*(rd_buf + result), buf);		if (r) {			kfree(rd_buf);			return r; /* r = -EFAULT */		} 		buf += 1;		size -= 1;		*pos += 1;		result += 1;	} 	kfree(rd_buf);	return result;} static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,				 size_t size, loff_t *pos){	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;	struct dc_link *link = connector->dc_link;	struct amdgpu_device *adev = drm_to_adev(connector->base.dev);	struct dc *dc = (struct dc *)link->dc;	struct dc_link_settings prefer_link_settings;	char *wr_buf = NULL;	const uint32_t wr_buf_size = 40;	/* 0: lane_count; 1: link_rate */	int max_param_num = 2;	uint8_t param_nums = 0;	long param[2];	bool valid_input = true; 	if (size == 0)		return -EINVAL; 	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);	if (!wr_buf)		return -ENOSPC; 	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,					   (long *)param, buf,					   max_param_num,					   &param_nums)) {		kfree(wr_buf);		return -EINVAL;	} 	if (param_nums <= 0) {		kfree(wr_buf);		DRM_DEBUG_DRIVER("user data not be read\n");		return -EINVAL;	} 	switch (param[0]) {	case LANE_COUNT_ONE:	case LANE_COUNT_TWO:	case LANE_COUNT_FOUR:		break;	default:		valid_input = false;		break;	} 	switch (param[1]) {	case LINK_RATE_LOW:	case LINK_RATE_HIGH:	case LINK_RATE_RBR2:	case LINK_RATE_HIGH2:	case LINK_RATE_HIGH3:	case LINK_RATE_UHBR10:	case LINK_RATE_UHBR13_5:	case LINK_RATE_UHBR20:		break;	default:		valid_input = false;		break;	} 	if (!valid_input) {		kfree(wr_buf);		DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");		mutex_lock(&adev->dm.dc_lock);		dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);		mutex_unlock(&adev->dm.dc_lock);		return size;	} 	/* save user force lane_count, link_rate to preferred settings	 * spread spectrum will not be changed	 */	prefer_link_settings.link_spread = link->cur_link_settings.link_spread;	prefer_link_settings.use_link_rate_set = false;	prefer_link_settings.lane_count = param[0];	prefer_link_settings.link_rate = param[1]; 	mutex_lock(&adev->dm.dc_lock);	dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);	mutex_unlock(&adev->dm.dc_lock); 	kfree(wr_buf);	return size;} /* function: get current DP PHY settings: voltage swing, pre-emphasis, * post-cursor2 (defined by VESA DP specification) * * valid values * voltage swing: 0,1,2,3 * pre-emphasis : 0,1,2,3 * post cursor2 : 0,1,2,3 * * * how to use this debugfs * * debugfs is located at /sys/kernel/debug/dri/0/DP-x * * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display * * To figure out which DP-x is the display for DP to be check, * cd DP-x * ls -ll * There should be debugfs file, like link_settings, phy_settings. * cat link_settings * from lane_count, link_rate to figure which DP-x is for display to be worked * on * * To get current DP PHY settings, * cat phy_settings * * To change DP PHY settings, * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to * 0, * echo 2 3 0 > phy_settings * * To check if change be applied, get current phy settings by * cat phy_settings * * In case invalid values are set by user, like * echo 1 4 0 > phy_settings * * HW will NOT be programmed by these settings. * cat phy_settings will show the previous valid settings. */static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,				 size_t size, loff_t *pos){	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;	struct dc_link *link = connector->dc_link;	char *rd_buf = NULL;	const uint32_t rd_buf_size = 20;	uint32_t result = 0;	int r; 	if (*pos & 3 || size & 3)		return -EINVAL; 	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);	if (!rd_buf)		return -EINVAL; 	snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",			link->cur_lane_setting[0].VOLTAGE_SWING,			link->cur_lane_setting[0].PRE_EMPHASIS,			link->cur_lane_setting[0].POST_CURSOR2); 	while (size) {		if (*pos >= rd_buf_size)			break; 		r = put_user((*(rd_buf + result)), buf);		if (r) {			kfree(rd_buf);			return r; /* r = -EFAULT */		} 		buf += 1;		size -= 1;		*pos += 1;		result += 1;	} 	kfree(rd_buf);	return result;} static int dp_lttpr_status_show(struct seq_file *m, void *d){	char *data;	struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;	struct dc_link *link = connector->dc_link;	uint32_t read_size = 1;	uint8_t repeater_count = 0; 	data = kzalloc(read_size, GFP_KERNEL);	if (!data)		return 0; 	dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 	switch ((uint8_t)*data) {	case 0x80:		repeater_count = 1;		break;	case 0x40:		repeater_count = 2;		break;	case 0x20:		repeater_count = 3;		break;	case 0x10:		repeater_count = 4;		break;	case 0x8:		repeater_count = 5;		break;	case 0x4:		repeater_count = 6;		break;	case 0x2:		repeater_count = 7;		break;	case 0x1:		repeater_count = 8;		break;	case 0x0:		repeater_count = 0;		break;	default:		repeater_count = (uint8_t)*data;		break;	} 	seq_printf(m, "phy repeater count: %d\n", repeater_count); 	dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 	if ((uint8_t)*data == 0x55)		seq_printf(m, "phy repeater mode: transparent\n");	else if ((uint8_t)*data == 0xAA)		seq_printf(m, "phy repeater mode: non-transparent\n");	else if ((uint8_t)*data == 0x00)		seq_printf(m, "phy repeater mode: non lttpr\n");	else		seq_printf(m, "phy repeater mode: read error\n"); 	kfree(data);	return 0;} static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,				 size_t size, loff_t *pos){	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;	struct dc_link *link = connector->dc_link;	struct dc *dc = (struct dc *)link->dc;	char *wr_buf = NULL;	uint32_t wr_buf_size = 40;	long param[3];	bool use_prefer_link_setting;	struct link_training_settings link_lane_settings;	int max_param_num = 3;	uint8_t param_nums = 0;	int r = 0; 

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