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Merge tag 'amd-drm-fixes-5.19-2022-07-13' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-5.19-2022-07-13: amdgpu: - DP MST blank screen fix for specific platforms - MEC firmware check fix for GC 10.3.7 - Deep color fix for DCE - Fix possible divide by 0 - Coverage blend mode fix - Fix cursor only commit timestamps

Dave Airlie committed 4 years ago

Commit 093f8d82 parents 5bde069 3283c836 files · +115 −9Browse files

Unified · Split

6 files
  1. drivers/gpu/drm/amd/amdkfd/kfd_device.c +2 −0
  2. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +80 −4
  3. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +8 −0
  4. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +17 −0
  5. drivers/gpu/drm/amd/display/dc/core/dc_resource.c +6 −5
  6. drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +2 −0
drivers/gpu/drm/amd/amdkfd/kfd_device.c+2−0
@@ -184,6 +184,8 @@ static void kfd_device_info_init(struct kfd_dev *kfd, · 183 unmodified lines
184184 /* Navi2x+, Navi1x+ */
185185 if (gc_version == IP_VERSION(10, 3, 6))
186186 kfd->device_info.no_atomic_fw_version = 14;
187+ else if (gc_version == IP_VERSION(10, 3, 7))
188+ kfd->device_info.no_atomic_fw_version = 3;
187189 else if (gc_version >= IP_VERSION(10, 3, 0))
188190 kfd->device_info.no_atomic_fw_version = 92;
189191 else if (gc_version >= IP_VERSION(10, 1, 1))
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+80−4
@@ -72,6 +72,7 @@ · 71 unmodified lines
7272 #include <linux/pci.h>
7373 #include <linux/firmware.h>
7474 #include <linux/component.h>
75+#include <linux/dmi.h>
7576
7677 #include <drm/display/drm_dp_mst_helper.h>
7778 #include <drm/display/drm_hdmi_helper.h>
@@ -462,6 +463,26 @@ static void dm_pflip_high_irq(void *interrupt_params) · 384 unmodified lines
462463 vrr_active, (int) !e);
463464 }
464465
466+static void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
467+{
468+ struct drm_crtc *crtc = &acrtc->base;
469+ struct drm_device *dev = crtc->dev;
470+ unsigned long flags;
471+
472+ drm_crtc_handle_vblank(crtc);
473+
474+ spin_lock_irqsave(&dev->event_lock, flags);
475+
476+ /* Send completion event for cursor-only commits */
477+ if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
478+ drm_crtc_send_vblank_event(crtc, acrtc->event);
479+ drm_crtc_vblank_put(crtc);
480+ acrtc->event = NULL;
481+ }
482+
483+ spin_unlock_irqrestore(&dev->event_lock, flags);
484+}
485+
465486 static void dm_vupdate_high_irq(void *interrupt_params)
466487 {
467488 struct common_irq_params *irq_params = interrupt_params;
@@ -500,7 +521,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) · 32 unmodified lines
500521 * if a pageflip happened inside front-porch.
501522 */
502523 if (vrr_active) {
503− drm_crtc_handle_vblank(&acrtc->base);
524+ dm_crtc_handle_vblank(acrtc);
504525
505526 /* BTR processing for pre-DCE12 ASICs */
506527 if (acrtc->dm_irq_params.stream &&
@@ -552,7 +573,7 @@ static void dm_crtc_high_irq(void *interrupt_params) · 45 unmodified lines
552573 * to dm_vupdate_high_irq after end of front-porch.
553574 */
554575 if (!vrr_active)
555− drm_crtc_handle_vblank(&acrtc->base);
576+ dm_crtc_handle_vblank(acrtc);
556577
557578 /**
558579 * Following stuff must happen at start of vblank, for crc
@@ -1382,6 +1403,41 @@ static bool dm_should_disable_stutter(struct pci_dev *pdev) · 823 unmodified lines
13821403 return false;
13831404 }
13841405
1406+static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1407+ {
1408+ .matches = {
1409+ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1410+ DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1411+ },
1412+ },
1413+ {
1414+ .matches = {
1415+ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1416+ DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1417+ },
1418+ },
1419+ {
1420+ .matches = {
1421+ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1422+ DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1423+ },
1424+ },
1425+ {}
1426+};
1427+
1428+static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1429+{
1430+ const struct dmi_system_id *dmi_id;
1431+
1432+ dm->aux_hpd_discon_quirk = false;
1433+
1434+ dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1435+ if (dmi_id) {
1436+ dm->aux_hpd_discon_quirk = true;
1437+ DRM_INFO("aux_hpd_discon_quirk attached\n");
1438+ }
1439+}
1440+
13851441 static int amdgpu_dm_init(struct amdgpu_device *adev)
13861442 {
13871443 struct dc_init_data init_data;
@@ -1508,6 +1564,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 120 unmodified lines
15081564 }
15091565
15101566 INIT_LIST_HEAD(&adev->dm.da_list);
1567+
1568+ retrieve_dmi_info(&adev->dm);
1569+
15111570 /* Display Core create. */
15121571 adev->dm.dc = dc_create(&init_data);
15131572
@@ -5407,7 +5466,7 @@ fill_blending_from_plane_state(const struct drm_plane_state *plane_state, · 3893 unmodified lines
54075466 }
54085467 }
54095468
5410− if (per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
5469+ if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
54115470 *pre_multiplied_alpha = false;
54125471 }
54135472
@@ -9135,6 +9194,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 3721 unmodified lines
91359194 struct amdgpu_bo *abo;
91369195 uint32_t target_vblank, last_flip_vblank;
91379196 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
9197+ bool cursor_update = false;
91389198 bool pflip_present = false;
91399199 struct {
91409200 struct dc_surface_update surface_updates[MAX_SURFACES];
@@ -9170,8 +9230,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 29 unmodified lines
91709230 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
91719231
91729232 /* Cursor plane is handled after stream updates */
9173− if (plane->type == DRM_PLANE_TYPE_CURSOR)
9233+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9234+ if ((fb && crtc == pcrtc) ||
9235+ (old_plane_state->fb && old_plane_state->crtc == pcrtc))
9236+ cursor_update = true;
9237+
91749238 continue;
9239+ }
91759240
91769241 if (!fb || !crtc || pcrtc != crtc)
91779242 continue;
@@ -9334,6 +9399,17 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 156 unmodified lines
93349399 bundle->stream_update.vrr_infopacket =
93359400 &acrtc_state->stream->vrr_infopacket;
93369401 }
9402+ } else if (cursor_update && acrtc_state->active_planes > 0 &&
9403+ !acrtc_state->force_dpms_off &&
9404+ acrtc_attach->base.state->event) {
9405+ drm_crtc_vblank_get(pcrtc);
9406+
9407+ spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
9408+
9409+ acrtc_attach->event = acrtc_attach->base.state->event;
9410+ acrtc_attach->base.state->event = NULL;
9411+
9412+ spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
93379413 }
93389414
93399415 /* Update the planes if changed or disable if we don't have any. */
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+8−0
@@ -540,6 +540,14 @@ struct amdgpu_display_manager { · 539 unmodified lines
540540 * last successfully applied backlight values.
541541 */
542542 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
543+
544+ /**
545+ * @aux_hpd_discon_quirk:
546+ *
547+ * quirk for hpd discon while aux is on-going.
548+ * occurred on certain intel platform
549+ */
550+ bool aux_hpd_discon_quirk;
543551 };
544552
545553 enum dsc_clock_force_state {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+17−0
@@ -56,6 +56,8 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, · 55 unmodified lines
5656 ssize_t result = 0;
5757 struct aux_payload payload;
5858 enum aux_return_code_type operation_result;
59+ struct amdgpu_device *adev;
60+ struct ddc_service *ddc;
5961
6062 if (WARN_ON(msg->size > 16))
6163 return -E2BIG;
@@ -74,6 +76,21 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, · 12 unmodified lines
7476 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
7577 &operation_result);
7678
79+ /*
80+ * w/a on certain intel platform where hpd is unexpected to pull low during
81+ * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
82+ * aux transaction is succuess in such case, therefore bypass the error
83+ */
84+ ddc = TO_DM_AUX(aux)->ddc_service;
85+ adev = ddc->ctx->driver_context;
86+ if (adev->dm.aux_hpd_discon_quirk) {
87+ if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
88+ operation_result == AUX_RET_ERROR_HPD_DISCON) {
89+ result = 0;
90+ operation_result = AUX_RET_SUCCESS;
91+ }
92+ }
93+
7794 if (payload.write && result >= 0)
7895 result = msg->size;
7996
drivers/gpu/drm/amd/display/dc/core/dc_resource.c+6−5
@@ -1117,12 +1117,13 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 1116 unmodified lines
11171117 * on certain displays, such as the Sharp 4k. 36bpp is needed
11181118 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
11191119 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1120− * precision on at least DCN display engines. However, at least
1121− * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1122− * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3
1123− * did not show such problems, so this seems to be the exception.
1120+ * precision on DCN display engines, but apparently not for DCE, as
1121+ * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
1122+ * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1123+ * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
1124+ * passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
11241125 */
1125− if (plane_state->ctx->dce_version > DCE_VERSION_11_0)
1126+ if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
11261127 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
11271128 else
11281129 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c+2−0
@@ -1228,6 +1228,8 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, · 1227 unmodified lines
12281228 uint32_t crystal_clock_freq = 2500;
12291229 uint32_t tach_period;
12301230
1231+ if (speed == 0)
1232+ return -EINVAL;
12311233 /*
12321234 * To prevent from possible overheat, some ASICs may have requirement
12331235 * for minimum fan speed: