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Merge tag 'drm-intel-fixes-2018-11-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

- Fix for fastboot DSI panel boot time flicker regression, also fixes Bugzilla #108225 - Fix Bugzilla #101269 to avoid GPU hangs on Sandybridge machines - Avoid GPU hang on error capture on Broxton with Vt-d enabled - Avoid missing GPU relocations on Pineview and Bearlake (Gen3)

Dave Airlie committed 7 years ago

Commit 98c9cdf2 parents 8cf6f36 f5591567 files · +112 −4Browse files

Unified · Split

7 files
  1. drivers/gpu/drm/i915/i915_gem_execbuffer.c +6 −1
  2. drivers/gpu/drm/i915/i915_gem_gtt.c +5 −0
  3. drivers/gpu/drm/i915/i915_gpu_error.c +14 −1
  4. drivers/gpu/drm/i915/i915_gpu_error.h +7 −1
  5. drivers/gpu/drm/i915/intel_display.c +39 −0
  6. drivers/gpu/drm/i915/intel_drv.h +1 −0
  7. drivers/gpu/drm/i915/intel_pm.c +40 −1
drivers/gpu/drm/i915/i915_gem_execbuffer.c+6−1
@@ -1268,7 +1268,7 @@ relocate_entry(struct i915_vma *vma, · 1267 unmodified lines
12681268 else if (gen >= 4)
12691269 len = 4;
12701270 else
1271− len = 3;
1271+ len = 6;
12721272
12731273 batch = reloc_gpu(eb, vma, len);
12741274 if (IS_ERR(batch))
@@ -1309,6 +1309,11 @@ relocate_entry(struct i915_vma *vma, · 34 unmodified lines
13091309 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
13101310 *batch++ = addr;
13111311 *batch++ = target_offset;
1312+
1313+ /* And again for good measure (blb/pnv) */
1314+ *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1315+ *batch++ = addr;
1316+ *batch++ = target_offset;
13121317 }
13131318
13141319 goto out;
drivers/gpu/drm/i915/i915_gem_gtt.c+5−0
@@ -3413,6 +3413,11 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) · 3412 unmodified lines
34133413 ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL;
34143414 if (ggtt->vm.clear_range != nop_clear_range)
34153415 ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;
3416+
3417+ /* Prevent recursively calling stop_machine() and deadlocks. */
3418+ dev_info(dev_priv->drm.dev,
3419+ "Disabling error capture for VT-d workaround\n");
3420+ i915_disable_error_state(dev_priv, -ENODEV);
34163421 }
34173422
34183423 ggtt->invalidate = gen6_ggtt_invalidate;
drivers/gpu/drm/i915/i915_gpu_error.c+14−1
@@ -648,6 +648,9 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, · 647 unmodified lines
648648 return 0;
649649 }
650650
651+ if (IS_ERR(error))
652+ return PTR_ERR(error);
653+
651654 if (*error->error_msg)
652655 err_printf(m, "%s\n", error->error_msg);
653656 err_printf(m, "Kernel: " UTS_RELEASE "\n");
@@ -1859,6 +1862,7 @@ void i915_capture_error_state(struct drm_i915_private *i915, · 1205 unmodified lines
18591862 error = i915_capture_gpu_state(i915);
18601863 if (!error) {
18611864 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1865+ i915_disable_error_state(i915, -ENOMEM);
18621866 return;
18631867 }
18641868
@@ -1914,5 +1918,14 @@ void i915_reset_error_state(struct drm_i915_private *i915) · 49 unmodified lines
19141918 i915->gpu_error.first_error = NULL;
19151919 spin_unlock_irq(&i915->gpu_error.lock);
19161920
1917− i915_gpu_state_put(error);
1921+ if (!IS_ERR(error))
1922+ i915_gpu_state_put(error);
1923+}
1924+
1925+void i915_disable_error_state(struct drm_i915_private *i915, int err)
1926+{
1927+ spin_lock_irq(&i915->gpu_error.lock);
1928+ if (!i915->gpu_error.first_error)
1929+ i915->gpu_error.first_error = ERR_PTR(err);
1930+ spin_unlock_irq(&i915->gpu_error.lock);
19181931 }
drivers/gpu/drm/i915/i915_gpu_error.h+7−1
@@ -343,6 +343,7 @@ static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) · 342 unmodified lines
343343
344344 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
345345 void i915_reset_error_state(struct drm_i915_private *i915);
346+void i915_disable_error_state(struct drm_i915_private *i915, int err);
346347
347348 #else
348349
@@ -355,13 +356,18 @@ static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, · 6 unmodified lines
355356 static inline struct i915_gpu_state *
356357 i915_first_error_state(struct drm_i915_private *i915)
357358 {
358− return NULL;
359+ return ERR_PTR(-ENODEV);
359360 }
360361
361362 static inline void i915_reset_error_state(struct drm_i915_private *i915)
362363 {
363364 }
364365
366+static inline void i915_disable_error_state(struct drm_i915_private *i915,
367+ int err)
368+{
369+}
370+
365371 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
366372
367373 #endif /* _I915_GPU_ERROR_H_ */
drivers/gpu/drm/i915/intel_display.c+39−0
@@ -2890,6 +2890,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, · 2889 unmodified lines
28902890 return;
28912891
28922892 valid_fb:
2893+ intel_state->base.rotation = plane_config->rotation;
28932894 intel_fill_fb_ggtt_view(&intel_state->view, fb,
28942895 intel_state->base.rotation);
28952896 intel_state->color_plane[0].stride =
@@ -7882,8 +7883,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, · 4986 unmodified lines
78827883 plane_config->tiling = I915_TILING_X;
78837884 fb->modifier = I915_FORMAT_MOD_X_TILED;
78847885 }
7886+
7887+ if (val & DISPPLANE_ROTATE_180)
7888+ plane_config->rotation = DRM_MODE_ROTATE_180;
78857889 }
78867890
7891+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
7892+ val & DISPPLANE_MIRROR)
7893+ plane_config->rotation |= DRM_MODE_REFLECT_X;
7894+
78877895 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
78887896 fourcc = i9xx_format_to_fourcc(pixel_format);
78897897 fb->format = drm_format_info(fourcc);
@@ -8952,6 +8960,29 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, · 1062 unmodified lines
89528960 goto error;
89538961 }
89548962
8963+ /*
8964+ * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
8965+ * while i915 HW rotation is clockwise, thats why this swapping.
8966+ */
8967+ switch (val & PLANE_CTL_ROTATE_MASK) {
8968+ case PLANE_CTL_ROTATE_0:
8969+ plane_config->rotation = DRM_MODE_ROTATE_0;
8970+ break;
8971+ case PLANE_CTL_ROTATE_90:
8972+ plane_config->rotation = DRM_MODE_ROTATE_270;
8973+ break;
8974+ case PLANE_CTL_ROTATE_180:
8975+ plane_config->rotation = DRM_MODE_ROTATE_180;
8976+ break;
8977+ case PLANE_CTL_ROTATE_270:
8978+ plane_config->rotation = DRM_MODE_ROTATE_90;
8979+ break;
8980+ }
8981+
8982+ if (INTEL_GEN(dev_priv) >= 10 &&
8983+ val & PLANE_CTL_FLIP_HORIZONTAL)
8984+ plane_config->rotation |= DRM_MODE_REFLECT_X;
8985+
89558986 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
89568987 plane_config->base = base;
89578988
@@ -15267,6 +15298,14 @@ retry: · 6309 unmodified lines
1526715298 ret = drm_atomic_add_affected_planes(state, crtc);
1526815299 if (ret)
1526915300 goto out;
15301+
15302+ /*
15303+ * FIXME hack to force a LUT update to avoid the
15304+ * plane update forcing the pipe gamma on without
15305+ * having a proper LUT loaded. Remove once we
15306+ * have readout for pipe gamma enable.
15307+ */
15308+ crtc_state->color_mgmt_changed = true;
1527015309 }
1527115310 }
1527215311
drivers/gpu/drm/i915/intel_drv.h+1−0
@@ -547,6 +547,7 @@ struct intel_initial_plane_config { · 546 unmodified lines
547547 unsigned int tiling;
548548 int size;
549549 u32 base;
550+ u8 rotation;
550551 };
551552
552553 #define SKL_MIN_SRC_W 8
drivers/gpu/drm/i915/intel_pm.c+40−1
@@ -2493,6 +2493,9 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, · 2492 unmodified lines
24932493 uint32_t method1, method2;
24942494 int cpp;
24952495
2496+ if (mem_value == 0)
2497+ return U32_MAX;
2498+
24962499 if (!intel_wm_plane_visible(cstate, pstate))
24972500 return 0;
24982501
@@ -2522,6 +2525,9 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, · 23 unmodified lines
25222525 uint32_t method1, method2;
25232526 int cpp;
25242527
2528+ if (mem_value == 0)
2529+ return U32_MAX;
2530+
25252531 if (!intel_wm_plane_visible(cstate, pstate))
25262532 return 0;
25272533
@@ -2545,6 +2551,9 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, · 17 unmodified lines
25452551 {
25462552 int cpp;
25472553
2554+ if (mem_value == 0)
2555+ return U32_MAX;
2556+
25482557 if (!intel_wm_plane_visible(cstate, pstate))
25492558 return 0;
25502559
@@ -3008,6 +3017,34 @@ static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) · 457 unmodified lines
30083017 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
30093018 }
30103019
3020+static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3021+{
3022+ /*
3023+ * On some SNB machines (Thinkpad X220 Tablet at least)
3024+ * LP3 usage can cause vblank interrupts to be lost.
3025+ * The DEIIR bit will go high but it looks like the CPU
3026+ * never gets interrupted.
3027+ *
3028+ * It's not clear whether other interrupt source could
3029+ * be affected or if this is somehow limited to vblank
3030+ * interrupts only. To play it safe we disable LP3
3031+ * watermarks entirely.
3032+ */
3033+ if (dev_priv->wm.pri_latency[3] == 0 &&
3034+ dev_priv->wm.spr_latency[3] == 0 &&
3035+ dev_priv->wm.cur_latency[3] == 0)
3036+ return;
3037+
3038+ dev_priv->wm.pri_latency[3] = 0;
3039+ dev_priv->wm.spr_latency[3] = 0;
3040+ dev_priv->wm.cur_latency[3] = 0;
3041+
3042+ DRM_DEBUG_KMS("LP3 watermarks disabled due to potential for lost interrupts\n");
3043+ intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3044+ intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3045+ intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3046+}
3047+
30113048 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
30123049 {
30133050 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
@@ -3024,8 +3061,10 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) · 10 unmodified lines
30243061 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
30253062 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
30263063
3027− if (IS_GEN6(dev_priv))
3064+ if (IS_GEN6(dev_priv)) {
30283065 snb_wm_latency_quirk(dev_priv);
3066+ snb_wm_lp3_irq_quirk(dev_priv);
3067+ }
30293068 }
30303069
30313070 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)

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