| @@ -315,13 +315,13 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { · 314 unmodified lines |
| 315 | RK2928_CLKGATE_CON(10), 8, GFLAGS), | 315 | RK2928_CLKGATE_CON(10), 8, GFLAGS), |
| 316 | | 316 | |
| 317 | GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0, | 317 | GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0, |
| 318 | RK2928_CLKGATE_CON(10), 8, GFLAGS), | 318 | RK2928_CLKGATE_CON(10), 0, GFLAGS), |
| 319 | GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0, | 319 | GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0, |
| 320 | RK2928_CLKGATE_CON(10), 8, GFLAGS), | 320 | RK2928_CLKGATE_CON(10), 1, GFLAGS), |
| 321 | GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0, | 321 | GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0, |
| 322 | RK2928_CLKGATE_CON(10), 8, GFLAGS), | 322 | RK2928_CLKGATE_CON(10), 2, GFLAGS), |
| 323 | GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED, | 323 | GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED, |
| 324 | RK2928_CLKGATE_CON(10), 8, GFLAGS), | 324 | RK2928_CLKGATE_CON(2), 15, GFLAGS), |
| 325 | | 325 | |
| 326 | COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, | 326 | COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, |
| 327 | RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS, | 327 | RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS, |
| @@ -541,7 +541,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { · 213 unmodified lines |
| 541 | GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), | 541 | GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), |
| 542 | GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS), | 542 | GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS), |
| 543 | | 543 | |
| 544 | GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 2, GFLAGS), | 544 | GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), |
| 545 | GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS), | 545 | GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS), |
| 546 | | 546 | |
| 547 | /* PD_MMC */ | 547 | /* PD_MMC */ |
| @@ -577,6 +577,8 @@ static const char *const rk3128_critical_clocks[] __initconst = { · 29 unmodified lines |
| 577 | "aclk_peri", | 577 | "aclk_peri", |
| 578 | "hclk_peri", | 578 | "hclk_peri", |
| 579 | "pclk_peri", | 579 | "pclk_peri", |
| | 580 | "pclk_pmu", |
| | 581 | "sclk_timer5", |
| 580 | }; | 582 | }; |
| 581 | | 583 | |
| 582 | static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np) | 584 | static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np) |