-	writeback-	D_VREG? vector register type/index field?-	ACASE/ABCASE	- register in ACASE must be dead after use, or better, take two registers MOVWZ -> MOVWU? basic §3.2 CBZ	Rt, label (imm19)CBNZ B.<cond>	label (imm19) SVC	$imm16HVCSMCBRKHLTDCPS1DCPS2DCPS3 MSR	$imm, CRnHINTCLREXDSBDMBISBSYS	CRm, CRn, RtMSR	CRm, CRn, RtSYSL	CRm, CRn, RtMRS	CRm, CRn, Rt TBZ	$b5:b40, Rt, label (imm14)   # bit numberTBNZ B	label (imm26)BL BR	RnBLRRET ERET Rn=1FDRPS §3.3 [SIMD later] LDR	label:19, RtLDR [SIMD&FP]LDRSWPRFM [load/store exclusive, later][load/store no-allocate pair, later] # post-index write-back load/store [simm9 range -256 to 255, then scaled]STR[BWHX]	#<simm9>, [Rn], RtLDR[S][BWHX] # pre-index write-backSTR[BWHX]	[Rn, <simm9>]!, RtLDR[S][BWHX] # unsigned offsetSTR[BWHX]	<uimm12>(Rn), Rt	# <uimm12> scaled by operand size fieldLDR[S][BWHX] STR[BWHX]	Rm [<option>][<shift>](Rn), Rt           SHIFT(EXT-or-LSL(Rn),{size|0})LDR[S][BWHX] [load/store unscaled immediate, later][load/store unsigned immediate, later][load/store register pair, offset][load/store register pair, post-indexed][load/store register pair, pre-indexed] §3.4 ADD		imm12+shift, Rn, RdADDSSUBSUBS SBFM	immr, imms, Rn, RdBFMUBFM EXR	imms, Rm, Rn, Rd AND	immr, imms, Rn, RdORREORANDS MOVN	hw, imm16, RdMOVZMOVK ADR	immhi:immlo, RdADRP §3.5 ADD	Rm [extend, imm3], Rn, RdADDSSUBSUBS ADD Rm <shift> imm6, Rn, RdADDSSUBSUBS ADC	Rm, Rn, RdADCSSBCSBCS # if cond then compare(Rn, -<imm5>) else $nzcvCCMN.<cond>	$<imm5>, Rn, $<nzcv>CCMP # if cond then compare(Rn, -Rm) else $nzcvCCMN.<cond>	Rm, Rn, $<nzcv>CCMP # if cond then Rn else F(Rm)CSEL.<cond> Rm, Rn, Rd		F = copyCSINC	Rm, Rn, Rd		F = add oneCSINV	Rm, Rn, Rd		F = NOTCSNEG	Rm, Rn, Rd		F = negate # OP Rn, RdRBIT	Rn, RdREV16REVCLZCLSRBITREV16REV32REVCLZCLS # OP Rm, Rn, RdUDIVSDIVLSLVLSRVASRVRORVCRC32[BHWX]CRC32C[BHWX] # OP Rm, Rn, Ra, RdMADDMSUBSMADDLSMSUBLSMULHUMADDLUMSUBLUMULH # logical shifted registerAND	Rm <shift> imm6, Rn, RdBICORRORNEOREONANDSBICS