.TH ATOM 2.SH NAMEainc, adec, cas, cas32, cas64, casp, casl, loadlink, storecond, _tas \- atomic RMW operations.SH SYNOPSIS.B #include <u.h>.br.B #include <libc.h>.PP.Blong ainc(long *addr);.PP.Blong adec(long *addr);.PP.Bint cas32(u32int *addr, u32int ov, u32int nv);.PP.Bint cas64(u64int *addr, u64int ov, u64int nv);.PP.Bint cas(int *addr, int ov, int nv);.PP.Bint casp(void **addr, void *ov, void *nv);.PP.Bint casl(ulong *addr, ulong ov, ulong nv);.PP.Bint _tas(ulong *addr);.PP.Bulong loadlink(ulong*);.PP.Bint storecond(ulong*, ulong);.SH DESCRIPTION.I Aincatomically increments the value pointed to by.I addrand returns the new value..PP.I Adecatomically decrements the value pointed to by.I addrand returns the new value..PP.IR Cas ,.IR cas32 ,.IR cas64 ,.IR casp ,and.I caslimplement.I Compare-and-Swapon, respectively,.IR int ,.IR u32int ,.IR u64int ,.IR void* ,and.IR ulongvalues.  The availability of these functions depends on the\s-2CPU\s0 architecture:  Pentium III and later, as well as AMD64have 64-bit CAS instructions.  Other architectures don't.ARM-5 processors and earlier do not have CAS (nor have they.I Load-Linkedor.I Store-Conditional ).These instructions are, however, emulated by the Plan 9 kernel.All other architectures have 32-bit CAS..PP.I _tasimplements.IR Test-and-Set ,which is available on all architectures and used for the implementationof kernel locks(see.IR lock (2)and.IR thread (2))..PP.I Loadlinkand.I Storecondaccess the.I load-linkedand.I store-conditionalinstructions present on MIPS (LL/SC), ARM (Strex/Ldrex), PowerPC (LWAR/STWCCC), Alpha (MOVLL, MOVLC).These are not present on Pentium or AMD64..PPOn the architectures that have.I load-linkedand.IR store-conditional ,these are used to implement.IR compare-and-swap ..SH SOURCE.B /sys/src/libc/*/atom.s.br.B /sys/src/libc/*/tas.s.SH SEE ALSO.IR semacquire (2),.IR lock (2),.IR thread (2).SH DIAGNOSTICSThe CAS functions,.IR _tas ,and.I storecondreturn 0 for failure and 1 for success.