; Copyright © 2018, VideoLAN and dav1d authors; Copyright © 2018, Two Orioles, LLC; All rights reserved.;; Redistribution and use in source and binary forms, with or without; modification, are permitted provided that the following conditions are met:;; 1. Redistributions of source code must retain the above copyright notice, this;    list of conditions and the following disclaimer.;; 2. Redistributions in binary form must reproduce the above copyright notice,;    this list of conditions and the following disclaimer in the documentation;    and/or other materials provided with the distribution.;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %include "config.asm"%include "ext/x86/x86inc.asm" %if ARCH_X86_64 SECTION_RODATA 32 wiener_shufA:  db  1,  7,  2,  8,  3,  9,  4, 10,  5, 11,  6, 12,  7, 13,  8, 14wiener_shufB:  db  2,  3,  3,  4,  4,  5,  5,  6,  6,  7,  7,  8,  8,  9,  9, 10wiener_shufC:  db  6,  5,  7,  6,  8,  7,  9,  8, 10,  9, 11, 10, 12, 11, 13, 12wiener_shufD:  db  4, -1,  5, -1,  6, -1,  7, -1,  8, -1,  9, -1, 10, -1, 11, -1wiener_l_shuf: db  4,  4,  4,  4,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15pb_0to31:      db  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15               db 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31pb_right_ext_mask: times 32 db 0xff                   times 32 db 0 pb_3:          times 4 db 3pb_m5:         times 4 db -5pw_16:         times 2 dw 16pw_256:        times 2 dw 256pw_2056:       times 2 dw 2056pw_m16380:     times 2 dw -16380pw_5_6:        dw 5, 6pd_1024:       dd 1024pd_0xf0080029: dd 0xf0080029pd_0xf00801c7: dd 0xf00801c7 cextern sgr_x_by_x SECTION .text %macro REPX 2-*    %xdefine %%f(x) %1%rep %0 - 1    %rotate 1    %%f(%1)%endrep%endmacro DECLARE_REG_TMP 4, 9, 7, 11, 12, 13, 14 ; wiener ring buffer pointers INIT_YMM avx2cglobal wiener_filter7, 5, 15, 16, -384*12-16, dst, dst_stride, left, lpf, \                                               lpf_stride, w, edge, flt, h    mov           fltq, fltmp    mov          edged, r8m    mov             wd, wm    mov             hd, r6m    vbroadcasti128  m6, [wiener_shufA]    vpbroadcastb   m11, [fltq+ 0] ; x0 x0    vbroadcasti128  m7, [wiener_shufB]    vpbroadcastd   m12, [fltq+ 2]    vbroadcasti128  m8, [wiener_shufC]    packsswb       m12, m12       ; x1 x2    vpbroadcastw   m13, [fltq+ 6] ; x3    vbroadcasti128  m9, [wiener_shufD]    add           lpfq, wq    vpbroadcastd   m10, [pw_m16380]    lea             t1, [rsp+wq*2+16]    vpbroadcastd   m14, [fltq+16] ; y0 y1    add           dstq, wq    vpbroadcastd   m15, [fltq+20] ; y2 y3    neg             wq    test         edgeb, 4 ; LR_HAVE_TOP    jz .no_top    call .h_top    add           lpfq, lpf_strideq    mov             t6, t1    mov             t5, t1    add             t1, 384*2    call .h_top    lea             r7, [lpfq+lpf_strideq*4]    mov           lpfq, dstq    mov             t4, t1    add             t1, 384*2    mov      [rsp+8*1], lpf_strideq    add             r7, lpf_strideq    mov      [rsp+8*0], r7 ; below    call .h    mov             t3, t1    mov             t2, t1    dec             hd    jz .v1    add           lpfq, dst_strideq    add             t1, 384*2    call .h    mov             t2, t1    dec             hd    jz .v2    add           lpfq, dst_strideq    add             t1, 384*2    call .h    dec             hd    jz .v3.main:    lea             t0, [t1+384*2].main_loop:    call .hv    dec             hd    jnz .main_loop    test         edgeb, 8 ; LR_HAVE_BOTTOM    jz .v3    mov           lpfq, [rsp+8*0]    call .hv_bottom    add           lpfq, [rsp+8*1]    call .hv_bottom.v1:    call .v    RET.no_top:    lea             r7, [lpfq+lpf_strideq*4]    mov           lpfq, dstq    mov      [rsp+8*1], lpf_strideq    lea             r7, [r7+lpf_strideq*2]    mov      [rsp+8*0], r7    call .h    mov             t6, t1    mov             t5, t1    mov             t4, t1    mov             t3, t1    mov             t2, t1    dec             hd    jz .v1    add           lpfq, dst_strideq    add             t1, 384*2    call .h    mov             t2, t1    dec             hd    jz .v2    add           lpfq, dst_strideq    add             t1, 384*2    call .h    dec             hd    jz .v3    lea             t0, [t1+384*2]    call .hv    dec             hd    jz .v3    add             t0, 384*8    call .hv    dec             hd    jnz .main.v3:    call .v.v2:    call .v    jmp .v1.extend_right:    movd           xm2, r10d    vpbroadcastd    m0, [pb_3]    vpbroadcastd    m1, [pb_m5]    vpbroadcastb    m2, xm2    movu            m3, [pb_0to31]    psubb           m0, m2    psubb           m1, m2    pminub          m0, m3    pminub          m1, m3    pshufb          m4, m0    pshufb          m5, m1    ret.h:    mov            r10, wq    test         edgeb, 1 ; LR_HAVE_LEFT    jz .h_extend_left    movd           xm4, [leftq]    vpblendd        m4, [lpfq+r10-4], 0xfe    add          leftq, 4    jmp .h_main.h_extend_left:    vbroadcasti128  m5, [lpfq+r10] ; avoid accessing memory located    mova            m4, [lpfq+r10] ; before the start of the buffer    palignr         m4, m5, 12    pshufb          m4, [wiener_l_shuf]    jmp .h_main.h_top:    mov            r10, wq    movu            m4, [lpfq+r10-4]    test         edgeb, 1 ; LR_HAVE_LEFT    jnz .h_main    pshufb          m4, [wiener_l_shuf]    jmp .h_main.h_loop:    movu            m4, [lpfq+r10-4].h_main:    movu            m5, [lpfq+r10+4]    test         edgeb, 2 ; LR_HAVE_RIGHT    jnz .h_have_right    cmp           r10d, -34    jl .h_have_right    call .extend_right.h_have_right:    pshufb          m0, m4, m6    pmaddubsw       m0, m11    pshufb          m1, m5, m6    pmaddubsw       m1, m11    pshufb          m2, m4, m7    pmaddubsw       m2, m12    pshufb          m3, m5, m7    pmaddubsw       m3, m12    paddw           m0, m2    pshufb          m2, m4, m8    pmaddubsw       m2, m12    paddw           m1, m3    pshufb          m3, m5, m8    pmaddubsw       m3, m12    pshufb          m4, m9    paddw           m0, m2    pmullw          m2, m4, m13    pshufb          m5, m9    paddw           m1, m3    pmullw          m3, m5, m13    psllw           m4, 7    psllw           m5, 7    paddw           m4, m10    paddw           m5, m10    paddw           m0, m2    vpbroadcastd    m2, [pw_2056]    paddw           m1, m3    paddsw          m0, m4    paddsw          m1, m5    psraw           m0, 3    psraw           m1, 3    paddw           m0, m2    paddw           m1, m2    mova [t1+r10*2+ 0], m0    mova [t1+r10*2+32], m1    add            r10, 32    jl .h_loop    retALIGN function_align.hv:    add           lpfq, dst_strideq    mov            r10, wq    test         edgeb, 1 ; LR_HAVE_LEFT    jz .hv_extend_left    movd           xm4, [leftq]    vpblendd        m4, [lpfq+r10-4], 0xfe    add          leftq, 4    jmp .hv_main.hv_extend_left:    movu            m4, [lpfq+r10-4]    pshufb          m4, [wiener_l_shuf]    jmp .hv_main.hv_bottom:    mov            r10, wq    test         edgeb, 1 ; LR_HAVE_LEFT    jz .hv_extend_left.hv_loop:    movu            m4, [lpfq+r10-4].hv_main:    movu            m5, [lpfq+r10+4]    test         edgeb, 2 ; LR_HAVE_RIGHT    jnz .hv_have_right    cmp           r10d, -34    jl .hv_have_right    call .extend_right.hv_have_right:    pshufb          m0, m4, m6    pmaddubsw       m0, m11    pshufb          m1, m5, m6    pmaddubsw       m1, m11    pshufb          m2, m4, m7    pmaddubsw       m2, m12    pshufb          m3, m5, m7    pmaddubsw       m3, m12    paddw           m0, m2    pshufb          m2, m4, m8    pmaddubsw       m2, m12    paddw           m1, m3    pshufb          m3, m5, m8    pmaddubsw       m3, m12    pshufb          m4, m9    paddw           m0, m2    pmullw          m2, m4, m13    pshufb          m5, m9    paddw           m1, m3    pmullw          m3, m5, m13    psllw           m4, 7    psllw           m5, 7    paddw           m4, m10    paddw           m5, m10    paddw           m0, m2    paddw           m1, m3    mova            m2, [t4+r10*2]    paddw           m2, [t2+r10*2]    mova            m3, [t3+r10*2]    paddsw          m0, m4    vpbroadcastd    m4, [pw_2056]    paddsw          m1, m5    mova            m5, [t5+r10*2]    paddw           m5, [t1+r10*2]    psraw           m0, 3    psraw           m1, 3    paddw           m0, m4    paddw           m1, m4    paddw           m4, m0, [t6+r10*2]    mova    [t0+r10*2], m0    punpcklwd       m0, m2, m3    pmaddwd         m0, m15    punpckhwd       m2, m3    pmaddwd         m2, m15    punpcklwd       m3, m4, m5    pmaddwd         m3, m14    punpckhwd       m4, m5    pmaddwd         m4, m14    paddd           m0, m3    paddd           m4, m2    mova            m2, [t4+r10*2+32]    paddw           m2, [t2+r10*2+32]    mova            m3, [t3+r10*2+32]    mova            m5, [t5+r10*2+32]    paddw           m5, [t1+r10*2+32]    psrad           m0, 11    psrad           m4, 11    packssdw        m0, m4    paddw           m4, m1, [t6+r10*2+32]    mova [t0+r10*2+32], m1    punpcklwd       m1, m2, m3    pmaddwd         m1, m15    punpckhwd       m2, m3    pmaddwd         m2, m15    punpcklwd       m3, m4, m5    pmaddwd         m3, m14    punpckhwd       m4, m5    pmaddwd         m4, m14    paddd           m1, m3    paddd           m2, m4    psrad           m1, 11    psrad           m2, 11    packssdw        m1, m2    packuswb        m0, m1    mova    [dstq+r10], m0    add            r10, 32    jl .hv_loop    mov             t6, t5    mov             t5, t4    mov             t4, t3    mov             t3, t2    mov             t2, t1    mov             t1, t0    mov             t0, t6    add           dstq, dst_strideq    ret.v:    mov            r10, wq.v_loop:    mova            m2, [t4+r10*2+ 0]    paddw           m2, [t2+r10*2+ 0]    mova            m4, [t3+r10*2+ 0]    mova            m6, [t1+r10*2+ 0]    paddw           m8, m6, [t6+r10*2+ 0]    paddw           m6, [t5+r10*2+ 0]    mova            m3, [t4+r10*2+32]    paddw           m3, [t2+r10*2+32]    mova            m5, [t3+r10*2+32]    mova            m7, [t1+r10*2+32]    paddw           m9, m7, [t6+r10*2+32]    paddw           m7, [t5+r10*2+32]    punpcklwd       m0, m2, m4    pmaddwd         m0, m15    punpckhwd       m2, m4    pmaddwd         m2, m15    punpcklwd       m4, m8, m6    pmaddwd         m4, m14    punpckhwd       m6, m8, m6    pmaddwd         m6, m14    punpcklwd       m1, m3, m5    pmaddwd         m1, m15    punpckhwd       m3, m5    pmaddwd         m3, m15    punpcklwd       m5, m9, m7    pmaddwd         m5, m14    punpckhwd       m7, m9, m7    pmaddwd         m7, m14    paddd           m0, m4    paddd           m2, m6    paddd           m1, m5    paddd           m3, m7    REPX {psrad x, 11}, m0, m2, m1, m3    packssdw        m0, m2    packssdw        m1, m3    packuswb        m0, m1    mova    [dstq+r10], m0    add            r10, 32    jl .v_loop    mov             t6, t5    mov             t5, t4    mov             t4, t3    mov             t3, t2    mov             t2, t1    add           dstq, dst_strideq    ret cglobal wiener_filter5, 5, 13, 16, 384*8+16, dst, dst_stride, left, lpf, \                                             lpf_stride, w, edge, flt, h    mov           fltq, fltmp    mov          edged, r8m    mov             wd, wm    mov             hd, r6m    vbroadcasti128  m6, [wiener_shufB]    vpbroadcastd   m12, [fltq+ 2]    vbroadcasti128  m7, [wiener_shufC]    packsswb       m12, m12       ; x1 x2    vpbroadcastw   m13, [fltq+ 6] ; x3    vbroadcasti128  m8, [wiener_shufD]    add           lpfq, wq    vpbroadcastd    m9, [pw_m16380]    vpbroadcastd   m10, [pw_2056]    lea             t1, [rsp+wq*2+16]    mova           m11, [wiener_l_shuf]    vpbroadcastd   m14, [fltq+16] ; __ y1    add           dstq, wq    vpbroadcastd   m15, [fltq+20] ; y2 y3    neg             wq    test         edgeb, 4 ; LR_HAVE_TOP    jz .no_top    call .h_top    add           lpfq, lpf_strideq    mov             t4, t1    add             t1, 384*2    call .h_top    lea             r7, [lpfq+lpf_strideq*4]    mov           lpfq, dstq    mov             t3, t1    add             t1, 384*2    mov      [rsp+8*1], lpf_strideq    add             r7, lpf_strideq    mov      [rsp+8*0], r7 ; below    call .h    mov             t2, t1    dec             hd    jz .v1    add           lpfq, dst_strideq    add             t1, 384*2    call .h    dec             hd    jz .v2.main:    mov             t0, t4.main_loop:    call .hv    dec             hd    jnz .main_loop    test         edgeb, 8 ; LR_HAVE_BOTTOM    jz .v2    mov           lpfq, [rsp+8*0]    call .hv_bottom    add           lpfq, [rsp+8*1]    call .hv_bottom.end:    RET.no_top:    lea             r7, [lpfq+lpf_strideq*4]    mov           lpfq, dstq    mov      [rsp+8*1], lpf_strideq    lea             r7, [r7+lpf_strideq*2]    mov      [rsp+8*0], r7    call .h    mov             t4, t1    mov             t3, t1    mov             t2, t1    dec             hd    jz .v1    add           lpfq, dst_strideq    add             t1, 384*2    call .h    dec             hd    jz .v2    lea             t0, [t1+384*2]    call .hv    dec             hd    jz .v2    add             t0, 384*6    call .hv

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