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riscv: Add sar, shr insn

fixes 92_enum_bitfield.

Michael Matz committed 7 years ago

Commit 215bc1a1 parent f64d4601 file · +6 −2Browse files

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riscv64-gen.c+6−2
@@ -621,8 +621,6 @@ static void gen_opil(int op, int ll) · 620 unmodified lines
621621 d = ireg(d);
622622 switch (op) {
623623 case '%':
624− case TOK_SAR:
625− case TOK_SHR:
626624 case TOK_PDIV:
627625 default:
628626 tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
@@ -633,6 +631,12 @@ static void gen_opil(int op, int ll) · 4 unmodified lines
633631 case '-':
634632 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b
635633 break;
634+ case TOK_SAR:
635+ o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12) | (1 << 30)); //sra d, a, b
636+ break;
637+ case TOK_SHR:
638+ o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12)); //srl d, a, b
639+ break;
636640 case TOK_SHL:
637641 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b
638642 break;

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