/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie *          Alex Deucher *          Jerome Glisse */#include <linux/ktime.h>#include <linux/module.h>#include <linux/overflow.h>#include <linux/pagemap.h>#include <linux/pci.h>#include <linux/dma-buf.h>#include <linux/dma-fence-unwrap.h>#include <linux/uaccess.h> #include <drm/amdgpu_drm.h>#include <drm/drm_drv.h>#include <drm/drm_exec.h>#include <drm/drm_gem_ttm_helper.h>#include <drm/ttm/ttm_tt.h>#include <drm/drm_syncobj.h> #include "amdgpu.h"#include "amdgpu_display.h"#include "amdgpu_dma_buf.h"#include "amdgpu_hmm.h"#include "amdgpu_xgmi.h"#include "amdgpu_vm.h" static intamdgpu_gem_add_input_fence(struct drm_file *filp,			   uint64_t syncobj_handles_array,			   uint32_t num_syncobj_handles){	struct dma_fence *fence;	uint32_t *syncobj_handles;	int ret, i; 	if (!num_syncobj_handles)		return 0; 	syncobj_handles = memdup_user(u64_to_user_ptr(syncobj_handles_array),				      size_mul(sizeof(uint32_t), num_syncobj_handles));	if (IS_ERR(syncobj_handles))		return PTR_ERR(syncobj_handles); 	for (i = 0; i < num_syncobj_handles; i++) { 		if (!syncobj_handles[i]) {			ret = -EINVAL;			goto free_memdup;		} 		ret = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, 0, &fence);		if (ret)			goto free_memdup; 		dma_fence_wait(fence, false); 		/* TODO: optimize async handling */		dma_fence_put(fence);	} free_memdup:	kfree(syncobj_handles);	return ret;} static intamdgpu_gem_update_timeline_node(struct drm_file *filp,				uint32_t syncobj_handle,				uint64_t point,				struct drm_syncobj **syncobj,				struct dma_fence_chain **chain){	if (!syncobj_handle)		return 0; 	/* Find the sync object */	*syncobj = drm_syncobj_find(filp, syncobj_handle);	if (!*syncobj)		return -ENOENT; 	if (!point)		return 0; 	/* Allocate the chain node */	*chain = dma_fence_chain_alloc();	if (!*chain) {		drm_syncobj_put(*syncobj);		*syncobj = NULL;		return -ENOMEM;	} 	return 0;} static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf){	struct ttm_buffer_object *bo = vmf->vma->vm_private_data;	struct drm_device *ddev = bo->base.dev;	vm_fault_t ret;	int idx; 	ret = ttm_bo_vm_reserve(bo, vmf);	if (ret)		return ret; 	if (drm_dev_enter(ddev, &idx)) {		ret = amdgpu_bo_fault_reserve_notify(bo);		if (ret) {			drm_dev_exit(idx);			goto unlock;		} 		ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,					       TTM_BO_VM_NUM_PREFAULT); 		drm_dev_exit(idx);	} else {		ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);	}	if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))		return ret; unlock:	dma_resv_unlock(bo->base.resv);	return ret;} static const struct vm_operations_struct amdgpu_gem_vm_ops = {	.fault = amdgpu_gem_fault,	.open = ttm_bo_vm_open,	.close = ttm_bo_vm_close,	.access = ttm_bo_vm_access}; static void amdgpu_gem_object_free(struct drm_gem_object *gobj){	struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); 	amdgpu_hmm_unregister(aobj);	ttm_bo_fini(&aobj->tbo);} int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,			     int alignment, u32 initial_domain,			     u64 flags, enum ttm_bo_type type,			     struct dma_resv *resv,			     struct drm_gem_object **obj, int8_t xcp_id_plus1){	struct amdgpu_bo *bo;	struct amdgpu_bo_user *ubo;	struct amdgpu_bo_param bp;	int r; 	memset(&bp, 0, sizeof(bp));	*obj = NULL;	flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 	bp.size = size;	bp.byte_align = alignment;	bp.type = type;	bp.resv = resv;	bp.preferred_domain = initial_domain;	bp.flags = flags;	bp.domain = initial_domain;	bp.bo_ptr_size = sizeof(struct amdgpu_bo);	bp.xcp_id_plus1 = xcp_id_plus1; 	r = amdgpu_bo_create_user(adev, &bp, &ubo);	if (r)		return r; 	bo = &ubo->bo;	*obj = &bo->tbo.base; 	return 0;} void amdgpu_gem_force_release(struct amdgpu_device *adev){	struct drm_device *ddev = adev_to_drm(adev);	struct drm_file *file; 	mutex_lock(&ddev->filelist_mutex); 	list_for_each_entry(file, &ddev->filelist, lhead) {		struct drm_gem_object *gobj;		int handle; 		WARN_ONCE(1, "Still active user space clients!\n");		spin_lock(&file->table_lock);		idr_for_each_entry(&file->object_idr, gobj, handle) {			WARN_ONCE(1, "And also active allocations!\n");			drm_gem_object_put(gobj);		}		idr_destroy(&file->object_idr);		spin_unlock(&file->table_lock);	} 	mutex_unlock(&ddev->filelist_mutex);} /* * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */static int amdgpu_gem_object_open(struct drm_gem_object *obj,				  struct drm_file *file_priv){	struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;	struct amdgpu_vm *vm = &fpriv->vm;	struct amdgpu_bo_va *bo_va;	struct mm_struct *mm;	struct drm_exec exec;	int r; 	mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);	if (mm && mm != current->mm)		return -EPERM; 	if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&	    !amdgpu_vm_is_bo_always_valid(vm, abo))		return -EPERM; 	drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);	drm_exec_until_all_locked(&exec) {		r = drm_exec_prepare_obj(&exec, &abo->tbo.base, TTM_NUM_MOVE_FENCES + 1);		drm_exec_retry_on_contention(&exec);		if (unlikely(r))			goto out_unlock; 		r = amdgpu_vm_lock_pd(vm, &exec, 0);		drm_exec_retry_on_contention(&exec);		if (unlikely(r))			goto out_unlock;	} 	amdgpu_vm_bo_update_shared(abo);	bo_va = amdgpu_vm_bo_find(vm, abo);	if (!bo_va) {		bo_va = amdgpu_vm_bo_add(adev, vm, abo);		r = amdgpu_evf_mgr_attach_fence(&fpriv->evf_mgr, abo);		if (r)			goto out_unlock;	} else {		++bo_va->ref_count;	} 	drm_exec_fini(&exec); 	/* Validate and add eviction fence to DMABuf imports with dynamic	 * attachment in compute VMs. Re-validation will be done by	 * amdgpu_vm_validate. Fences are on the reservation shared with the	 * export, which is currently required to be validated and fenced	 * already by amdgpu_amdkfd_gpuvm_restore_process_bos.	 *	 * Nested locking below for the case that a GEM object is opened in	 * kfd_mem_export_dmabuf. Since the lock below is only taken for imports,	 * but not for export, this is a different lock class that cannot lead to	 * circular lock dependencies.	 */	if (!vm->is_compute_context || !vm->process_info)		return 0;	if (!drm_gem_is_imported(obj) ||	    !dma_buf_is_dynamic(obj->import_attach->dmabuf))		return 0;	mutex_lock_nested(&vm->process_info->lock, 1);	if (!WARN_ON(!vm->process_info->eviction_fence)) {		r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT,							&vm->process_info->eviction_fence->base);		if (r) {			struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm); 			dev_warn(adev->dev, "validate_and_fence failed: %d\n", r);			if (ti) {				dev_warn(adev->dev, "pid %d\n", ti->task.pid);				amdgpu_vm_put_task_info(ti);			}		}	}	mutex_unlock(&vm->process_info->lock);	return r; out_unlock:	drm_exec_fini(&exec);	return r;} static void amdgpu_gem_object_close(struct drm_gem_object *obj,				    struct drm_file *file_priv){	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;	struct amdgpu_vm *vm = &fpriv->vm; 	struct dma_fence *fence = NULL;	struct amdgpu_bo_va *bo_va;	struct drm_exec exec;	long r; 	drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);	drm_exec_until_all_locked(&exec) {		r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);		drm_exec_retry_on_contention(&exec);		if (unlikely(r))			goto out_unlock; 		r = amdgpu_vm_lock_pd(vm, &exec, 0);		drm_exec_retry_on_contention(&exec);		if (unlikely(r))			goto out_unlock;	} 	if (!amdgpu_vm_is_bo_always_valid(vm, bo))		amdgpu_evf_mgr_detach_fence(&fpriv->evf_mgr, bo); 	bo_va = amdgpu_vm_bo_find(vm, bo);	if (!bo_va || --bo_va->ref_count)		goto out_unlock; 	amdgpu_vm_bo_del(adev, bo_va);	amdgpu_vm_bo_update_shared(bo);	if (!amdgpu_vm_ready(vm))		goto out_unlock; 	r = amdgpu_vm_clear_freed(adev, vm, &fence);	if (unlikely(r < 0) && !drm_dev_is_unplugged(adev_to_drm(adev)))		dev_err(adev->dev, "failed to clear page "			"tables on GEM object close (%ld)\n", r);	if (r || !fence)		goto out_unlock; 	amdgpu_bo_fence(bo, fence, true);	dma_fence_put(fence); out_unlock:	if (r && !drm_dev_is_unplugged(adev_to_drm(adev)))		dev_err(adev->dev, "leaking bo va (%ld)\n", r);	drm_exec_fini(&exec);} static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma){	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))		return -EPERM;	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)		return -EPERM; 	/* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings	 * for debugger access to invisible VRAM. Should have used MAP_SHARED	 * instead. Clearing VM_MAYWRITE prevents the mapping from ever	 * becoming writable and makes vma_is_cow_mapping(vma) false.	 */	if (vma_is_cow_mapping(vma) &&	    !(vma->vm_flags & VM_ACCESS_FLAGS))		vm_flags_clear(vma, VM_MAYWRITE); 	return drm_gem_ttm_mmap(obj, vma);} const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {	.free = amdgpu_gem_object_free,	.open = amdgpu_gem_object_open,	.close = amdgpu_gem_object_close,	.export = amdgpu_gem_prime_export,	.vmap = drm_gem_ttm_vmap,	.vunmap = drm_gem_ttm_vunmap,	.mmap = amdgpu_gem_object_mmap,	.vm_ops = &amdgpu_gem_vm_ops,}; static bool amdgpu_gem_are_domains_valid(u32 domains){	u32 normal = AMDGPU_GEM_DOMAIN_CPU |		     AMDGPU_GEM_DOMAIN_GTT |		     AMDGPU_GEM_DOMAIN_VRAM;	/* Treat all non CPU/GTT/VRAM domains as special domains. */	u32 special = AMDGPU_GEM_DOMAIN_MASK & ~normal;	u32 normal_mask = domains & normal;	u32 special_mask = domains & special; 	if (!special_mask)		return true; 	if (normal_mask)		return false; 	return !(special_mask & (special_mask - 1));} /* * GEM ioctls. */int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,			    struct drm_file *filp){	struct amdgpu_device *adev = drm_to_adev(dev);	struct amdgpu_fpriv *fpriv = filp->driver_priv;	struct amdgpu_vm *vm = &fpriv->vm;	union drm_amdgpu_gem_create *args = data;	uint64_t flags = args->in.domain_flags;	uint64_t size = args->in.bo_size;	struct dma_resv *resv = NULL;	struct drm_gem_object *gobj;	uint32_t handle, initial_domain;	int r; 	/* reject invalid gem flags */	if (flags & ~AMDGPU_GEM_CREATE_SETTABLE_MASK)		return -EINVAL; 	/* reject invalid gem domains */	if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)		return -EINVAL;	if (!amdgpu_gem_are_domains_valid(args->in.domains))		return -EINVAL; 	if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {		DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");		return -EINVAL;	} 	/* always clear VRAM */	flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 	/* create a gem object to contain this object in */	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {		if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {			/* if gds bo is created from user space, it must be			 * passed to bo list			 */			DRM_ERROR("GDS bo cannot be per-vm-bo\n");			return -EINVAL;		}		flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;	} 	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {		r = amdgpu_bo_reserve(vm->root.bo, false);		if (r)			return r; 		resv = vm->root.bo->tbo.base.resv;	} 	initial_domain = (u32)(0xffffffff & args->in.domains);retry:	r = amdgpu_gem_object_create(adev, size, args->in.alignment,				     initial_domain,				     flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);	if (r && r != -ERESTARTSYS) {		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {			flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;			goto retry;		} 		if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {			initial_domain |= AMDGPU_GEM_DOMAIN_GTT;			goto retry;		}		DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",				size, initial_domain, args->in.alignment, r);	} 	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {		if (!r) {			struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 			abo->parent = amdgpu_bo_ref(vm->root.bo);		}		amdgpu_bo_unreserve(vm->root.bo);

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