/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * */#ifndef _AMDGPU_RAS_H#define _AMDGPU_RAS_H #include <linux/debugfs.h>#include <linux/list.h>#include <linux/kfifo.h>#include <linux/radix-tree.h>#include "ta_ras_if.h"#include "amdgpu_ras_eeprom.h"#include "amdgpu_smuio.h" struct amdgpu_iv_entry; #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x)		AMDGPU_GET_REG_FIELD(x, 0, 0)#define AMDGPU_RAS_GPU_ERR_FW_LOAD(x)			AMDGPU_GET_REG_FIELD(x, 1, 1)#define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 2, 2)#define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 3, 3)#define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 4, 4)#define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 5, 5)#define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x)		AMDGPU_GET_REG_FIELD(x, 6, 6)#define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x)		AMDGPU_GET_REG_FIELD(x, 7, 7)#define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x)			AMDGPU_GET_REG_FIELD(x, 10, 8)#define AMDGPU_RAS_GPU_ERR_AID_ID(x)			AMDGPU_GET_REG_FIELD(x, 12, 11)#define AMDGPU_RAS_GPU_ERR_HBM_ID(x)			AMDGPU_GET_REG_FIELD(x, 14, 13)#define AMDGPU_RAS_GPU_ERR_DATA_ABORT(x)		AMDGPU_GET_REG_FIELD(x, 29, 29)#define AMDGPU_RAS_GPU_ERR_GENERIC(x)			AMDGPU_GET_REG_FIELD(x, 30, 30) #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT	100#define AMDGPU_RAS_BOOT_STEADY_STATUS		0xBA#define AMDGPU_RAS_BOOT_STATUS_MASK		0xFF #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS		(0x1 << 0)/* position of instance value in sub_block_index of * ta_ras_trigger_error_input, the sub block uses lower 12 bits */#define AMDGPU_RAS_INST_MASK 0xfffff000#define AMDGPU_RAS_INST_SHIFT 0xc #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29#define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 /* Reserve 8 physical dram row for possible retirement. * In worst cases, it will lose 8 * 2MB memory in vram domain */#define AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT	(16ULL << 20)/* The high three bits indicates socketid */#define AMDGPU_RAS_GET_FEATURES(val)  ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) #define RAS_EVENT_INVALID_ID		(BIT_ULL(63))#define RAS_EVENT_ID_IS_VALID(x)	(!((x) & BIT_ULL(63))) #define RAS_EVENT_LOG(adev, id, fmt, ...)	\	amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__) #define amdgpu_ras_mark_ras_event(adev, type)	\	(amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0))) enum amdgpu_ras_block {	AMDGPU_RAS_BLOCK__UMC = 0,	AMDGPU_RAS_BLOCK__SDMA,	AMDGPU_RAS_BLOCK__GFX,	AMDGPU_RAS_BLOCK__MMHUB,	AMDGPU_RAS_BLOCK__ATHUB,	AMDGPU_RAS_BLOCK__PCIE_BIF,	AMDGPU_RAS_BLOCK__HDP,	AMDGPU_RAS_BLOCK__XGMI_WAFL,	AMDGPU_RAS_BLOCK__DF,	AMDGPU_RAS_BLOCK__SMN,	AMDGPU_RAS_BLOCK__SEM,	AMDGPU_RAS_BLOCK__MP0,	AMDGPU_RAS_BLOCK__MP1,	AMDGPU_RAS_BLOCK__FUSE,	AMDGPU_RAS_BLOCK__MCA,	AMDGPU_RAS_BLOCK__VCN,	AMDGPU_RAS_BLOCK__JPEG,	AMDGPU_RAS_BLOCK__IH,	AMDGPU_RAS_BLOCK__MPIO,	AMDGPU_RAS_BLOCK__MMSCH, 	AMDGPU_RAS_BLOCK__LAST,	AMDGPU_RAS_BLOCK__ANY = -1}; enum amdgpu_ras_mca_block {	AMDGPU_RAS_MCA_BLOCK__MP0 = 0,	AMDGPU_RAS_MCA_BLOCK__MP1,	AMDGPU_RAS_MCA_BLOCK__MPIO,	AMDGPU_RAS_MCA_BLOCK__IOHC, 	AMDGPU_RAS_MCA_BLOCK__LAST}; #define AMDGPU_RAS_BLOCK_COUNT	AMDGPU_RAS_BLOCK__LAST#define AMDGPU_RAS_MCA_BLOCK_COUNT	AMDGPU_RAS_MCA_BLOCK__LAST#define AMDGPU_RAS_BLOCK_MASK	((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) enum amdgpu_ras_gfx_subblock {	/* CPC */	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =		AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =		AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,	/* CPF */	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =		AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,	/* CPG */	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =		AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,	/* GDS */	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =		AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,	/* SPI */	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,	/* SQ */	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,	/* SQC (3 ranges) */	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,	/* SQC range 0 */	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,	/* SQC range 1 */	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,	/* SQC range 2 */	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,	/* TA */	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =		AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,	/* TCA */	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =		AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =		AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,	/* TCC (5 sub-ranges) */	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,	/* TCC range 0 */	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =		AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,	/* TCC range 1 */	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =		AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,	/* TCC range 2 */	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =		AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,	/* TCC range 3 */	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =		AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,	/* TCC range 4 */	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =		AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,	/* TCI */	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,	/* TCP */	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =		AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =		AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,	/* TD */	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =		AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,	/* EA (3 sub-ranges) */	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,	/* EA range 0 */	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =		AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =		AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,	/* EA range 1 */	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =		AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,	/* EA range 2 */	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =		AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,	/* UTC VM L2 bank */	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,	/* UTC VM walker */	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,	/* UTC ATC L2 2MB cache */	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,	/* UTC ATC L2 4KB cache */	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,	AMDGPU_RAS_BLOCK__GFX_MAX}; enum amdgpu_ras_error_type {	AMDGPU_RAS_ERROR__NONE							= 0,	AMDGPU_RAS_ERROR__PARITY						= 1,	AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE					= 2,	AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE					= 4,	AMDGPU_RAS_ERROR__POISON						= 8,}; enum amdgpu_ras_ret {	AMDGPU_RAS_SUCCESS = 0,	AMDGPU_RAS_FAIL,	AMDGPU_RAS_UE,	AMDGPU_RAS_CE,	AMDGPU_RAS_PT,}; enum amdgpu_ras_error_query_mode {	AMDGPU_RAS_INVALID_ERROR_QUERY		= 0,	AMDGPU_RAS_DIRECT_ERROR_QUERY		= 1,	AMDGPU_RAS_FIRMWARE_ERROR_QUERY		= 2,	AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY	= 3,}; /* ras error status reisger fields */#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT	0x0#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK	0x00000001L#define ERR_STATUS_LO__MEMORY_ID__SHIFT			0x18#define ERR_STATUS_LO__MEMORY_ID_MASK			0xFF000000L#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT	0x2#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK		0x00000004L#define ERR_STATUS__ERR_CNT__SHIFT			0x17#define ERR_STATUS__ERR_CNT_MASK			0x03800000L #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \	ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \	(adev->reg_offset[hwip][ip_inst][segment] + (reg)) #define AMDGPU_RAS_ERR_INFO_VALID	(1 << 0)#define AMDGPU_RAS_ERR_STATUS_VALID	(1 << 1)#define AMDGPU_RAS_ERR_ADDRESS_VALID	(1 << 2) #define AMDGPU_RAS_GPU_RESET_MODE2_RESET  (0x1 << 0)#define AMDGPU_RAS_GPU_RESET_MODE1_RESET  (0x1 << 1) struct amdgpu_ras_err_status_reg_entry {	uint32_t hwip;	uint32_t ip_inst;	uint32_t seg_lo;	uint32_t reg_lo;	uint32_t seg_hi;	uint32_t reg_hi;	uint32_t reg_inst;	uint32_t flags;	const char *block_name;}; struct amdgpu_ras_memory_id_entry {	uint32_t memory_id;	const char *name;}; struct ras_common_if {	enum amdgpu_ras_block block;	enum amdgpu_ras_error_type type;	uint32_t sub_block_index;	char name[32];}; #define MAX_UMC_CHANNEL_NUM 32 struct ecc_info_per_ch {	uint16_t ce_count_lo_chip;	uint16_t ce_count_hi_chip;	uint64_t mca_umc_status;	uint64_t mca_umc_addr;	uint64_t mca_ceumc_addr;}; struct umc_ecc_info {	struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 	/* Determine smu ecctable whether support	 * record correctable error address	 */	int record_ce_addr_supported;}; enum ras_event_type {	RAS_EVENT_TYPE_INVALID = 0,	RAS_EVENT_TYPE_FATAL,	RAS_EVENT_TYPE_POISON_CREATION,	RAS_EVENT_TYPE_POISON_CONSUMPTION,	RAS_EVENT_TYPE_COUNT,}; struct ras_event_state {	u64 last_seqno;	atomic64_t count;}; struct ras_event_manager {	atomic64_t seqno;	struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT];}; struct ras_event_id {	enum ras_event_type type;	u64 event_id;}; struct ras_query_context {	struct ras_event_id evid;}; typedef int (*pasid_notify)(struct amdgpu_device *adev,		uint16_t pasid, void *data); struct ras_err_pages {	uint32_t count;	uint64_t *pfn;}; struct ras_ecc_err {	uint64_t status;	uint64_t ipid;	uint64_t addr;	uint64_t pa_pfn;	/* save global channel index across all UMC instances */	uint32_t channel_idx;	struct ras_err_pages err_pages;}; struct ras_ecc_log_info {	struct mutex lock;	struct radix_tree_root de_page_tree;}; struct ras_critical_region {	struct list_head node;	struct amdgpu_bo *bo;	uint64_t start;	uint64_t size;}; struct amdgpu_ras {	void *ras_mgr;	/* ras infrastructure */	/* for ras itself. */	uint32_t features;	uint32_t schema;

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