/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu_ras_eeprom.h"#include "amdgpu.h"#include "amdgpu_ras.h"#include <linux/bits.h>#include "atom.h"#include "amdgpu_eeprom.h"#include "amdgpu_atomfirmware.h"#include <linux/debugfs.h>#include <linux/uaccess.h> #include "amdgpu_reset.h"#include "amdgpu_ras_mgr.h" /* These are memory addresses as would be seen by one or more EEPROM * chips strung on the I2C bus, usually by manipulating pins 1-3 of a * set of EEPROM devices. They form a continuous memory space. * * The I2C device address includes the device type identifier, 1010b, * which is a reserved value and indicates that this is an I2C EEPROM * device. It also includes the top 3 bits of the 19 bit EEPROM memory * address, namely bits 18, 17, and 16. This makes up the 7 bit * address sent on the I2C bus with bit 0 being the direction bit, * which is not represented here, and sent by the hardware directly. * * For instance, * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. * Depending on the size of the I2C EEPROM device(s), bits 18:16 may * address memory in a device or a device on the I2C bus, depending on * the status of pins 1-3. See top of amdgpu_eeprom.c. * * The RAS table lives either at address 0 or address 40000h of EEPROM. */#define EEPROM_I2C_MADDR_0 0x0#define EEPROM_I2C_MADDR_4 0x40000 /* * The 2 macros below represent the actual size in bytes that * those entities occupy in the EEPROM memory. * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which * uses uint64 to store 6b fields such as retired_page. */#define RAS_TABLE_HEADER_SIZE 20#define RAS_TABLE_RECORD_SIZE 24 /* Table hdr is 'AMDR' */#define RAS_TABLE_HDR_VAL 0x414d4452 /* Bad GPU tag ‘BADG’ */#define RAS_TABLE_HDR_BAD 0x42414447 /* * EEPROM Table structure v1 * --------------------------------- * | | * | EEPROM TABLE HEADER | * | ( size 20 Bytes ) | * | | * --------------------------------- * | | * | BAD PAGE RECORD AREA | * | | * --------------------------------- */ /* Assume 2-Mbit size EEPROM and take up the whole space. */#define RAS_TBL_SIZE_BYTES (256 * 1024)#define RAS_TABLE_START 0#define RAS_HDR_START RAS_TABLE_START#define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)#define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ / RAS_TABLE_RECORD_SIZE) /* * EEPROM Table structrue v2.1 * --------------------------------- * | | * | EEPROM TABLE HEADER | * | ( size 20 Bytes ) | * | | * --------------------------------- * | | * | EEPROM TABLE RAS INFO | * | (available info size 4 Bytes) | * | ( reserved size 252 Bytes ) | * | | * --------------------------------- * | | * | BAD PAGE RECORD AREA | * | | * --------------------------------- */ /* EEPROM Table V2_1 */#define RAS_TABLE_V2_1_INFO_SIZE 256#define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE#define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ RAS_TABLE_V2_1_INFO_SIZE)#define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ RAS_TABLE_V2_1_INFO_SIZE) \ / RAS_TABLE_RECORD_SIZE) /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM * offset off of RAS_TABLE_START. That is, this is something you can * add to control->i2c_address, and then tell I2C layer to read * from/write to there. _N is the so called absolute index, * because it starts right after the table header. */#define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ (_N) * RAS_TABLE_RECORD_SIZE) #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off * of "fri", return the absolute record index off of the end of * the table header. */#define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ (_C)->ras_max_record_count) #define RAS_NUM_RECS(_tbl_hdr) \ (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE) ? 0u : \ (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)) #define RAS_NUM_RECS_V2_1(_tbl_hdr) \ (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE + \ RAS_TABLE_V2_1_INFO_SIZE) ? 0u : \ (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE - \ RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)) #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) static bool __is_ras_eeprom_supported(struct amdgpu_device *adev){ if (amdgpu_sriov_vf(adev)) return false; switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ case IP_VERSION(11, 0, 7): /* Sienna cichlid */ case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 2): /* Aldebaran */ case IP_VERSION(13, 0, 10): return true; case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): return (adev->gmc.is_app_apu) ? false : true; default: return false; }} static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, struct amdgpu_ras_eeprom_control *control){ struct atom_context *atom_ctx = adev->mode_info.atom_context; u8 i2c_addr; if (!control) return false; if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { /* The address given by VBIOS is an 8-bit, wire-format * address, i.e. the most significant byte. * * Normalize it to a 19-bit EEPROM address. Remove the * device type identifier and make it a 7-bit address; * then make it a 19-bit EEPROM address. See top of * amdgpu_eeprom.c. */ i2c_addr = (i2c_addr & 0x0F) >> 1; control->i2c_address = ((u32) i2c_addr) << 16; return true; } switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ if (adev->asic_type == CHIP_VEGA20) control->i2c_address = EEPROM_I2C_MADDR_0; else if (strnstr(atom_ctx->vbios_pn, "D342", sizeof(atom_ctx->vbios_pn))) control->i2c_address = EEPROM_I2C_MADDR_0; else control->i2c_address = EEPROM_I2C_MADDR_4; return true; case IP_VERSION(11, 0, 7): control->i2c_address = EEPROM_I2C_MADDR_0; return true; case IP_VERSION(13, 0, 2): if (strnstr(atom_ctx->vbios_pn, "D673", sizeof(atom_ctx->vbios_pn))) control->i2c_address = EEPROM_I2C_MADDR_4; else control->i2c_address = EEPROM_I2C_MADDR_0; return true; case IP_VERSION(13, 0, 0): if (strnstr(atom_ctx->vbios_pn, "D707", sizeof(atom_ctx->vbios_pn))) control->i2c_address = EEPROM_I2C_MADDR_0; else control->i2c_address = EEPROM_I2C_MADDR_4; return true; case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): control->i2c_address = EEPROM_I2C_MADDR_4; return true; default: return false; }} static void__encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, unsigned char *buf){ u32 *pp = (uint32_t *)buf; pp[0] = cpu_to_le32(hdr->header); pp[1] = cpu_to_le32(hdr->version); pp[2] = cpu_to_le32(hdr->first_rec_offset); pp[3] = cpu_to_le32(hdr->tbl_size); pp[4] = cpu_to_le32(hdr->checksum);} static void__decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, unsigned char *buf){ u32 *pp = (uint32_t *)buf; hdr->header = le32_to_cpu(pp[0]); hdr->version = le32_to_cpu(pp[1]); hdr->first_rec_offset = le32_to_cpu(pp[2]); hdr->tbl_size = le32_to_cpu(pp[3]); hdr->checksum = le32_to_cpu(pp[4]);} static int __write_table_header(struct amdgpu_ras_eeprom_control *control){ u8 buf[RAS_TABLE_HEADER_SIZE]; struct amdgpu_device *adev = to_amdgpu_device(control); int res; memset(buf, 0, sizeof(buf)); __encode_table_header_to_buf(&control->tbl_hdr, buf); /* i2c may be unstable in gpu reset */ down_read(&adev->reset_domain->sem); res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, control->i2c_address + control->ras_header_offset, buf, RAS_TABLE_HEADER_SIZE); up_read(&adev->reset_domain->sem); if (res < 0) { dev_err(adev->dev, "Failed to write EEPROM table header:%d", res); } else if (res < RAS_TABLE_HEADER_SIZE) { dev_err(adev->dev, "Short write:%d out of %d\n", res, RAS_TABLE_HEADER_SIZE); res = -EIO; } else { res = 0; } return res;} static void__encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, unsigned char *buf){ u32 *pp = (uint32_t *)buf; u32 tmp; tmp = ((uint32_t)(rai->rma_status) & 0xFF) | (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); pp[0] = cpu_to_le32(tmp);} static void__decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, unsigned char *buf){ u32 *pp = (uint32_t *)buf; u32 tmp; tmp = le32_to_cpu(pp[0]); rai->rma_status = tmp & 0xFF; rai->health_percent = (tmp >> 8) & 0xFF; rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF;} static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control){ struct amdgpu_device *adev = to_amdgpu_device(control); u8 *buf; int res; buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); if (!buf) { dev_err(adev->dev, "Failed to alloc buf to write table ras info\n"); return -ENOMEM; } __encode_table_ras_info_to_buf(&control->tbl_rai, buf); /* i2c may be unstable in gpu reset */ down_read(&adev->reset_domain->sem); res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, control->i2c_address + control->ras_info_offset, buf, RAS_TABLE_V2_1_INFO_SIZE); up_read(&adev->reset_domain->sem); if (res < 0) { dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", res); } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { dev_err(adev->dev, "Short write:%d out of %d\n", res, RAS_TABLE_V2_1_INFO_SIZE); res = -EIO; } else { res = 0; } kfree(buf); return res;} static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control){ int ii; u8 *pp, csum; size_t sz; /* Header checksum, skip checksum field in the calculation */ sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); pp = (u8 *) &control->tbl_hdr; csum = 0; for (ii = 0; ii < sz; ii++, pp++) csum += *pp; return csum;} static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control){ int ii; u8 *pp, csum; size_t sz; sz = sizeof(control->tbl_rai); pp = (u8 *) &control->tbl_rai; csum = 0; for (ii = 0; ii < sz; ii++, pp++) csum += *pp; return csum;} static int amdgpu_ras_eeprom_correct_header_tag( struct amdgpu_ras_eeprom_control *control, uint32_t header){ struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; u8 *hh; int res; u8 csum; csum = -hdr->checksum; hh = (void *) &hdr->header; csum -= (hh[0] + hh[1] + hh[2] + hh[3]); hh = (void *) &header; csum += hh[0] + hh[1] + hh[2] + hh[3]; csum = -csum; mutex_lock(&control->ras_tbl_mutex); hdr->header = header; hdr->checksum = csum; res = __write_table_header(control); mutex_unlock(&control->ras_tbl_mutex); return res;} static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control){ struct amdgpu_device *adev = to_amdgpu_device(control); struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { case IP_VERSION(8, 10, 0): hdr->version = RAS_TABLE_VER_V2_1; return; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 5, 0): hdr->version = RAS_TABLE_VER_V3; return; default: hdr->version = RAS_TABLE_VER_V1; return; }} /** * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table * @control: pointer to control structure * * Reset the contents of the header of the RAS EEPROM table. * Return 0 on success, -errno on error. */int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control){ struct amdgpu_device *adev = to_amdgpu_device(control); struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; struct amdgpu_ras *con = amdgpu_ras_get_context(adev); u8 csum; int res; mutex_lock(&control->ras_tbl_mutex); hdr->header = RAS_TABLE_HDR_VAL; amdgpu_ras_set_eeprom_table_version(control); if (hdr->version >= RAS_TABLE_VER_V2_1) { hdr->first_rec_offset = RAS_RECORD_START_V2_1; hdr->tbl_size = RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE; rai->rma_status = GPU_HEALTH_USABLE; control->ras_record_offset = RAS_RECORD_START_V2_1; control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; /** * GPU health represented as a percentage. * 0 means worst health, 100 means fully health. */ rai->health_percent = 100; /* ecc_page_threshold = 0 means disable bad page retirement */ rai->ecc_page_threshold = con->bad_page_cnt_threshold; } else { hdr->first_rec_offset = RAS_RECORD_START; hdr->tbl_size = RAS_TABLE_HEADER_SIZE; control->ras_record_offset = RAS_RECORD_START; control->ras_max_record_count = RAS_MAX_RECORD_COUNT; } csum = __calc_hdr_byte_sum(control); if (hdr->version >= RAS_TABLE_VER_V2_1) csum += __calc_ras_info_byte_sum(control); csum = -csum; hdr->checksum = csum; res = __write_table_header(control); if (!res && hdr->version > RAS_TABLE_VER_V1) res = __write_table_ras_info(control); control->ras_num_recs = 0; control->ras_num_bad_pages = 0; control->ras_num_mca_recs = 0; control->ras_num_pa_recs = 0; control->ras_fri = 0; amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); Lines 1–500 of 1718. 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/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu_ras_eeprom.h" #include "amdgpu.h" #include "amdgpu_ras.h" #include <linux/bits.h> #include "atom.h" #include "amdgpu_eeprom.h" #include "amdgpu_atomfirmware.h" #include <linux/debugfs.h> #include <linux/uaccess.h> #include "amdgpu_reset.h" #include "amdgpu_ras_mgr.h" /* These are memory addresses as would be seen by one or more EEPROM * chips strung on the I2C bus, usually by manipulating pins 1-3 of a * set of EEPROM devices. They form a continuous memory space. * * The I2C device address includes the device type identifier, 1010b, * which is a reserved value and indicates that this is an I2C EEPROM * device. It also includes the top 3 bits of the 19 bit EEPROM memory * address, namely bits 18, 17, and 16. This makes up the 7 bit * address sent on the I2C bus with bit 0 being the direction bit, * which is not represented here, and sent by the hardware directly. * * For instance, * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. * Depending on the size of the I2C EEPROM device(s), bits 18:16 may * address memory in a device or a device on the I2C bus, depending on * the status of pins 1-3. See top of amdgpu_eeprom.c. * * The RAS table lives either at address 0 or address 40000h of EEPROM. */ #define EEPROM_I2C_MADDR_0 0x0 #define EEPROM_I2C_MADDR_4 0x40000 /* * The 2 macros below represent the actual size in bytes that * those entities occupy in the EEPROM memory. * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which * uses uint64 to store 6b fields such as retired_page. */ #define RAS_TABLE_HEADER_SIZE 20 #define RAS_TABLE_RECORD_SIZE 24 /* Table hdr is 'AMDR' */ #define RAS_TABLE_HDR_VAL 0x414d4452 /* Bad GPU tag ‘BADG’ */ #define RAS_TABLE_HDR_BAD 0x42414447 /* * EEPROM Table structure v1 * --------------------------------- * | | * | EEPROM TABLE HEADER | * | ( size 20 Bytes ) | * | | * --------------------------------- * | | * | BAD PAGE RECORD AREA | * | | * --------------------------------- */ /* Assume 2-Mbit size EEPROM and take up the whole space. */ #define RAS_TBL_SIZE_BYTES (256 * 1024) #define RAS_TABLE_START 0 #define RAS_HDR_START RAS_TABLE_START #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ / RAS_TABLE_RECORD_SIZE) /* * EEPROM Table structrue v2.1 * --------------------------------- * | | * | EEPROM TABLE HEADER | * | ( size 20 Bytes ) | * | | * --------------------------------- * | | * | EEPROM TABLE RAS INFO | * | (available info size 4 Bytes) | * | ( reserved size 252 Bytes ) | * | | * --------------------------------- * | | * | BAD PAGE RECORD AREA | * | | * --------------------------------- */ /* EEPROM Table V2_1 */ #define RAS_TABLE_V2_1_INFO_SIZE 256 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ RAS_TABLE_V2_1_INFO_SIZE) #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ RAS_TABLE_V2_1_INFO_SIZE) \ / RAS_TABLE_RECORD_SIZE) /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM * offset off of RAS_TABLE_START. That is, this is something you can * add to control->i2c_address, and then tell I2C layer to read * from/write to there. _N is the so called absolute index, * because it starts right after the table header. */ #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ (_N) * RAS_TABLE_RECORD_SIZE) #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off * of "fri", return the absolute record index off of the end of * the table header. */ #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ (_C)->ras_max_record_count) #define RAS_NUM_RECS(_tbl_hdr) \ (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE) ? 0u : \ (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)) #define RAS_NUM_RECS_V2_1(_tbl_hdr) \ (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE + \ RAS_TABLE_V2_1_INFO_SIZE) ? 0u : \ (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE - \ RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)) #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev) static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) { if (amdgpu_sriov_vf(adev)) return false; switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ case IP_VERSION(11, 0, 7): /* Sienna cichlid */ case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 2): /* Aldebaran */ case IP_VERSION(13, 0, 10): return true; case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): return (adev->gmc.is_app_apu) ? false : true; default: return false; } } static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, struct amdgpu_ras_eeprom_control *control) { struct atom_context *atom_ctx = adev->mode_info.atom_context; u8 i2c_addr; if (!control) return false; if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { /* The address given by VBIOS is an 8-bit, wire-format * address, i.e. the most significant byte. * * Normalize it to a 19-bit EEPROM address. Remove the * device type identifier and make it a 7-bit address; * then make it a 19-bit EEPROM address. See top of * amdgpu_eeprom.c. */ i2c_addr = (i2c_addr & 0x0F) >> 1; control->i2c_address = ((u32) i2c_addr) << 16; return true; } switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ if (adev->asic_type == CHIP_VEGA20) control->i2c_address = EEPROM_I2C_MADDR_0; else if (strnstr(atom_ctx->vbios_pn, "D342", sizeof(atom_ctx->vbios_pn))) control->i2c_address = EEPROM_I2C_MADDR_0; else control->i2c_address = EEPROM_I2C_MADDR_4; return true; case IP_VERSION(11, 0, 7): control->i2c_address = EEPROM_I2C_MADDR_0; return true; case IP_VERSION(13, 0, 2): if (strnstr(atom_ctx->vbios_pn, "D673", sizeof(atom_ctx->vbios_pn))) control->i2c_address = EEPROM_I2C_MADDR_4; else control->i2c_address = EEPROM_I2C_MADDR_0; return true; case IP_VERSION(13, 0, 0): if (strnstr(atom_ctx->vbios_pn, "D707", sizeof(atom_ctx->vbios_pn))) control->i2c_address = EEPROM_I2C_MADDR_0; else control->i2c_address = EEPROM_I2C_MADDR_4; return true; case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): control->i2c_address = EEPROM_I2C_MADDR_4; return true; default: return false; } } static void __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, unsigned char *buf) { u32 *pp = (uint32_t *)buf; pp[0] = cpu_to_le32(hdr->header); pp[1] = cpu_to_le32(hdr->version); pp[2] = cpu_to_le32(hdr->first_rec_offset); pp[3] = cpu_to_le32(hdr->tbl_size); pp[4] = cpu_to_le32(hdr->checksum); } static void __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, unsigned char *buf) { u32 *pp = (uint32_t *)buf; hdr->header = le32_to_cpu(pp[0]); hdr->version = le32_to_cpu(pp[1]); hdr->first_rec_offset = le32_to_cpu(pp[2]); hdr->tbl_size = le32_to_cpu(pp[3]); hdr->checksum = le32_to_cpu(pp[4]); } static int __write_table_header(struct amdgpu_ras_eeprom_control *control) { u8 buf[RAS_TABLE_HEADER_SIZE]; struct amdgpu_device *adev = to_amdgpu_device(control); int res; memset(buf, 0, sizeof(buf)); __encode_table_header_to_buf(&control->tbl_hdr, buf); /* i2c may be unstable in gpu reset */ down_read(&adev->reset_domain->sem); res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, control->i2c_address + control->ras_header_offset, buf, RAS_TABLE_HEADER_SIZE); up_read(&adev->reset_domain->sem); if (res < 0) { dev_err(adev->dev, "Failed to write EEPROM table header:%d", res); } else if (res < RAS_TABLE_HEADER_SIZE) { dev_err(adev->dev, "Short write:%d out of %d\n", res, RAS_TABLE_HEADER_SIZE); res = -EIO; } else { res = 0; } return res; } static void __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, unsigned char *buf) { u32 *pp = (uint32_t *)buf; u32 tmp; tmp = ((uint32_t)(rai->rma_status) & 0xFF) | (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); pp[0] = cpu_to_le32(tmp); } static void __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, unsigned char *buf) { u32 *pp = (uint32_t *)buf; u32 tmp; tmp = le32_to_cpu(pp[0]); rai->rma_status = tmp & 0xFF; rai->health_percent = (tmp >> 8) & 0xFF; rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; } static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) { struct amdgpu_device *adev = to_amdgpu_device(control); u8 *buf; int res; buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); if (!buf) { dev_err(adev->dev, "Failed to alloc buf to write table ras info\n"); return -ENOMEM; } __encode_table_ras_info_to_buf(&control->tbl_rai, buf); /* i2c may be unstable in gpu reset */ down_read(&adev->reset_domain->sem); res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, control->i2c_address + control->ras_info_offset, buf, RAS_TABLE_V2_1_INFO_SIZE); up_read(&adev->reset_domain->sem); if (res < 0) { dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", res); } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { dev_err(adev->dev, "Short write:%d out of %d\n", res, RAS_TABLE_V2_1_INFO_SIZE); res = -EIO; } else { res = 0; } kfree(buf); return res; } static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) { int ii; u8 *pp, csum; size_t sz; /* Header checksum, skip checksum field in the calculation */ sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); pp = (u8 *) &control->tbl_hdr; csum = 0; for (ii = 0; ii < sz; ii++, pp++) csum += *pp; return csum; } static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) { int ii; u8 *pp, csum; size_t sz; sz = sizeof(control->tbl_rai); pp = (u8 *) &control->tbl_rai; csum = 0; for (ii = 0; ii < sz; ii++, pp++) csum += *pp; return csum; } static int amdgpu_ras_eeprom_correct_header_tag( struct amdgpu_ras_eeprom_control *control, uint32_t header) { struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; u8 *hh; int res; u8 csum; csum = -hdr->checksum; hh = (void *) &hdr->header; csum -= (hh[0] + hh[1] + hh[2] + hh[3]); hh = (void *) &header; csum += hh[0] + hh[1] + hh[2] + hh[3]; csum = -csum; mutex_lock(&control->ras_tbl_mutex); hdr->header = header; hdr->checksum = csum; res = __write_table_header(control); mutex_unlock(&control->ras_tbl_mutex); return res; } static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) { struct amdgpu_device *adev = to_amdgpu_device(control); struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { case IP_VERSION(8, 10, 0): hdr->version = RAS_TABLE_VER_V2_1; return; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 5, 0): hdr->version = RAS_TABLE_VER_V3; return; default: hdr->version = RAS_TABLE_VER_V1; return; } } /** * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table * @control: pointer to control structure * * Reset the contents of the header of the RAS EEPROM table. * Return 0 on success, -errno on error. */ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) { struct amdgpu_device *adev = to_amdgpu_device(control); struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; struct amdgpu_ras *con = amdgpu_ras_get_context(adev); u8 csum; int res; mutex_lock(&control->ras_tbl_mutex); hdr->header = RAS_TABLE_HDR_VAL; amdgpu_ras_set_eeprom_table_version(control); if (hdr->version >= RAS_TABLE_VER_V2_1) { hdr->first_rec_offset = RAS_RECORD_START_V2_1; hdr->tbl_size = RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE; rai->rma_status = GPU_HEALTH_USABLE; control->ras_record_offset = RAS_RECORD_START_V2_1; control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; /** * GPU health represented as a percentage. * 0 means worst health, 100 means fully health. */ rai->health_percent = 100; /* ecc_page_threshold = 0 means disable bad page retirement */ rai->ecc_page_threshold = con->bad_page_cnt_threshold; } else { hdr->first_rec_offset = RAS_RECORD_START; hdr->tbl_size = RAS_TABLE_HEADER_SIZE; control->ras_record_offset = RAS_RECORD_START; control->ras_max_record_count = RAS_MAX_RECORD_COUNT; } csum = __calc_hdr_byte_sum(control); if (hdr->version >= RAS_TABLE_VER_V2_1) csum += __calc_ras_info_byte_sum(control); csum = -csum; hdr->checksum = csum; res = __write_table_header(control); if (!res && hdr->version > RAS_TABLE_VER_V1) res = __write_table_ras_info(control); control->ras_num_recs = 0; control->ras_num_bad_pages = 0; control->ras_num_mca_recs = 0; control->ras_num_pa_recs = 0; control->ras_fri = 0; amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages);