/* * Copyright 2013 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * Authors: Christian König <christian.koenig@amd.com> */ #include <linux/firmware.h>#include <linux/module.h> #include <drm/drm.h>#include <drm/drm_drv.h> #include "amdgpu.h"#include "amdgpu_pm.h"#include "amdgpu_vce.h"#include "amdgpu_cs.h"#include "cikd.h" /* 1 second timeout */#define VCE_IDLE_TIMEOUT	msecs_to_jiffies(1000) /* Firmware Names */#ifdef CONFIG_DRM_AMDGPU_SI#define FIRMWARE_VCE_V1_0	"amdgpu/vce_1_0_0.bin"#endif#ifdef CONFIG_DRM_AMDGPU_CIK#define FIRMWARE_BONAIRE	"amdgpu/bonaire_vce.bin"#define FIRMWARE_KABINI	"amdgpu/kabini_vce.bin"#define FIRMWARE_KAVERI	"amdgpu/kaveri_vce.bin"#define FIRMWARE_HAWAII	"amdgpu/hawaii_vce.bin"#define FIRMWARE_MULLINS	"amdgpu/mullins_vce.bin"#endif#define FIRMWARE_TONGA		"amdgpu/tonga_vce.bin"#define FIRMWARE_CARRIZO	"amdgpu/carrizo_vce.bin"#define FIRMWARE_FIJI		"amdgpu/fiji_vce.bin"#define FIRMWARE_STONEY		"amdgpu/stoney_vce.bin"#define FIRMWARE_POLARIS10	"amdgpu/polaris10_vce.bin"#define FIRMWARE_POLARIS11	"amdgpu/polaris11_vce.bin"#define FIRMWARE_POLARIS12	"amdgpu/polaris12_vce.bin"#define FIRMWARE_VEGAM		"amdgpu/vegam_vce.bin" #define FIRMWARE_VEGA10		"amdgpu/vega10_vce.bin"#define FIRMWARE_VEGA12		"amdgpu/vega12_vce.bin"#define FIRMWARE_VEGA20		"amdgpu/vega20_vce.bin" #ifdef CONFIG_DRM_AMDGPU_SIMODULE_FIRMWARE(FIRMWARE_VCE_V1_0);#endif#ifdef CONFIG_DRM_AMDGPU_CIKMODULE_FIRMWARE(FIRMWARE_BONAIRE);MODULE_FIRMWARE(FIRMWARE_KABINI);MODULE_FIRMWARE(FIRMWARE_KAVERI);MODULE_FIRMWARE(FIRMWARE_HAWAII);MODULE_FIRMWARE(FIRMWARE_MULLINS);#endifMODULE_FIRMWARE(FIRMWARE_TONGA);MODULE_FIRMWARE(FIRMWARE_CARRIZO);MODULE_FIRMWARE(FIRMWARE_FIJI);MODULE_FIRMWARE(FIRMWARE_STONEY);MODULE_FIRMWARE(FIRMWARE_POLARIS10);MODULE_FIRMWARE(FIRMWARE_POLARIS11);MODULE_FIRMWARE(FIRMWARE_POLARIS12);MODULE_FIRMWARE(FIRMWARE_VEGAM); MODULE_FIRMWARE(FIRMWARE_VEGA10);MODULE_FIRMWARE(FIRMWARE_VEGA12);MODULE_FIRMWARE(FIRMWARE_VEGA20); static void amdgpu_vce_idle_work_handler(struct work_struct *work);static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,				     struct dma_fence **fence);static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,				      bool direct, struct dma_fence **fence); /** * amdgpu_vce_firmware_name() - determine the firmware file name for VCE * * @adev: amdgpu_device pointer * * Each chip that has VCE IP may need a different firmware. * This function returns the name of the VCE firmware file * appropriate for the current chip. */static const char *amdgpu_vce_firmware_name(struct amdgpu_device *adev){	switch (adev->asic_type) {#ifdef CONFIG_DRM_AMDGPU_SI	case CHIP_PITCAIRN:	case CHIP_TAHITI:	case CHIP_VERDE:		return FIRMWARE_VCE_V1_0;#endif#ifdef CONFIG_DRM_AMDGPU_CIK	case CHIP_BONAIRE:		return FIRMWARE_BONAIRE;	case CHIP_KAVERI:		return FIRMWARE_KAVERI;	case CHIP_KABINI:		return FIRMWARE_KABINI;	case CHIP_HAWAII:		return FIRMWARE_HAWAII;	case CHIP_MULLINS:		return FIRMWARE_MULLINS;#endif	case CHIP_TONGA:		return  FIRMWARE_TONGA;	case CHIP_CARRIZO:		return  FIRMWARE_CARRIZO;	case CHIP_FIJI:		return  FIRMWARE_FIJI;	case CHIP_STONEY:		return  FIRMWARE_STONEY;	case CHIP_POLARIS10:		return  FIRMWARE_POLARIS10;	case CHIP_POLARIS11:		return  FIRMWARE_POLARIS11;	case CHIP_POLARIS12:		return  FIRMWARE_POLARIS12;	case CHIP_VEGAM:		return  FIRMWARE_VEGAM;	case CHIP_VEGA10:		return  FIRMWARE_VEGA10;	case CHIP_VEGA12:		return  FIRMWARE_VEGA12;	case CHIP_VEGA20:		return  FIRMWARE_VEGA20; 	default:		return NULL;	}} /** * amdgpu_vce_early_init() - try to load VCE firmware * * @adev: amdgpu_device pointer * * Tries to load the VCE firmware. * * When not found, returns ENOENT so that the driver can * still load and initialize the rest of the IP blocks. * The GPU can function just fine without VCE, they will just * not support video encoding. */int amdgpu_vce_early_init(struct amdgpu_device *adev){	const char *fw_name = amdgpu_vce_firmware_name(adev);	const struct common_firmware_header *hdr;	unsigned int ucode_version, version_major, version_minor, binary_id;	int r; 	if (!fw_name)		return -ENOENT; 	r = amdgpu_ucode_request(adev, &adev->vce.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name);	if (r) {		dev_err(adev->dev,			"amdgpu_vce: Firmware \"%s\" not found or failed to validate (%d)\n",			fw_name, r); 		amdgpu_ucode_release(&adev->vce.fw);		return -ENOENT;	} 	hdr = (const struct common_firmware_header *)adev->vce.fw->data; 	ucode_version = le32_to_cpu(hdr->ucode_version);	version_major = (ucode_version >> 20) & 0xfff;	version_minor = (ucode_version >> 8) & 0xfff;	binary_id = ucode_version & 0xff;	dev_info(adev->dev, "Found VCE firmware Version: %d.%d Binary ID: %d\n",		version_major, version_minor, binary_id);	adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |				(binary_id << 8)); 	return 0;} /** * amdgpu_vce_sw_init() - allocate memory for VCE BO * * @adev: amdgpu_device pointer * @size: size for the new BO * * First step to get VCE online: allocate memory for VCE BO. * The VCE firmware binary is copied into the VCE BO later, * in amdgpu_vce_resume. The VCE executes its code from the * VCE BO and also uses the space in this BO for its stack and data. * * Ideally this BO should be placed in VRAM for optimal performance, * although technically it also runs from system RAM (albeit slowly). */int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size){	int i, r; 	if (!adev->vce.fw)		return -ENOENT; 	r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,				    AMDGPU_GEM_DOMAIN_VRAM |				    AMDGPU_GEM_DOMAIN_GTT,				    &adev->vce.vcpu_bo,				    &adev->vce.gpu_addr, &adev->vce.cpu_addr);	if (r) {		dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);		return r;	} 	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {		atomic_set(&adev->vce.handles[i], 0);		adev->vce.filp[i] = NULL;	} 	INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);	mutex_init(&adev->vce.idle_mutex); 	return 0;} /** * amdgpu_vce_sw_fini - free memory * * @adev: amdgpu_device pointer * * Last step on VCE teardown, free firmware memory */int amdgpu_vce_sw_fini(struct amdgpu_device *adev){	unsigned int i; 	if (adev->vce.vcpu_bo == NULL)		return 0; 	drm_sched_entity_destroy(&adev->vce.entity); 	for (i = 0; i < adev->vce.num_rings; i++)		amdgpu_ring_fini(&adev->vce.ring[i]); 	amdgpu_ucode_release(&adev->vce.fw);	mutex_destroy(&adev->vce.idle_mutex); 	amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,		(void **)&adev->vce.cpu_addr); 	return 0;} /** * amdgpu_vce_entity_init - init entity * * @adev: amdgpu_device pointer * @ring: amdgpu_ring pointer to check * * Initialize the entity used for handle management in the kernel driver. */int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring){	if (ring == &adev->vce.ring[0]) {		struct drm_gpu_scheduler *sched = &ring->sched;		int r; 		r = drm_sched_entity_init(&adev->vce.entity, DRM_SCHED_PRIORITY_NORMAL,					  &sched, 1, NULL);		if (r != 0) {			DRM_ERROR("Failed setting up VCE run queue.\n");			return r;		}	} 	return 0;} /** * amdgpu_vce_suspend - unpin VCE fw memory * * @adev: amdgpu_device pointer * */int amdgpu_vce_suspend(struct amdgpu_device *adev){	int i; 	cancel_delayed_work_sync(&adev->vce.idle_work); 	if (adev->vce.vcpu_bo == NULL)		return 0; 	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)		if (atomic_read(&adev->vce.handles[i]))			break; 	if (i == AMDGPU_MAX_VCE_HANDLES)		return 0; 	/* TODO: suspending running encoding sessions isn't supported */	return -EINVAL;} /** * amdgpu_vce_resume - pin VCE fw memory * * @adev: amdgpu_device pointer * */int amdgpu_vce_resume(struct amdgpu_device *adev){	const struct common_firmware_header *hdr;	unsigned int offset;	int idx; 	if (adev->vce.vcpu_bo == NULL)		return -EINVAL; 	hdr = (const struct common_firmware_header *)adev->vce.fw->data;	offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 	if (drm_dev_enter(adev_to_drm(adev), &idx)) {		memset_io(adev->vce.cpu_addr, 0, amdgpu_bo_size(adev->vce.vcpu_bo));		memcpy_toio(adev->vce.cpu_addr, adev->vce.fw->data + offset,			    adev->vce.fw->size - offset);		drm_dev_exit(idx);	} 	return 0;} /** * amdgpu_vce_idle_work_handler - power off VCE * * @work: pointer to work structure * * power of VCE when it's not used any more */static void amdgpu_vce_idle_work_handler(struct work_struct *work){	struct amdgpu_device *adev =		container_of(work, struct amdgpu_device, vce.idle_work.work);	unsigned int i, count = 0; 	for (i = 0; i < adev->vce.num_rings; i++)		count += amdgpu_fence_count_emitted(&adev->vce.ring[i]); 	if (count == 0) {		if (adev->pm.dpm_enabled) {			amdgpu_dpm_enable_vce(adev, false);		} else {			amdgpu_asic_set_vce_clocks(adev, 0, 0);			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,							       AMD_PG_STATE_GATE);			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,							       AMD_CG_STATE_GATE);		}	} else {		schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);	}} /** * amdgpu_vce_ring_begin_use - power up VCE * * @ring: amdgpu ring * * Make sure VCE is powerd up when we want to use it */void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring){	struct amdgpu_device *adev = ring->adev;	bool set_clocks; 	if (amdgpu_sriov_vf(adev))		return; 	mutex_lock(&adev->vce.idle_mutex);	set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);	if (set_clocks) {		if (adev->pm.dpm_enabled) {			amdgpu_dpm_enable_vce(adev, true);		} else {			amdgpu_asic_set_vce_clocks(adev, 53300, 40000);			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,							       AMD_CG_STATE_UNGATE);			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,							       AMD_PG_STATE_UNGATE); 		}	}	mutex_unlock(&adev->vce.idle_mutex);} /** * amdgpu_vce_ring_end_use - power VCE down * * @ring: amdgpu ring * * Schedule work to power VCE down again */void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring){	if (!amdgpu_sriov_vf(ring->adev))		schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);} /** * amdgpu_vce_free_handles - free still open VCE handles * * @adev: amdgpu_device pointer * @filp: drm file pointer * * Close all VCE handles still open by this file pointer */void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp){	struct amdgpu_ring *ring = &adev->vce.ring[0];	int i, r; 	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {		uint32_t handle = atomic_read(&adev->vce.handles[i]); 		if (!handle || adev->vce.filp[i] != filp)			continue; 		r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);		if (r)			DRM_ERROR("Error destroying VCE handle (%d)!\n", r); 		adev->vce.filp[i] = NULL;		atomic_set(&adev->vce.handles[i], 0);	}} /** * amdgpu_vce_get_create_msg - generate a VCE create msg * * @ring: ring we should submit the msg to * @handle: VCE session handle to use * @fence: optional fence to return * * Open up a stream for HW test */static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,				     struct dma_fence **fence){	const unsigned int ib_size_dw = 1024;	struct amdgpu_job *job;	struct amdgpu_ib *ib;	struct amdgpu_ib ib_msg;	struct dma_fence *f = NULL;	uint64_t addr;	int i, r; 	r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity,				     AMDGPU_FENCE_OWNER_UNDEFINED,				     ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST,				     &job);	if (r)		return r; 	memset(&ib_msg, 0, sizeof(ib_msg));	/* only one gpu page is needed, alloc +1 page to make addr aligned. */	r = amdgpu_ib_get(ring->adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,			  AMDGPU_IB_POOL_DIRECT,			  &ib_msg);	if (r)		goto err; 	ib = &job->ibs[0];	/* let addr point to page boundary */	addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); 	/* stitch together an VCE create msg */	ib->length_dw = 0;	ib->ptr[ib->length_dw++] = 0x0000000c; /* len */	ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */	ib->ptr[ib->length_dw++] = handle; 	if ((ring->adev->vce.fw_version >> 24) >= 52)		ib->ptr[ib->length_dw++] = 0x00000040; /* len */

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