// SPDX-License-Identifier: GPL-2.0 OR MIT/* * Copyright 2014-2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/slab.h>#include <linux/list.h>#include "kfd_device_queue_manager.h"#include "kfd_priv.h"#include "kfd_kernel_queue.h"#include "amdgpu_amdkfd.h"#include "amdgpu_reset.h" static inline struct process_queue_node *get_queue_by_qid( struct process_queue_manager *pqm, unsigned int qid){ struct process_queue_node *pqn; list_for_each_entry(pqn, &pqm->queues, process_queue_list) { if ((pqn->q && pqn->q->properties.queue_id == qid) || (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) return pqn; } return NULL;} static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, unsigned int qid){ if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) return -EINVAL; if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); return -ENOSPC; } return 0;} static int find_available_queue_slot(struct process_queue_manager *pqm, unsigned int *qid){ unsigned long found; found = find_first_zero_bit(pqm->queue_slot_bitmap, KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); pr_debug("The new slot id %lu\n", found); if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { pr_info("Cannot open more queues for process with pid %d\n", pqm->process->lead_thread->pid); return -ENOMEM; } set_bit(found, pqm->queue_slot_bitmap); *qid = found; return 0;} void kfd_process_dequeue_from_device(struct kfd_process_device *pdd){ struct kfd_node *dev = pdd->dev; if (pdd->already_dequeued) return; /* The MES context flush needs to filter out the case which the * KFD process is created without setting up the MES context and * queue for creating a compute queue. */ dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && down_read_trylock(&dev->adev->reset_domain->sem)) { amdgpu_mes_flush_shader_debugger(dev->adev, pdd->proc_ctx_gpu_addr, ffs(pdd->dev->xcc_mask) - 1); up_read(&dev->adev->reset_domain->sem); } pdd->already_dequeued = true;} int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, void *gws){ struct mqd_update_info minfo = {0}; struct kfd_node *dev = NULL; struct process_queue_node *pqn; struct kfd_process_device *pdd; struct kgd_mem *mem = NULL; int ret; pqn = get_queue_by_qid(pqm, qid); if (!pqn) { pr_err("Queue id does not match any known queue\n"); return -EINVAL; } if (pqn->q) dev = pqn->q->device; if (WARN_ON(!dev)) return -ENODEV; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { pr_err("Process device data doesn't exist\n"); return -EINVAL; } /* Only allow one queue per process can have GWS assigned */ if (gws && pdd->qpd.num_gws) return -EBUSY; if (!gws && pdd->qpd.num_gws == 0) return -EINVAL; if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) && !dev->kfd->shared_resources.enable_mes) { if (gws) ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, gws, &mem); else ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, pqn->q->gws); if (unlikely(ret)) return ret; pqn->q->gws = mem; } else { /* * Intentionally set GWS to a non-NULL value * for devices that do not use GWS for global wave * synchronization but require the formality * of setting GWS for cooperative groups. */ pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; } pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, pqn->q, &minfo);} void kfd_process_dequeue_from_all_devices(struct kfd_process *p){ int i; for (i = 0; i < p->n_pdds; i++) kfd_process_dequeue_from_device(p->pdds[i]);} int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p){ INIT_LIST_HEAD(&pqm->queues); pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; return 0;} static void pqm_clean_queue_resource(struct process_queue_manager *pqm, struct process_queue_node *pqn){ struct kfd_node *dev; struct kfd_process_device *pdd; dev = pqn->q->device; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { pr_err("Process device data doesn't exist\n"); return; } if (pqn->q->gws) { if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) && !dev->kfd->shared_resources.enable_mes) amdgpu_amdkfd_remove_gws_from_process( pqm->process->kgd_process_info, pqn->q->gws); pdd->qpd.num_gws = 0; } if (dev->kfd->shared_resources.enable_mes) { amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, pqn->q->gang_ctx_array_index); amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo); amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); }} void pqm_uninit(struct process_queue_manager *pqm){ struct process_queue_node *pqn, *next; list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { if (pqn->q) { struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device, pqm->process); if (pdd) { kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); kfd_queue_release_buffers(pdd, &pqn->q->properties); } else { WARN_ON(!pdd); } pqm_clean_queue_resource(pqm, pqn); } kfd_procfs_del_queue(pqn->q); uninit_queue(pqn->q); list_del(&pqn->process_queue_list); kfree(pqn); } bitmap_free(pqm->queue_slot_bitmap); pqm->queue_slot_bitmap = NULL;} static int init_user_queue(struct process_queue_manager *pqm, struct kfd_node *dev, struct queue **q, struct queue_properties *q_properties, unsigned int qid){ int retval; /* Doorbell initialized in user space*/ q_properties->doorbell_ptr = NULL; q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); /* let DQM handle it*/ q_properties->vmid = 0; q_properties->queue_id = qid; retval = init_queue(q, q_properties); if (retval != 0) return retval; (*q)->device = dev; (*q)->process = pqm->process; if (dev->kfd->shared_resources.enable_mes) { if (!q_properties->wptr_bo) { pr_debug("Queue initialization with shared MES requires queue buffers to be initialized\n"); return -EINVAL; } retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, AMDGPU_MES_GANG_CTX_SIZE, AMDGPU_GEM_DOMAIN_GTT, &(*q)->gang_ctx_bo, &(*q)->gang_ctx_gpu_addr, &(*q)->gang_ctx_cpu_ptr, false); if (retval) { pr_err("failed to allocate gang context bo\n"); goto cleanup; } memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); /* Bind one MES gang context slot per queue (gang). */ if (dev->adev->mes.use_rs64mem) { retval = amdgpu_mes_alloc_gang_ctx_index(&dev->adev->mes, &(*q)->gang_ctx_array_index); if (retval) { pr_err("failed to allocate gang context index slot\n"); goto cleanup; } } /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) */ if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { pr_err("Queue memory allocated to wrong device\n"); retval = -EINVAL; goto free_gang_ctx_bo; } retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, &(*q)->wptr_bo_gart); if (retval) { pr_err("Failed to map wptr bo to GART\n"); goto free_gang_ctx_bo; } } pr_debug("PQM After init queue"); return 0; free_gang_ctx_bo: amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, (*q)->gang_ctx_array_index); amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo);cleanup: uninit_queue(*q); *q = NULL; return retval;} int pqm_create_queue(struct process_queue_manager *pqm, struct kfd_node *dev, struct queue_properties *properties, unsigned int *qid, const struct kfd_criu_queue_priv_data *q_data, const void *restore_mqd, const void *restore_ctl_stack, uint32_t *p_doorbell_offset_in_process){ int retval; struct kfd_process_device *pdd; struct queue *q; struct process_queue_node *pqn; struct kernel_queue *kq; enum kfd_queue_type type = properties->type; unsigned int max_queues = 127; /* HWS limit */ /* * On GFX 9.4.3/9.5.0, increase the number of queues that * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0. */ if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) max_queues = 255; q = NULL; kq = NULL; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { pr_err("Process device data doesn't exist\n"); return -1; } /* * for debug process, verify that it is within the static queues limit * currently limit is set to half of the total avail HQD slots * If we are just about to create DIQ, the is_debug flag is not set yet * Hence we also check the type as well */ if (pdd->qpd.is_debug) max_queues = dev->kfd->device_info.max_no_of_hqd/2; if (pdd->qpd.queue_count >= max_queues) return -ENOSPC; if (q_data) { retval = assign_queue_slot_by_qid(pqm, q_data->q_id); *qid = q_data->q_id; } else retval = find_available_queue_slot(pqm, qid); if (retval != 0) return retval; /* Register process if this is the first queue */ if (list_empty(&pdd->qpd.queues_list) && list_empty(&pdd->qpd.priv_queue_list)) dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, AMDGPU_MES_PROC_CTX_SIZE, AMDGPU_GEM_DOMAIN_GTT, &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, false); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context bo\n"); goto err_allocate_pqn; } memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); /* Bind one MES process context slot to the whole process * (per device); every queue of this process reuses it. */ if (dev->adev->mes.use_rs64mem) { retval = amdgpu_mes_alloc_proc_ctx_index(&dev->adev->mes, &pdd->proc_ctx_array_index); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context index\n"); goto err_allocate_pqn; } } } pqn = kzalloc_obj(*pqn); if (!pqn) { retval = -ENOMEM; goto err_allocate_pqn; } switch (type) { case KFD_QUEUE_TYPE_SDMA: case KFD_QUEUE_TYPE_SDMA_XGMI: case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: /* SDMA queues are always allocated statically no matter * which scheduler mode is used. We also do not need to * check whether a SDMA queue can be allocated here, because * allocate_sdma_queue() in create_queue() has the * corresponding check logic. */ retval = init_user_queue(pqm, dev, &q, properties, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; pqn->kq = NULL; retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, restore_mqd, restore_ctl_stack); print_queue(q); break; case KFD_QUEUE_TYPE_COMPUTE: /* check if there is over subscription */ if ((dev->dqm->sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); retval = -EPERM; goto err_create_queue; } retval = init_user_queue(pqm, dev, &q, properties, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; pqn->kq = NULL; retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, restore_mqd, restore_ctl_stack); print_queue(q); break; default: WARN(1, "Invalid queue type %d", type); retval = -EINVAL; } if (retval != 0) { if ((type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI || type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) && retval == -ENOMEM) pr_warn("process pid %d DQM create queue type %d failed. ret %d\n", pqm->process->lead_thread->pid, type, retval); else pr_err("process pid %d DQM create queue type %d failed. ret %d\n", pqm->process->lead_thread->pid, type, retval); goto err_create_queue; } if (q && p_doorbell_offset_in_process) { /* Return the doorbell offset within the doorbell page * to the caller so it can be passed up to user mode * (in bytes). * relative doorbell index = Absolute doorbell index - * absolute index of first doorbell in the page. */ uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, pdd->qpd.proc_doorbells, 0, pdd->dev->kfd->device_info.doorbell_size); *p_doorbell_offset_in_process = (q->properties.doorbell_off - first_db_index) * sizeof(uint32_t); } pr_debug("PQM After DQM create queue\n"); list_add(&pqn->process_queue_list, &pqm->queues); if (q) { pr_debug("PQM done creating queue\n"); kfd_procfs_add_queue(q); print_queue_properties(&q->properties); }Lines 1–500 of 1185. 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// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014-2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/slab.h> #include <linux/list.h> #include "kfd_device_queue_manager.h" #include "kfd_priv.h" #include "kfd_kernel_queue.h" #include "amdgpu_amdkfd.h" #include "amdgpu_reset.h" static inline struct process_queue_node *get_queue_by_qid( struct process_queue_manager *pqm, unsigned int qid) { struct process_queue_node *pqn; list_for_each_entry(pqn, &pqm->queues, process_queue_list) { if ((pqn->q && pqn->q->properties.queue_id == qid) || (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) return pqn; } return NULL; } static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, unsigned int qid) { if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) return -EINVAL; if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); return -ENOSPC; } return 0; } static int find_available_queue_slot(struct process_queue_manager *pqm, unsigned int *qid) { unsigned long found; found = find_first_zero_bit(pqm->queue_slot_bitmap, KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); pr_debug("The new slot id %lu\n", found); if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { pr_info("Cannot open more queues for process with pid %d\n", pqm->process->lead_thread->pid); return -ENOMEM; } set_bit(found, pqm->queue_slot_bitmap); *qid = found; return 0; } void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) { struct kfd_node *dev = pdd->dev; if (pdd->already_dequeued) return; /* The MES context flush needs to filter out the case which the * KFD process is created without setting up the MES context and * queue for creating a compute queue. */ dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && down_read_trylock(&dev->adev->reset_domain->sem)) { amdgpu_mes_flush_shader_debugger(dev->adev, pdd->proc_ctx_gpu_addr, ffs(pdd->dev->xcc_mask) - 1); up_read(&dev->adev->reset_domain->sem); } pdd->already_dequeued = true; } int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, void *gws) { struct mqd_update_info minfo = {0}; struct kfd_node *dev = NULL; struct process_queue_node *pqn; struct kfd_process_device *pdd; struct kgd_mem *mem = NULL; int ret; pqn = get_queue_by_qid(pqm, qid); if (!pqn) { pr_err("Queue id does not match any known queue\n"); return -EINVAL; } if (pqn->q) dev = pqn->q->device; if (WARN_ON(!dev)) return -ENODEV; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { pr_err("Process device data doesn't exist\n"); return -EINVAL; } /* Only allow one queue per process can have GWS assigned */ if (gws && pdd->qpd.num_gws) return -EBUSY; if (!gws && pdd->qpd.num_gws == 0) return -EINVAL; if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) && !dev->kfd->shared_resources.enable_mes) { if (gws) ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, gws, &mem); else ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, pqn->q->gws); if (unlikely(ret)) return ret; pqn->q->gws = mem; } else { /* * Intentionally set GWS to a non-NULL value * for devices that do not use GWS for global wave * synchronization but require the formality * of setting GWS for cooperative groups. */ pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; } pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, pqn->q, &minfo); } void kfd_process_dequeue_from_all_devices(struct kfd_process *p) { int i; for (i = 0; i < p->n_pdds; i++) kfd_process_dequeue_from_device(p->pdds[i]); } int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) { INIT_LIST_HEAD(&pqm->queues); pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; return 0; } static void pqm_clean_queue_resource(struct process_queue_manager *pqm, struct process_queue_node *pqn) { struct kfd_node *dev; struct kfd_process_device *pdd; dev = pqn->q->device; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { pr_err("Process device data doesn't exist\n"); return; } if (pqn->q->gws) { if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) && !dev->kfd->shared_resources.enable_mes) amdgpu_amdkfd_remove_gws_from_process( pqm->process->kgd_process_info, pqn->q->gws); pdd->qpd.num_gws = 0; } if (dev->kfd->shared_resources.enable_mes) { amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, pqn->q->gang_ctx_array_index); amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo); amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); } } void pqm_uninit(struct process_queue_manager *pqm) { struct process_queue_node *pqn, *next; list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { if (pqn->q) { struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device, pqm->process); if (pdd) { kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); kfd_queue_release_buffers(pdd, &pqn->q->properties); } else { WARN_ON(!pdd); } pqm_clean_queue_resource(pqm, pqn); } kfd_procfs_del_queue(pqn->q); uninit_queue(pqn->q); list_del(&pqn->process_queue_list); kfree(pqn); } bitmap_free(pqm->queue_slot_bitmap); pqm->queue_slot_bitmap = NULL; } static int init_user_queue(struct process_queue_manager *pqm, struct kfd_node *dev, struct queue **q, struct queue_properties *q_properties, unsigned int qid) { int retval; /* Doorbell initialized in user space*/ q_properties->doorbell_ptr = NULL; q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); /* let DQM handle it*/ q_properties->vmid = 0; q_properties->queue_id = qid; retval = init_queue(q, q_properties); if (retval != 0) return retval; (*q)->device = dev; (*q)->process = pqm->process; if (dev->kfd->shared_resources.enable_mes) { if (!q_properties->wptr_bo) { pr_debug("Queue initialization with shared MES requires queue buffers to be initialized\n"); return -EINVAL; } retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, AMDGPU_MES_GANG_CTX_SIZE, AMDGPU_GEM_DOMAIN_GTT, &(*q)->gang_ctx_bo, &(*q)->gang_ctx_gpu_addr, &(*q)->gang_ctx_cpu_ptr, false); if (retval) { pr_err("failed to allocate gang context bo\n"); goto cleanup; } memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); /* Bind one MES gang context slot per queue (gang). */ if (dev->adev->mes.use_rs64mem) { retval = amdgpu_mes_alloc_gang_ctx_index(&dev->adev->mes, &(*q)->gang_ctx_array_index); if (retval) { pr_err("failed to allocate gang context index slot\n"); goto cleanup; } } /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) */ if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { pr_err("Queue memory allocated to wrong device\n"); retval = -EINVAL; goto free_gang_ctx_bo; } retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, &(*q)->wptr_bo_gart); if (retval) { pr_err("Failed to map wptr bo to GART\n"); goto free_gang_ctx_bo; } } pr_debug("PQM After init queue"); return 0; free_gang_ctx_bo: amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, (*q)->gang_ctx_array_index); amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo); cleanup: uninit_queue(*q); *q = NULL; return retval; } int pqm_create_queue(struct process_queue_manager *pqm, struct kfd_node *dev, struct queue_properties *properties, unsigned int *qid, const struct kfd_criu_queue_priv_data *q_data, const void *restore_mqd, const void *restore_ctl_stack, uint32_t *p_doorbell_offset_in_process) { int retval; struct kfd_process_device *pdd; struct queue *q; struct process_queue_node *pqn; struct kernel_queue *kq; enum kfd_queue_type type = properties->type; unsigned int max_queues = 127; /* HWS limit */ /* * On GFX 9.4.3/9.5.0, increase the number of queues that * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0. */ if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) max_queues = 255; q = NULL; kq = NULL; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { pr_err("Process device data doesn't exist\n"); return -1; } /* * for debug process, verify that it is within the static queues limit * currently limit is set to half of the total avail HQD slots * If we are just about to create DIQ, the is_debug flag is not set yet * Hence we also check the type as well */ if (pdd->qpd.is_debug) max_queues = dev->kfd->device_info.max_no_of_hqd/2; if (pdd->qpd.queue_count >= max_queues) return -ENOSPC; if (q_data) { retval = assign_queue_slot_by_qid(pqm, q_data->q_id); *qid = q_data->q_id; } else retval = find_available_queue_slot(pqm, qid); if (retval != 0) return retval; /* Register process if this is the first queue */ if (list_empty(&pdd->qpd.queues_list) && list_empty(&pdd->qpd.priv_queue_list)) dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, AMDGPU_MES_PROC_CTX_SIZE, AMDGPU_GEM_DOMAIN_GTT, &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, false); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context bo\n"); goto err_allocate_pqn; } memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); /* Bind one MES process context slot to the whole process * (per device); every queue of this process reuses it. */ if (dev->adev->mes.use_rs64mem) { retval = amdgpu_mes_alloc_proc_ctx_index(&dev->adev->mes, &pdd->proc_ctx_array_index); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context index\n"); goto err_allocate_pqn; } } } pqn = kzalloc_obj(*pqn); if (!pqn) { retval = -ENOMEM; goto err_allocate_pqn; } switch (type) { case KFD_QUEUE_TYPE_SDMA: case KFD_QUEUE_TYPE_SDMA_XGMI: case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: /* SDMA queues are always allocated statically no matter * which scheduler mode is used. We also do not need to * check whether a SDMA queue can be allocated here, because * allocate_sdma_queue() in create_queue() has the * corresponding check logic. */ retval = init_user_queue(pqm, dev, &q, properties, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; pqn->kq = NULL; retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, restore_mqd, restore_ctl_stack); print_queue(q); break; case KFD_QUEUE_TYPE_COMPUTE: /* check if there is over subscription */ if ((dev->dqm->sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); retval = -EPERM; goto err_create_queue; } retval = init_user_queue(pqm, dev, &q, properties, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; pqn->kq = NULL; retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, restore_mqd, restore_ctl_stack); print_queue(q); break; default: WARN(1, "Invalid queue type %d", type); retval = -EINVAL; } if (retval != 0) { if ((type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI || type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) && retval == -ENOMEM) pr_warn("process pid %d DQM create queue type %d failed. ret %d\n", pqm->process->lead_thread->pid, type, retval); else pr_err("process pid %d DQM create queue type %d failed. ret %d\n", pqm->process->lead_thread->pid, type, retval); goto err_create_queue; } if (q && p_doorbell_offset_in_process) { /* Return the doorbell offset within the doorbell page * to the caller so it can be passed up to user mode * (in bytes). * relative doorbell index = Absolute doorbell index - * absolute index of first doorbell in the page. */ uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, pdd->qpd.proc_doorbells, 0, pdd->dev->kfd->device_info.doorbell_size); *p_doorbell_offset_in_process = (q->properties.doorbell_off - first_db_index) * sizeof(uint32_t); } pr_debug("PQM After DQM create queue\n"); list_add(&pqn->process_queue_list, &pqm->queues); if (q) { pr_debug("PQM done creating queue\n"); kfd_procfs_add_queue(q); print_queue_properties(&q->properties); }