/* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __MES_API_DEF_H__#define __MES_API_DEF_H__ #pragma pack(push, 8) #define MES_API_VERSION 0x14 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */#define  AMDGPU_MES_LOG_BUFFER_SIZE  0xC000 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API * to ease the debugging and parsing of ring buffer. */enum {API_FRAME_SIZE_IN_DWORDS = 64}; /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in, * this creates another queue */enum {API_NUMBER_OF_COMMAND_MAX   = 32}; enum MES_API_TYPE {	MES_API_TYPE_SCHEDULER = 1,	MES_API_TYPE_MAX}; enum MES_SCH_API_OPCODE {	MES_SCH_API_SET_HW_RSRC			= 0,	MES_SCH_API_SET_SCHEDULING_CONFIG	= 1, /* agreegated db, quantums, etc */	MES_SCH_API_ADD_QUEUE			= 2,	MES_SCH_API_REMOVE_QUEUE		= 3,	MES_SCH_API_PERFORM_YIELD		= 4,	MES_SCH_API_SET_GANG_PRIORITY_LEVEL	= 5, /* For windows GANG = Context */	MES_SCH_API_SUSPEND			= 6,	MES_SCH_API_RESUME			= 7,	MES_SCH_API_RESET			= 8,	MES_SCH_API_SET_LOG_BUFFER		= 9,	MES_SCH_API_CHANGE_GANG_PRORITY		= 10,	MES_SCH_API_QUERY_SCHEDULER_STATUS	= 11,	MES_SCH_API_SET_DEBUG_VMID		= 13,	MES_SCH_API_MISC			= 14,	MES_SCH_API_UPDATE_ROOT_PAGE_TABLE	= 15,	MES_SCH_API_AMD_LOG			= 16,	MES_SCH_API_SET_SE_MODE			= 17,	MES_SCH_API_SET_GANG_SUBMIT		= 18,	MES_SCH_API_SET_HW_RSRC_1               = 19,	MES_SCH_API_INV_TLBS                    = 20, 	MES_SCH_API_MAX = 0xFF}; enum MES_RRMT_MODE {	MES_RRMT_MODE_LOCAL_XCD,	MES_RRMT_MODE_LOCAL_REMOTE_AID,	MES_RRMT_MODE_REMOTE_XCD,	MES_RRMT_MODE_REMOTE_MID}; union MES_API_HEADER {	struct {		uint32_t type	  : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */		uint32_t opcode   : 8;		uint32_t dwsize   : 8; /* including header */		uint32_t reserved : 12;	}; 	uint32_t u32All;}; enum MES_AMD_PRIORITY_LEVEL {	AMD_PRIORITY_LEVEL_LOW		= 0,	AMD_PRIORITY_LEVEL_NORMAL	= 1,	AMD_PRIORITY_LEVEL_MEDIUM	= 2,	AMD_PRIORITY_LEVEL_HIGH		= 3,	AMD_PRIORITY_LEVEL_REALTIME	= 4, 	AMD_PRIORITY_NUM_LEVELS}; enum MES_QUEUE_TYPE {	MES_QUEUE_TYPE_GFX,	MES_QUEUE_TYPE_COMPUTE,	MES_QUEUE_TYPE_SDMA, 	MES_QUEUE_TYPE_MAX,	MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX,}; struct MES_API_STATUS {	uint64_t api_completion_fence_addr;	uint64_t api_completion_fence_value;}; /* * MES will set api_completion_fence_value in api_completion_fence_addr * when it can successflly process the API. MES will also trigger * following interrupt when it finish process the API no matter success * or failed. *     Interrupt source id 181 (EOP) with context ID (DW 6 in the int *     cookie) set to 0xb1 and context type set to 8. Driver side need *     to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to *     catch this interrupt. *     Driver side also need to set enable_mes_fence_int = 1 in *     set_HW_resource package to enable this fence interrupt. * when the API process failed. *     lowre 32 bits set to 0. *     higher 32 bits set as follows (bit shift within high 32) *         bit 0  -  7    API specific error code. *         bit 8  - 15    API OPCODE. *         bit 16 - 23    MISC OPCODE if any *         bit 24 - 30    ERROR category (API_ERROR_XXX) *         bit 31         Set to 1 to indicate error status * */enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 };enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 };enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 };enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 }; enum MES_ERROR_CATEGORY_CODE_12 {	MES_ERROR_API                = 1,	MES_ERROR_SCHEDULING         = 2,	MES_ERROR_UNKNOWN            = 3,}; #define MES_ERR_CODE(api_err, opcode, misc_op, category) \			((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \			misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \			category << MES_ERROR_CATEGORY_SHIFT_12 | \			1 << MES_API_STATUS_ERROR_SHIFT_12) << 32) enum { MAX_COMPUTE_PIPES = 8 };enum { MAX_GFX_PIPES	 = 2 };enum { MAX_SDMA_PIPES	 = 2 }; enum { MAX_COMPUTE_HQD_PER_PIPE		= 8 };enum { MAX_GFX_HQD_PER_PIPE		= 8 };enum { MAX_SDMA_HQD_PER_PIPE		= 10 };enum { MAX_SDMA_HQD_PER_PIPE_11_0	= 8 };  enum { MAX_QUEUES_IN_A_GANG = 8 }; enum VM_HUB_TYPE {	VM_HUB_TYPE_GC = 0,	VM_HUB_TYPE_MM = 1, 	VM_HUB_TYPE_MAX,}; enum { VMID_INVALID = 0xffff }; enum { MAX_VMID_GCHUB = 16 };enum { MAX_VMID_MMHUB = 16 }; enum SET_DEBUG_VMID_OPERATIONS {	DEBUG_VMID_OP_PROGRAM	= 0,	DEBUG_VMID_OP_ALLOCATE	= 1,	DEBUG_VMID_OP_RELEASE	= 2,	DEBUG_VMID_OP_VM_SETUP	= 3 // used to set up the debug vmid page table in the kernel queue case (mode 1)}; enum MES_MS_LOG_CONTEXT_STATE {	MES_LOG_CONTEXT_STATE_IDLE		= 0,	MES_LOG_CONTEXT_STATE_RUNNING		= 1,	MES_LOG_CONTEXT_STATE_READY		= 2,	MES_LOG_CONTEXT_STATE_READY_STANDBY	= 3,	MES_LOG_CONTEXT_STATE_INVALID		= 0xF,}; enum MES_MS_LOG_OPERATION {	MES_LOG_OPERATION_CONTEXT_STATE_CHANGE		= 0,	MES_LOG_OPERATION_QUEUE_NEW_WORK		= 1,	MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT	= 2,	MES_LOG_OPERATION_QUEUE_NO_MORE_WORK		= 3,	MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT	= 4,	MES_LOG_OPERATION_QUEUE_INVALID			= 0xF,}; struct MES_LOG_CONTEXT_STATE_CHANGE {	uint64_t			h_context;	enum MES_MS_LOG_CONTEXT_STATE	new_context_state;}; struct MES_LOG_QUEUE_NEW_WORK {	uint64_t	h_queue;	uint64_t	reserved;}; struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {	uint64_t	h_queue;	uint64_t	h_sync_object;}; struct MES_LOG_QUEUE_NO_MORE_WORK {	uint64_t	h_queue;	uint64_t	reserved;}; struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {	uint64_t	h_queue;	uint64_t	h_sync_object;}; struct MES_LOG_ENTRY_HEADER {	uint32_t first_free_entry_index;	uint32_t wraparound_count;	uint64_t number_of_entries;	uint64_t reserved[2];}; struct MES_LOG_ENTRY_DATA {	uint64_t gpu_time_stamp;	uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */	uint32_t reserved_operation_type_bits;	union {		struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;		struct MES_LOG_QUEUE_NEW_WORK queue_new_work;		struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;		struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;		struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;		uint64_t all[2];	};}; struct MES_LOG_BUFFER {	struct MES_LOG_ENTRY_HEADER header;	struct MES_LOG_ENTRY_DATA	entries[];}; enum MES_SWIP_TO_HWIP_DEF {	MES_MAX_HWIP_SEGMENT = 8,}; union MESAPI_SET_HW_RESOURCES {	struct {		union MES_API_HEADER	header;		uint32_t		vmid_mask_mmhub;		uint32_t		vmid_mask_gfxhub;		uint32_t		gds_size;		uint32_t		paging_vmid;		uint32_t		compute_hqd_mask[MAX_COMPUTE_PIPES];		uint32_t		gfx_hqd_mask[MAX_GFX_PIPES];		uint32_t		sdma_hqd_mask[MAX_SDMA_PIPES];		uint32_t		aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];		uint64_t		g_sch_ctx_gpu_mc_ptr;		uint64_t		query_status_fence_gpu_mc_ptr;		uint32_t		gc_base[MES_MAX_HWIP_SEGMENT];		uint32_t		mmhub_base[MES_MAX_HWIP_SEGMENT];		uint32_t		osssys_base[MES_MAX_HWIP_SEGMENT];		struct MES_API_STATUS	api_status;		union {			struct {				uint32_t disable_reset : 1;				uint32_t use_different_vmid_compute : 1;				uint32_t disable_mes_log   : 1;				uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;				uint32_t apply_grbm_remote_register_dummy_read_wa : 1;				uint32_t second_gfx_pipe_enabled : 1;				uint32_t enable_level_process_quantum_check : 1;				uint32_t legacy_sch_mode : 1;				uint32_t disable_add_queue_wptr_mc_addr : 1;				uint32_t enable_mes_event_int_logging : 1;				uint32_t enable_reg_active_poll : 1;				uint32_t use_disable_queue_in_legacy_uq_preemption : 1;				uint32_t send_write_data : 1;				uint32_t os_tdr_timeout_override : 1;				uint32_t use_rs64mem_for_proc_gang_ctx : 1;				uint32_t halt_on_misaligned_access : 1;				uint32_t use_add_queue_unmap_flag_addr : 1;				uint32_t enable_mes_sch_stb_log : 1;				uint32_t limit_single_process : 1;				uint32_t unmapped_doorbell_handling: 2;				uint32_t enable_mes_fence_int: 1;				uint32_t enable_lr_compute_wa : 2;				uint32_t enable_compute_pipe_reset : 1;				uint32_t reserved : 7;			};			uint32_t uint32_all;		};	uint32_t	oversubscription_timer;	uint64_t	doorbell_info;	uint64_t	event_intr_history_gpu_mc_ptr;	uint64_t	timestamp;	uint32_t	os_tdr_timeout_in_sec;	}; 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];}; union MESAPI_SET_HW_RESOURCES_1 {	struct {		union MES_API_HEADER                header;		struct MES_API_STATUS               api_status;		uint64_t                            timestamp;		union {			struct {				uint32_t enable_mes_debug_ctx : 1;				uint32_t mes_coop_mode : 1; /* 0: non-coop; 1: coop */				uint32_t reserved : 30;			};			uint32_t uint32_all;		};		uint64_t                            mes_debug_ctx_mc_addr;		uint32_t                            mes_debug_ctx_size;		/* unit is 100ms */		uint32_t                            mes_kiq_unmap_timeout;		/* shared buffer of master/slaves, valid if mes_coop_mode=1 */		uint64_t                            coop_sch_shared_mc_addr;		uint64_t                            cleaner_shader_fence_mc_addr;	}; 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];}; union MESAPI__ADD_QUEUE {	struct {		union MES_API_HEADER	header;		uint32_t		process_id;		uint64_t		page_table_base_addr;		uint64_t		process_va_start;		uint64_t		process_va_end;		uint64_t		process_quantum;		uint64_t		process_context_addr;		uint64_t		gang_quantum;		uint64_t		gang_context_addr;		uint32_t		inprocess_gang_priority;		enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;		uint32_t		doorbell_offset;		uint64_t		mqd_addr;		/* From MES_API_VERSION 2, mc addr is expected for wptr_addr */		uint64_t		wptr_addr;		uint64_t		h_context;		uint64_t		h_queue;		enum MES_QUEUE_TYPE	queue_type;		uint32_t		gds_base;		union {			/* backwards compatibility with Linux, remove union once they use kfd_queue_size */			uint32_t	gds_size;			uint32_t	kfd_queue_size;		};		uint32_t		gws_base;		uint32_t		gws_size;		uint32_t		oa_mask;		uint64_t		trap_handler_addr;		uint32_t		vm_context_cntl; 		struct {			uint32_t paging	 : 1;			uint32_t debug_vmid  : 4;			uint32_t program_gds : 1;			uint32_t is_gang_suspended : 1;			uint32_t is_tmz_queue : 1;			uint32_t map_kiq_utility_queue : 1;			uint32_t is_kfd_process : 1;			uint32_t trap_en : 1;			uint32_t is_aql_queue : 1;			uint32_t skip_process_ctx_clear : 1;			uint32_t map_legacy_kq : 1;			uint32_t exclusively_scheduled : 1;			uint32_t is_long_running : 1;			uint32_t is_dwm_queue : 1;			uint32_t reserved	 : 15;		};		struct MES_API_STATUS	api_status;		uint64_t		tma_addr;		uint32_t		sch_id;		uint64_t		timestamp;		uint32_t		process_context_array_index;		uint32_t		gang_context_array_index;		uint32_t		pipe_id;	//used for mapping legacy kernel queue		uint32_t		queue_id;		uint32_t		alignment_mode_setting;		uint32_t		full_sh_mem_config_data;	}; 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];}; union MESAPI__REMOVE_QUEUE {	struct {		union MES_API_HEADER	header;		uint32_t		doorbell_offset;		uint64_t		gang_context_addr; 		struct {			uint32_t reserved01		  : 1;			uint32_t unmap_kiq_utility_queue  : 1;			uint32_t preempt_legacy_gfx_queue : 1;			uint32_t unmap_legacy_queue	  : 1;			uint32_t remove_queue_after_reset : 1;			uint32_t reserved		  : 27;		};		struct MES_API_STATUS		api_status; 		uint32_t			pipe_id;		uint32_t			queue_id; 		uint64_t			tf_addr;		uint32_t			tf_data; 		enum MES_QUEUE_TYPE		queue_type;		uint64_t			timestamp;		uint32_t			gang_context_array_index;	}; 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];}; union MESAPI__SET_SCHEDULING_CONFIG {	struct {		union MES_API_HEADER	header;		/* Grace period when preempting another priority band for this priority band.		 * The value for idle priority band is ignored, as it never preempts other bands.		 */		uint64_t		grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 		/* Default quantum for scheduling across processes within a priority band. */		uint64_t		process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 		/* Default grace period for processes that preempt each other within a priority band.*/		uint64_t		process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 		/* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.		 * Valid values are between 0 and 50, with the default being 10.		 */		uint32_t		normal_yield_percent; 		struct MES_API_STATUS	api_status;		uint64_t		timestamp;	}; 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];}; union MESAPI__PERFORM_YIELD {	struct {		union MES_API_HEADER	header;		uint32_t		dummy;		struct MES_API_STATUS	api_status;		uint64_t		timestamp;	}; 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];}; union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {	struct {		union MES_API_HEADER		header;		uint32_t			inprocess_gang_priority;		enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;		uint64_t			gang_quantum;		uint64_t			gang_context_addr;		struct MES_API_STATUS		api_status;		uint32_t			doorbell_offset;		uint64_t			timestamp;		uint32_t			gang_context_array_index;		struct {			uint32_t		queue_quantum_scale	: 2;			uint32_t		queue_quantum_duration	: 8;			uint32_t		apply_quantum_all_processes : 1;			uint32_t		reserved		: 21;		};	}; 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];}; union MESAPI__SUSPEND {	struct {		union MES_API_HEADER	header;		/* false - suspend all gangs; true - specific gang */		struct {			uint32_t      suspend_all_gangs : 1; // suspend all compute gangs (can be set together with suspend_all_sdma_gangs)			uint32_t      query_status : 1;			uint32_t      suspend_all_sdma_gangs : 1; // suspend all sdma gangs (can be set together with suspend_all_gangs)			uint32_t      reserved : 29;		};

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