/* * Copyright (C) 2019  Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */#if !defined (_navi10_ENUM_HEADER)#define _navi10_ENUM_HEADER #ifndef _DRIVER_BUILD#ifndef GL_ZERO#define GL__ZERO                      BLEND_ZERO#define GL__ONE                       BLEND_ONE#define GL__SRC_COLOR                 BLEND_SRC_COLOR#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR#define GL__DST_COLOR                 BLEND_DST_COLOR#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA#define GL__DST_ALPHA                 BLEND_DST_ALPHA#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA#endif#endif /******************************************************* * GDS DATA_TYPE Enums *******************************************************/ #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H#define ENUMS_GDS_PERFCOUNT_SELECT_Htypedef enum GDS_PERFCOUNT_SELECT { GDS_PERF_SEL_DS_ADDR_CONFL = 0, GDS_PERF_SEL_DS_BANK_CONFL = 1, GDS_PERF_SEL_WBUF_FLUSH = 2, GDS_PERF_SEL_WR_COMP = 3, GDS_PERF_SEL_WBUF_WR = 4, GDS_PERF_SEL_RBUF_HIT = 5, GDS_PERF_SEL_RBUF_MISS = 6, GDS_PERF_SEL_SE0_SH0_NORET = 7, GDS_PERF_SEL_SE0_SH0_RET = 8, GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, GDS_PERF_SEL_SE0_SH1_NORET = 21, GDS_PERF_SEL_SE0_SH1_RET = 22, GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, GDS_PERF_SEL_SE1_SH0_NORET = 35, GDS_PERF_SEL_SE1_SH0_RET = 36, GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, GDS_PERF_SEL_SE1_SH1_NORET = 49, GDS_PERF_SEL_SE1_SH1_RET = 50, GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, GDS_PERF_SEL_SE2_SH0_NORET = 63, GDS_PERF_SEL_SE2_SH0_RET = 64, GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, GDS_PERF_SEL_SE2_SH1_NORET = 77, GDS_PERF_SEL_SE2_SH1_RET = 78, GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, GDS_PERF_SEL_SE3_SH0_NORET = 91, GDS_PERF_SEL_SE3_SH0_RET = 92, GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, GDS_PERF_SEL_SE3_SH1_NORET = 105, GDS_PERF_SEL_SE3_SH1_RET = 106, GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, GDS_PERF_SEL_GWS_RELEASED = 119, GDS_PERF_SEL_GWS_BYPASS = 120,} GDS_PERFCOUNT_SELECT;#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ /******************************************************* * Chip Enums *******************************************************/ /* * GATCL1RequestType enum */ typedef enum GATCL1RequestType {GATCL1_TYPE_NORMAL                       = 0x00000000,GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,GATCL1_TYPE_BYPASS                       = 0x00000002,} GATCL1RequestType; /* * UTCL1RequestType enum */ typedef enum UTCL1RequestType {UTCL1_TYPE_NORMAL                        = 0x00000000,UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,UTCL1_TYPE_BYPASS                        = 0x00000002,} UTCL1RequestType; /* * UTCL1FaultType enum */ typedef enum UTCL1FaultType {UTCL1_XNACK_SUCCESS                      = 0x00000000,UTCL1_XNACK_RETRY                        = 0x00000001,UTCL1_XNACK_PRT                          = 0x00000002,UTCL1_XNACK_NO_RETRY                     = 0x00000003,} UTCL1FaultType; /* * UTCL0RequestType enum */ typedef enum UTCL0RequestType {UTCL0_TYPE_NORMAL                        = 0x00000000,UTCL0_TYPE_SHOOTDOWN                     = 0x00000001,UTCL0_TYPE_BYPASS                        = 0x00000002,} UTCL0RequestType; /* * UTCL0FaultType enum */ typedef enum UTCL0FaultType {UTCL0_XNACK_SUCCESS                      = 0x00000000,UTCL0_XNACK_RETRY                        = 0x00000001,UTCL0_XNACK_PRT                          = 0x00000002,UTCL0_XNACK_NO_RETRY                     = 0x00000003,} UTCL0FaultType; /* * VMEMCMD_RETURN_ORDER enum */ typedef enum VMEMCMD_RETURN_ORDER {VMEMCMD_RETURN_OUT_OF_ORDER              = 0x00000000,VMEMCMD_RETURN_IN_ORDER                  = 0x00000001,VMEMCMD_RETURN_IN_ORDER_READ             = 0x00000002,} VMEMCMD_RETURN_ORDER; /* * GL0V_CACHE_POLICIES enum */ typedef enum GL0V_CACHE_POLICIES {GL0V_CACHE_POLICY_MISS_LRU               = 0x00000000,GL0V_CACHE_POLICY_MISS_EVICT             = 0x00000001,GL0V_CACHE_POLICY_HIT_LRU                = 0x00000002,GL0V_CACHE_POLICY_HIT_EVICT              = 0x00000003,} GL0V_CACHE_POLICIES; /* * GL1_CACHE_POLICIES enum */ typedef enum GL1_CACHE_POLICIES {GL1_CACHE_POLICY_MISS_LRU                = 0x00000000,GL1_CACHE_POLICY_MISS_EVICT              = 0x00000001,GL1_CACHE_POLICY_HIT_LRU                 = 0x00000002,GL1_CACHE_POLICY_HIT_EVICT               = 0x00000003,} GL1_CACHE_POLICIES; /* * GL1_CACHE_STORE_POLICIES enum */ typedef enum GL1_CACHE_STORE_POLICIES {GL1_CACHE_STORE_POLICY_BYPASS            = 0x00000000,} GL1_CACHE_STORE_POLICIES; /* * TCC_CACHE_POLICIES enum */ typedef enum TCC_CACHE_POLICIES {TCC_CACHE_POLICY_LRU                     = 0x00000000,TCC_CACHE_POLICY_STREAM                  = 0x00000001,} TCC_CACHE_POLICIES; /* * TCC_MTYPE enum */ typedef enum TCC_MTYPE {MTYPE_NC                                 = 0x00000000,MTYPE_WC                                 = 0x00000001,MTYPE_CC                                 = 0x00000002,} TCC_MTYPE; /* * GL2_CACHE_POLICIES enum */ typedef enum GL2_CACHE_POLICIES {GL2_CACHE_POLICY_LRU                     = 0x00000000,GL2_CACHE_POLICY_STREAM                  = 0x00000001,GL2_CACHE_POLICY_NOA                     = 0x00000002,GL2_CACHE_POLICY_BYPASS                  = 0x00000003,} GL2_CACHE_POLICIES; /* * MTYPE enum */ typedef enum MTYPE {MTYPE_C_RW_US                            = 0x00000000,MTYPE_RESERVED_1                         = 0x00000001,MTYPE_C_RO_S                             = 0x00000002,MTYPE_UC                                 = 0x00000003,MTYPE_C_RW_S                             = 0x00000004,MTYPE_RESERVED_5                         = 0x00000005,MTYPE_C_RO_US                            = 0x00000006,MTYPE_RESERVED_7                         = 0x00000007,} MTYPE; /* * RMI_CID enum */ typedef enum RMI_CID {RMI_CID_CC                               = 0x00000000,RMI_CID_FC                               = 0x00000001,RMI_CID_CM                               = 0x00000002,RMI_CID_DC                               = 0x00000003,RMI_CID_Z                                = 0x00000004,RMI_CID_S                                = 0x00000005,RMI_CID_TILE                             = 0x00000006,RMI_CID_ZPCPSD                           = 0x00000007,} RMI_CID; /* * WritePolicy enum */ typedef enum WritePolicy {CACHE_LRU_WR                             = 0x00000000,CACHE_STREAM                             = 0x00000001,CACHE_BYPASS                             = 0x00000002,UNCACHED_WR                              = 0x00000003,} WritePolicy; /* * ReadPolicy enum */ typedef enum ReadPolicy {CACHE_LRU_RD                             = 0x00000000,CACHE_NOA                                = 0x00000001,UNCACHED_RD                              = 0x00000002,RESERVED_RDPOLICY                        = 0x00000003,} ReadPolicy; /* * PERFMON_COUNTER_MODE enum */ typedef enum PERFMON_COUNTER_MODE {PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,PERFMON_COUNTER_MODE_MAX                 = 0x00000002,PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,} PERFMON_COUNTER_MODE; /* * PERFMON_SPM_MODE enum */ typedef enum PERFMON_SPM_MODE {PERFMON_SPM_MODE_OFF                     = 0x00000000,PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,} PERFMON_SPM_MODE; /* * SurfaceTiling enum */ typedef enum SurfaceTiling {ARRAY_LINEAR                             = 0x00000000,ARRAY_TILED                              = 0x00000001,} SurfaceTiling; /* * SurfaceArray enum */ typedef enum SurfaceArray {ARRAY_1D                                 = 0x00000000,ARRAY_2D                                 = 0x00000001,ARRAY_3D                                 = 0x00000002,ARRAY_3D_SLICE                           = 0x00000003,} SurfaceArray; /* * ColorArray enum */ typedef enum ColorArray {ARRAY_2D_ALT_COLOR                       = 0x00000000,ARRAY_2D_COLOR                           = 0x00000001,ARRAY_3D_SLICE_COLOR                     = 0x00000003,} ColorArray; /* * DepthArray enum */ typedef enum DepthArray {ARRAY_2D_ALT_DEPTH                       = 0x00000000,ARRAY_2D_DEPTH                           = 0x00000001,} DepthArray; /* * ENUM_NUM_SIMD_PER_CU enum */ typedef enum ENUM_NUM_SIMD_PER_CU {NUM_SIMD_PER_CU                          = 0x00000002,} ENUM_NUM_SIMD_PER_CU; /* * DSM_ENABLE_ERROR_INJECT enum */ typedef enum DSM_ENABLE_ERROR_INJECT {DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE    = 0x00000002,DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED  = 0x00000003,} DSM_ENABLE_ERROR_INJECT; /* * DSM_SELECT_INJECT_DELAY enum */ typedef enum DSM_SELECT_INJECT_DELAY {DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,} DSM_SELECT_INJECT_DELAY; /* * DSM_DATA_SEL enum */ typedef enum DSM_DATA_SEL {DSM_DATA_SEL_DISABLE                     = 0x00000000,DSM_DATA_SEL_0                           = 0x00000001,DSM_DATA_SEL_1                           = 0x00000002,DSM_DATA_SEL_BOTH                        = 0x00000003,} DSM_DATA_SEL; /* * DSM_SINGLE_WRITE enum */ typedef enum DSM_SINGLE_WRITE {DSM_SINGLE_WRITE_DIS                     = 0x00000000,DSM_SINGLE_WRITE_EN                      = 0x00000001,} DSM_SINGLE_WRITE; /* * Hdp_SurfaceEndian enum */ typedef enum Hdp_SurfaceEndian {HDP_ENDIAN_NONE                          = 0x00000000,HDP_ENDIAN_8IN16                         = 0x00000001,HDP_ENDIAN_8IN32                         = 0x00000002,HDP_ENDIAN_8IN64                         = 0x00000003,} Hdp_SurfaceEndian; /******************************************************* * CNVC_CFG Enums *******************************************************/ /* * CNVC_ENABLE enum */ typedef enum CNVC_ENABLE {CNVC_DIS                                 = 0x00000000,CNVC_EN                                  = 0x00000001,} CNVC_ENABLE; /*

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