/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */#if !defined (_vega10_ENUM_HEADER)#define _vega10_ENUM_HEADER #ifndef _DRIVER_BUILD#ifndef GL_ZERO#define GL__ZERO BLEND_ZERO#define GL__ONE BLEND_ONE#define GL__SRC_COLOR BLEND_SRC_COLOR#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR#define GL__DST_COLOR BLEND_DST_COLOR#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR#define GL__SRC_ALPHA BLEND_SRC_ALPHA#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA#define GL__DST_ALPHA BLEND_DST_ALPHA#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA#endif#endif /******************************************************* * GDS DATA_TYPE Enums *******************************************************/ #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H#define ENUMS_GDS_PERFCOUNT_SELECT_Htypedef enum GDS_PERFCOUNT_SELECT { GDS_PERF_SEL_DS_ADDR_CONFL = 0, GDS_PERF_SEL_DS_BANK_CONFL = 1, GDS_PERF_SEL_WBUF_FLUSH = 2, GDS_PERF_SEL_WR_COMP = 3, GDS_PERF_SEL_WBUF_WR = 4, GDS_PERF_SEL_RBUF_HIT = 5, GDS_PERF_SEL_RBUF_MISS = 6, GDS_PERF_SEL_SE0_SH0_NORET = 7, GDS_PERF_SEL_SE0_SH0_RET = 8, GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, GDS_PERF_SEL_SE0_SH1_NORET = 21, GDS_PERF_SEL_SE0_SH1_RET = 22, GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, GDS_PERF_SEL_SE1_SH0_NORET = 35, GDS_PERF_SEL_SE1_SH0_RET = 36, GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, GDS_PERF_SEL_SE1_SH1_NORET = 49, GDS_PERF_SEL_SE1_SH1_RET = 50, GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, GDS_PERF_SEL_SE2_SH0_NORET = 63, GDS_PERF_SEL_SE2_SH0_RET = 64, GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, GDS_PERF_SEL_SE2_SH1_NORET = 77, GDS_PERF_SEL_SE2_SH1_RET = 78, GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, GDS_PERF_SEL_SE3_SH0_NORET = 91, GDS_PERF_SEL_SE3_SH0_RET = 92, GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, GDS_PERF_SEL_SE3_SH1_NORET = 105, GDS_PERF_SEL_SE3_SH1_RET = 106, GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, GDS_PERF_SEL_GWS_RELEASED = 119, GDS_PERF_SEL_GWS_BYPASS = 120,} GDS_PERFCOUNT_SELECT;#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ /******************************************************* * Chip Enums *******************************************************/ /* * MEM_PWR_FORCE_CTRL enum */ typedef enum MEM_PWR_FORCE_CTRL {NO_FORCE_REQUEST = 0x00000000,FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,FORCE_DEEP_SLEEP_REQUEST = 0x00000002,FORCE_SHUT_DOWN_REQUEST = 0x00000003,} MEM_PWR_FORCE_CTRL; /* * MEM_PWR_FORCE_CTRL2 enum */ typedef enum MEM_PWR_FORCE_CTRL2 {NO_FORCE_REQ = 0x00000000,FORCE_LIGHT_SLEEP_REQ = 0x00000001,} MEM_PWR_FORCE_CTRL2; /* * MEM_PWR_DIS_CTRL enum */ typedef enum MEM_PWR_DIS_CTRL {ENABLE_MEM_PWR_CTRL = 0x00000000,DISABLE_MEM_PWR_CTRL = 0x00000001,} MEM_PWR_DIS_CTRL; /* * MEM_PWR_SEL_CTRL enum */ typedef enum MEM_PWR_SEL_CTRL {DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,} MEM_PWR_SEL_CTRL; /* * MEM_PWR_SEL_CTRL2 enum */ typedef enum MEM_PWR_SEL_CTRL2 {DYNAMIC_DEEP_SLEEP_EN = 0x00000000,DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,} MEM_PWR_SEL_CTRL2; /* * RowSize enum */ typedef enum RowSize {ADDR_CONFIG_1KB_ROW = 0x00000000,ADDR_CONFIG_2KB_ROW = 0x00000001,ADDR_CONFIG_4KB_ROW = 0x00000002,} RowSize; /* * SurfaceEndian enum */ typedef enum SurfaceEndian {ENDIAN_NONE = 0x00000000,ENDIAN_8IN16 = 0x00000001,ENDIAN_8IN32 = 0x00000002,ENDIAN_8IN64 = 0x00000003,} SurfaceEndian; /* * ArrayMode enum */ typedef enum ArrayMode {ARRAY_LINEAR_GENERAL = 0x00000000,ARRAY_LINEAR_ALIGNED = 0x00000001,ARRAY_1D_TILED_THIN1 = 0x00000002,ARRAY_1D_TILED_THICK = 0x00000003,ARRAY_2D_TILED_THIN1 = 0x00000004,ARRAY_PRT_TILED_THIN1 = 0x00000005,ARRAY_PRT_2D_TILED_THIN1 = 0x00000006,ARRAY_2D_TILED_THICK = 0x00000007,ARRAY_2D_TILED_XTHICK = 0x00000008,ARRAY_PRT_TILED_THICK = 0x00000009,ARRAY_PRT_2D_TILED_THICK = 0x0000000a,ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b,ARRAY_3D_TILED_THIN1 = 0x0000000c,ARRAY_3D_TILED_THICK = 0x0000000d,ARRAY_3D_TILED_XTHICK = 0x0000000e,ARRAY_PRT_3D_TILED_THICK = 0x0000000f,} ArrayMode; /* * NumPipes enum */ typedef enum NumPipes {ADDR_CONFIG_1_PIPE = 0x00000000,ADDR_CONFIG_2_PIPE = 0x00000001,ADDR_CONFIG_4_PIPE = 0x00000002,ADDR_CONFIG_8_PIPE = 0x00000003,ADDR_CONFIG_16_PIPE = 0x00000004,ADDR_CONFIG_32_PIPE = 0x00000005,} NumPipes; /* * NumBanksConfig enum */ typedef enum NumBanksConfig {ADDR_CONFIG_1_BANK = 0x00000000,ADDR_CONFIG_2_BANK = 0x00000001,ADDR_CONFIG_4_BANK = 0x00000002,ADDR_CONFIG_8_BANK = 0x00000003,ADDR_CONFIG_16_BANK = 0x00000004,} NumBanksConfig; /* * PipeInterleaveSize enum */ typedef enum PipeInterleaveSize {ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,} PipeInterleaveSize; /* * BankInterleaveSize enum */ typedef enum BankInterleaveSize {ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,} BankInterleaveSize; /* * NumShaderEngines enum */ typedef enum NumShaderEngines {ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,} NumShaderEngines; /* * NumRbPerShaderEngine enum */ typedef enum NumRbPerShaderEngine {ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,} NumRbPerShaderEngine; /* * NumGPUs enum */ typedef enum NumGPUs {ADDR_CONFIG_1_GPU = 0x00000000,ADDR_CONFIG_2_GPU = 0x00000001,ADDR_CONFIG_4_GPU = 0x00000002,ADDR_CONFIG_8_GPU = 0x00000003,} NumGPUs; /* * NumMaxCompressedFragments enum */ typedef enum NumMaxCompressedFragments {ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,} NumMaxCompressedFragments; /* * ShaderEngineTileSize enum */ typedef enum ShaderEngineTileSize {ADDR_CONFIG_SE_TILE_16 = 0x00000000,ADDR_CONFIG_SE_TILE_32 = 0x00000001,} ShaderEngineTileSize; /* * MultiGPUTileSize enum */ typedef enum MultiGPUTileSize {ADDR_CONFIG_GPU_TILE_16 = 0x00000000,ADDR_CONFIG_GPU_TILE_32 = 0x00000001,ADDR_CONFIG_GPU_TILE_64 = 0x00000002,ADDR_CONFIG_GPU_TILE_128 = 0x00000003,} MultiGPUTileSize; /* * NumLowerPipes enum */ typedef enum NumLowerPipes {ADDR_CONFIG_1_LOWER_PIPES = 0x00000000,ADDR_CONFIG_2_LOWER_PIPES = 0x00000001,} NumLowerPipes; /* * ColorTransform enum */ typedef enum ColorTransform {DCC_CT_AUTO = 0x00000000,DCC_CT_NONE = 0x00000001,ABGR_TO_A_BG_G_RB = 0x00000002,BGRA_TO_BG_G_RB_A = 0x00000003,} ColorTransform; /* * CompareRef enum */ typedef enum CompareRef {REF_NEVER = 0x00000000,REF_LESS = 0x00000001,REF_EQUAL = 0x00000002,REF_LEQUAL = 0x00000003,REF_GREATER = 0x00000004,REF_NOTEQUAL = 0x00000005,REF_GEQUAL = 0x00000006,REF_ALWAYS = 0x00000007,} CompareRef; /* * ReadSize enum */ typedef enum ReadSize {READ_256_BITS = 0x00000000,READ_512_BITS = 0x00000001,} ReadSize; /* * DepthFormat enum */ typedef enum DepthFormat {DEPTH_INVALID = 0x00000000,DEPTH_16 = 0x00000001,DEPTH_X8_24 = 0x00000002,DEPTH_8_24 = 0x00000003,DEPTH_X8_24_FLOAT = 0x00000004,DEPTH_8_24_FLOAT = 0x00000005,DEPTH_32_FLOAT = 0x00000006,DEPTH_X24_8_32_FLOAT = 0x00000007,} DepthFormat; /* * ZFormat enum */ typedef enum ZFormat {Z_INVALID = 0x00000000,Z_16 = 0x00000001,Z_24 = 0x00000002,Z_32_FLOAT = 0x00000003,} ZFormat; /* * StencilFormat enum */ typedef enum StencilFormat {STENCIL_INVALID = 0x00000000,STENCIL_8 = 0x00000001,} StencilFormat; /* * CmaskMode enum */ typedef enum CmaskMode {CMASK_CLEAR_NONE = 0x00000000,CMASK_CLEAR_ONE = 0x00000001,CMASK_CLEAR_ALL = 0x00000002,CMASK_ANY_EXPANDED = 0x00000003,CMASK_ALPHA0_FRAG1 = 0x00000004,CMASK_ALPHA0_FRAG2 = 0x00000005,CMASK_ALPHA0_FRAG4 = 0x00000006,CMASK_ALPHA0_FRAGS = 0x00000007,CMASK_ALPHA1_FRAG1 = 0x00000008,CMASK_ALPHA1_FRAG2 = 0x00000009,CMASK_ALPHA1_FRAG4 = 0x0000000a,CMASK_ALPHA1_FRAGS = 0x0000000b,CMASK_ALPHAX_FRAG1 = 0x0000000c,CMASK_ALPHAX_FRAG2 = 0x0000000d,CMASK_ALPHAX_FRAG4 = 0x0000000e,CMASK_ALPHAX_FRAGS = 0x0000000f,} CmaskMode; /* * QuadExportFormat enum */ typedef enum QuadExportFormat {EXPORT_UNUSED = 0x00000000,EXPORT_32_R = 0x00000001,EXPORT_32_GR = 0x00000002,EXPORT_32_AR = 0x00000003,EXPORT_FP16_ABGR = 0x00000004,EXPORT_UNSIGNED16_ABGR = 0x00000005,EXPORT_SIGNED16_ABGR = 0x00000006,EXPORT_32_ABGR = 0x00000007,EXPORT_32BPP_8PIX = 0x00000008,EXPORT_16_16_UNSIGNED_8PIX = 0x00000009,EXPORT_16_16_SIGNED_8PIX = 0x0000000a,EXPORT_16_16_FLOAT_8PIX = 0x0000000b,} QuadExportFormat;Lines 1–500 of 22532. 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/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #if !defined (_vega10_ENUM_HEADER) #define _vega10_ENUM_HEADER #ifndef _DRIVER_BUILD #ifndef GL_ZERO #define GL__ZERO BLEND_ZERO #define GL__ONE BLEND_ONE #define GL__SRC_COLOR BLEND_SRC_COLOR #define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR #define GL__DST_COLOR BLEND_DST_COLOR #define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR #define GL__SRC_ALPHA BLEND_SRC_ALPHA #define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA #define GL__DST_ALPHA BLEND_DST_ALPHA #define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA #define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE #define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR #define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR #define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA #define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA #endif #endif /******************************************************* * GDS DATA_TYPE Enums *******************************************************/ #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H #define ENUMS_GDS_PERFCOUNT_SELECT_H typedef enum GDS_PERFCOUNT_SELECT { GDS_PERF_SEL_DS_ADDR_CONFL = 0, GDS_PERF_SEL_DS_BANK_CONFL = 1, GDS_PERF_SEL_WBUF_FLUSH = 2, GDS_PERF_SEL_WR_COMP = 3, GDS_PERF_SEL_WBUF_WR = 4, GDS_PERF_SEL_RBUF_HIT = 5, GDS_PERF_SEL_RBUF_MISS = 6, GDS_PERF_SEL_SE0_SH0_NORET = 7, GDS_PERF_SEL_SE0_SH0_RET = 8, GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, GDS_PERF_SEL_SE0_SH1_NORET = 21, GDS_PERF_SEL_SE0_SH1_RET = 22, GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, GDS_PERF_SEL_SE1_SH0_NORET = 35, GDS_PERF_SEL_SE1_SH0_RET = 36, GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, GDS_PERF_SEL_SE1_SH1_NORET = 49, GDS_PERF_SEL_SE1_SH1_RET = 50, GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, GDS_PERF_SEL_SE2_SH0_NORET = 63, GDS_PERF_SEL_SE2_SH0_RET = 64, GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, GDS_PERF_SEL_SE2_SH1_NORET = 77, GDS_PERF_SEL_SE2_SH1_RET = 78, GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, GDS_PERF_SEL_SE3_SH0_NORET = 91, GDS_PERF_SEL_SE3_SH0_RET = 92, GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, GDS_PERF_SEL_SE3_SH1_NORET = 105, GDS_PERF_SEL_SE3_SH1_RET = 106, GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, GDS_PERF_SEL_GWS_RELEASED = 119, GDS_PERF_SEL_GWS_BYPASS = 120, } GDS_PERFCOUNT_SELECT; #endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ /******************************************************* * Chip Enums *******************************************************/ /* * MEM_PWR_FORCE_CTRL enum */ typedef enum MEM_PWR_FORCE_CTRL { NO_FORCE_REQUEST = 0x00000000, FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, FORCE_DEEP_SLEEP_REQUEST = 0x00000002, FORCE_SHUT_DOWN_REQUEST = 0x00000003, } MEM_PWR_FORCE_CTRL; /* * MEM_PWR_FORCE_CTRL2 enum */ typedef enum MEM_PWR_FORCE_CTRL2 { NO_FORCE_REQ = 0x00000000, FORCE_LIGHT_SLEEP_REQ = 0x00000001, } MEM_PWR_FORCE_CTRL2; /* * MEM_PWR_DIS_CTRL enum */ typedef enum MEM_PWR_DIS_CTRL { ENABLE_MEM_PWR_CTRL = 0x00000000, DISABLE_MEM_PWR_CTRL = 0x00000001, } MEM_PWR_DIS_CTRL; /* * MEM_PWR_SEL_CTRL enum */ typedef enum MEM_PWR_SEL_CTRL { DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, } MEM_PWR_SEL_CTRL; /* * MEM_PWR_SEL_CTRL2 enum */ typedef enum MEM_PWR_SEL_CTRL2 { DYNAMIC_DEEP_SLEEP_EN = 0x00000000, DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, } MEM_PWR_SEL_CTRL2; /* * RowSize enum */ typedef enum RowSize { ADDR_CONFIG_1KB_ROW = 0x00000000, ADDR_CONFIG_2KB_ROW = 0x00000001, ADDR_CONFIG_4KB_ROW = 0x00000002, } RowSize; /* * SurfaceEndian enum */ typedef enum SurfaceEndian { ENDIAN_NONE = 0x00000000, ENDIAN_8IN16 = 0x00000001, ENDIAN_8IN32 = 0x00000002, ENDIAN_8IN64 = 0x00000003, } SurfaceEndian; /* * ArrayMode enum */ typedef enum ArrayMode { ARRAY_LINEAR_GENERAL = 0x00000000, ARRAY_LINEAR_ALIGNED = 0x00000001, ARRAY_1D_TILED_THIN1 = 0x00000002, ARRAY_1D_TILED_THICK = 0x00000003, ARRAY_2D_TILED_THIN1 = 0x00000004, ARRAY_PRT_TILED_THIN1 = 0x00000005, ARRAY_PRT_2D_TILED_THIN1 = 0x00000006, ARRAY_2D_TILED_THICK = 0x00000007, ARRAY_2D_TILED_XTHICK = 0x00000008, ARRAY_PRT_TILED_THICK = 0x00000009, ARRAY_PRT_2D_TILED_THICK = 0x0000000a, ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b, ARRAY_3D_TILED_THIN1 = 0x0000000c, ARRAY_3D_TILED_THICK = 0x0000000d, ARRAY_3D_TILED_XTHICK = 0x0000000e, ARRAY_PRT_3D_TILED_THICK = 0x0000000f, } ArrayMode; /* * NumPipes enum */ typedef enum NumPipes { ADDR_CONFIG_1_PIPE = 0x00000000, ADDR_CONFIG_2_PIPE = 0x00000001, ADDR_CONFIG_4_PIPE = 0x00000002, ADDR_CONFIG_8_PIPE = 0x00000003, ADDR_CONFIG_16_PIPE = 0x00000004, ADDR_CONFIG_32_PIPE = 0x00000005, } NumPipes; /* * NumBanksConfig enum */ typedef enum NumBanksConfig { ADDR_CONFIG_1_BANK = 0x00000000, ADDR_CONFIG_2_BANK = 0x00000001, ADDR_CONFIG_4_BANK = 0x00000002, ADDR_CONFIG_8_BANK = 0x00000003, ADDR_CONFIG_16_BANK = 0x00000004, } NumBanksConfig; /* * PipeInterleaveSize enum */ typedef enum PipeInterleaveSize { ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, } PipeInterleaveSize; /* * BankInterleaveSize enum */ typedef enum BankInterleaveSize { ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, } BankInterleaveSize; /* * NumShaderEngines enum */ typedef enum NumShaderEngines { ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, } NumShaderEngines; /* * NumRbPerShaderEngine enum */ typedef enum NumRbPerShaderEngine { ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, } NumRbPerShaderEngine; /* * NumGPUs enum */ typedef enum NumGPUs { ADDR_CONFIG_1_GPU = 0x00000000, ADDR_CONFIG_2_GPU = 0x00000001, ADDR_CONFIG_4_GPU = 0x00000002, ADDR_CONFIG_8_GPU = 0x00000003, } NumGPUs; /* * NumMaxCompressedFragments enum */ typedef enum NumMaxCompressedFragments { ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, } NumMaxCompressedFragments; /* * ShaderEngineTileSize enum */ typedef enum ShaderEngineTileSize { ADDR_CONFIG_SE_TILE_16 = 0x00000000, ADDR_CONFIG_SE_TILE_32 = 0x00000001, } ShaderEngineTileSize; /* * MultiGPUTileSize enum */ typedef enum MultiGPUTileSize { ADDR_CONFIG_GPU_TILE_16 = 0x00000000, ADDR_CONFIG_GPU_TILE_32 = 0x00000001, ADDR_CONFIG_GPU_TILE_64 = 0x00000002, ADDR_CONFIG_GPU_TILE_128 = 0x00000003, } MultiGPUTileSize; /* * NumLowerPipes enum */ typedef enum NumLowerPipes { ADDR_CONFIG_1_LOWER_PIPES = 0x00000000, ADDR_CONFIG_2_LOWER_PIPES = 0x00000001, } NumLowerPipes; /* * ColorTransform enum */ typedef enum ColorTransform { DCC_CT_AUTO = 0x00000000, DCC_CT_NONE = 0x00000001, ABGR_TO_A_BG_G_RB = 0x00000002, BGRA_TO_BG_G_RB_A = 0x00000003, } ColorTransform; /* * CompareRef enum */ typedef enum CompareRef { REF_NEVER = 0x00000000, REF_LESS = 0x00000001, REF_EQUAL = 0x00000002, REF_LEQUAL = 0x00000003, REF_GREATER = 0x00000004, REF_NOTEQUAL = 0x00000005, REF_GEQUAL = 0x00000006, REF_ALWAYS = 0x00000007, } CompareRef; /* * ReadSize enum */ typedef enum ReadSize { READ_256_BITS = 0x00000000, READ_512_BITS = 0x00000001, } ReadSize; /* * DepthFormat enum */ typedef enum DepthFormat { DEPTH_INVALID = 0x00000000, DEPTH_16 = 0x00000001, DEPTH_X8_24 = 0x00000002, DEPTH_8_24 = 0x00000003, DEPTH_X8_24_FLOAT = 0x00000004, DEPTH_8_24_FLOAT = 0x00000005, DEPTH_32_FLOAT = 0x00000006, DEPTH_X24_8_32_FLOAT = 0x00000007, } DepthFormat; /* * ZFormat enum */ typedef enum ZFormat { Z_INVALID = 0x00000000, Z_16 = 0x00000001, Z_24 = 0x00000002, Z_32_FLOAT = 0x00000003, } ZFormat; /* * StencilFormat enum */ typedef enum StencilFormat { STENCIL_INVALID = 0x00000000, STENCIL_8 = 0x00000001, } StencilFormat; /* * CmaskMode enum */ typedef enum CmaskMode { CMASK_CLEAR_NONE = 0x00000000, CMASK_CLEAR_ONE = 0x00000001, CMASK_CLEAR_ALL = 0x00000002, CMASK_ANY_EXPANDED = 0x00000003, CMASK_ALPHA0_FRAG1 = 0x00000004, CMASK_ALPHA0_FRAG2 = 0x00000005, CMASK_ALPHA0_FRAG4 = 0x00000006, CMASK_ALPHA0_FRAGS = 0x00000007, CMASK_ALPHA1_FRAG1 = 0x00000008, CMASK_ALPHA1_FRAG2 = 0x00000009, CMASK_ALPHA1_FRAG4 = 0x0000000a, CMASK_ALPHA1_FRAGS = 0x0000000b, CMASK_ALPHAX_FRAG1 = 0x0000000c, CMASK_ALPHAX_FRAG2 = 0x0000000d, CMASK_ALPHAX_FRAG4 = 0x0000000e, CMASK_ALPHAX_FRAGS = 0x0000000f, } CmaskMode; /* * QuadExportFormat enum */ typedef enum QuadExportFormat { EXPORT_UNUSED = 0x00000000, EXPORT_32_R = 0x00000001, EXPORT_32_GR = 0x00000002, EXPORT_32_AR = 0x00000003, EXPORT_FP16_ABGR = 0x00000004, EXPORT_UNSIGNED16_ABGR = 0x00000005, EXPORT_SIGNED16_ABGR = 0x00000006, EXPORT_32_ABGR = 0x00000007, EXPORT_32BPP_8PIX = 0x00000008, EXPORT_16_16_UNSIGNED_8PIX = 0x00000009, EXPORT_16_16_SIGNED_8PIX = 0x0000000a, EXPORT_16_16_FLOAT_8PIX = 0x0000000b, } QuadExportFormat;