Ketan Patilmemory: tegra: Prepare for supporting multiple intmask registers9f261458 months agoHistory
1337 lines · 23.9 KB · CRawDownload
// SPDX-License-Identifier: GPL-2.0-only/* * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved. */ #include <linux/of.h>#include <linux/device.h>#include <linux/slab.h> #include <dt-bindings/memory/tegra124-mc.h> #include "mc.h" static const struct tegra_mc_client tegra124_mc_clients[] = {	{		.id = 0x00,		.name = "ptcr",		.swgroup = TEGRA_SWGROUP_PTC,		.regs = {			.la = {				.reg = 0x34c,				.shift = 0,				.mask = 0xff,				.def = 0x0,			},		},	}, {		.id = 0x01,		.name = "display0a",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 1,			},			.la = {				.reg = 0x2e8,				.shift = 0,				.mask = 0xff,				.def = 0xc2,			},		},	}, {		.id = 0x02,		.name = "display0ab",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 2,			},			.la = {				.reg = 0x2f4,				.shift = 0,				.mask = 0xff,				.def = 0xc6,			},		},	}, {		.id = 0x03,		.name = "display0b",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 3,			},			.la = {				.reg = 0x2e8,				.shift = 16,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = 0x04,		.name = "display0bb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 4,			},			.la = {				.reg = 0x2f4,				.shift = 16,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = 0x05,		.name = "display0c",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 5,			},			.la = {				.reg = 0x2ec,				.shift = 0,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = 0x06,		.name = "display0cb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 6,			},			.la = {				.reg = 0x2f8,				.shift = 0,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = 0x0e,		.name = "afir",		.swgroup = TEGRA_SWGROUP_AFI,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 14,			},			.la = {				.reg = 0x2e0,				.shift = 0,				.mask = 0xff,				.def = 0x13,			},		},	}, {		.id = 0x0f,		.name = "avpcarm7r",		.swgroup = TEGRA_SWGROUP_AVPC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 15,			},			.la = {				.reg = 0x2e4,				.shift = 0,				.mask = 0xff,				.def = 0x04,			},		},	}, {		.id = 0x10,		.name = "displayhc",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 16,			},			.la = {				.reg = 0x2f0,				.shift = 0,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = 0x11,		.name = "displayhcb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 17,			},			.la = {				.reg = 0x2fc,				.shift = 0,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = 0x15,		.name = "hdar",		.swgroup = TEGRA_SWGROUP_HDA,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 21,			},			.la = {				.reg = 0x318,				.shift = 0,				.mask = 0xff,				.def = 0x24,			},		},	}, {		.id = 0x16,		.name = "host1xdmar",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 22,			},			.la = {				.reg = 0x310,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = 0x17,		.name = "host1xr",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 23,			},			.la = {				.reg = 0x310,				.shift = 16,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = 0x1c,		.name = "msencsrd",		.swgroup = TEGRA_SWGROUP_MSENC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 28,			},			.la = {				.reg = 0x328,				.shift = 0,				.mask = 0xff,				.def = 0x23,			},		},	}, {		.id = 0x1d,		.name = "ppcsahbdmar",		.swgroup = TEGRA_SWGROUP_PPCS,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 29,			},			.la = {				.reg = 0x344,				.shift = 0,				.mask = 0xff,				.def = 0x49,			},		},	}, {		.id = 0x1e,		.name = "ppcsahbslvr",		.swgroup = TEGRA_SWGROUP_PPCS,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 30,			},			.la = {				.reg = 0x344,				.shift = 16,				.mask = 0xff,				.def = 0x1a,			},		},	}, {		.id = 0x1f,		.name = "satar",		.swgroup = TEGRA_SWGROUP_SATA,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 31,			},			.la = {				.reg = 0x350,				.shift = 0,				.mask = 0xff,				.def = 0x65,			},		},	}, {		.id = 0x22,		.name = "vdebsevr",		.swgroup = TEGRA_SWGROUP_VDE,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 2,			},			.la = {				.reg = 0x354,				.shift = 0,				.mask = 0xff,				.def = 0x4f,			},		},	}, {		.id = 0x23,		.name = "vdember",		.swgroup = TEGRA_SWGROUP_VDE,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 3,			},			.la = {				.reg = 0x354,				.shift = 16,				.mask = 0xff,				.def = 0x3d,			},		},	}, {		.id = 0x24,		.name = "vdemcer",		.swgroup = TEGRA_SWGROUP_VDE,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 4,			},			.la = {				.reg = 0x358,				.shift = 0,				.mask = 0xff,				.def = 0x66,			},		},	}, {		.id = 0x25,		.name = "vdetper",		.swgroup = TEGRA_SWGROUP_VDE,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 5,			},			.la = {				.reg = 0x358,				.shift = 16,				.mask = 0xff,				.def = 0xa5,			},		},	}, {		.id = 0x26,		.name = "mpcorelpr",		.swgroup = TEGRA_SWGROUP_MPCORELP,		.regs = {			.la = {				.reg = 0x324,				.shift = 0,				.mask = 0xff,				.def = 0x04,			},		},	}, {		.id = 0x27,		.name = "mpcorer",		.swgroup = TEGRA_SWGROUP_MPCORE,		.regs = {			.la = {				.reg = 0x320,				.shift = 0,				.mask = 0xff,				.def = 0x04,			},		},	}, {		.id = 0x2b,		.name = "msencswr",		.swgroup = TEGRA_SWGROUP_MSENC,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 11,			},			.la = {				.reg = 0x328,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = 0x31,		.name = "afiw",		.swgroup = TEGRA_SWGROUP_AFI,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 17,			},			.la = {				.reg = 0x2e0,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = 0x32,		.name = "avpcarm7w",		.swgroup = TEGRA_SWGROUP_AVPC,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 18,			},			.la = {				.reg = 0x2e4,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = 0x35,		.name = "hdaw",		.swgroup = TEGRA_SWGROUP_HDA,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 21,			},			.la = {				.reg = 0x318,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = 0x36,		.name = "host1xw",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 22,			},			.la = {				.reg = 0x314,				.shift = 0,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = 0x38,		.name = "mpcorelpw",		.swgroup = TEGRA_SWGROUP_MPCORELP,		.regs = {			.la = {				.reg = 0x324,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = 0x39,		.name = "mpcorew",		.swgroup = TEGRA_SWGROUP_MPCORE,		.regs = {			.la = {				.reg = 0x320,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = 0x3b,		.name = "ppcsahbdmaw",		.swgroup = TEGRA_SWGROUP_PPCS,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 27,			},			.la = {

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