// SPDX-License-Identifier: GPL-2.0-only/* * Copyright (C) 2015-2026 NVIDIA CORPORATION.  All rights reserved. */ #include <dt-bindings/memory/tegra210-mc.h> #include "mc.h" static const struct tegra_mc_client tegra210_mc_clients[] = {	{		.id = TEGRA210_MC_PTCR,		.name = "ptcr",		.swgroup = TEGRA_SWGROUP_PTC,	}, {		.id = TEGRA210_MC_DISPLAY0A,		.name = "display0a",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 1,			},			.la = {				.reg = 0x2e8,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_DISPLAY0AB,		.name = "display0ab",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 2,			},			.la = {				.reg = 0x2f4,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_DISPLAY0B,		.name = "display0b",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 3,			},			.la = {				.reg = 0x2e8,				.shift = 16,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_DISPLAY0BB,		.name = "display0bb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 4,			},			.la = {				.reg = 0x2f4,				.shift = 16,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_DISPLAY0C,		.name = "display0c",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 5,			},			.la = {				.reg = 0x2ec,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_DISPLAY0CB,		.name = "display0cb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 6,			},			.la = {				.reg = 0x2f8,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_AFIR,		.name = "afir",		.swgroup = TEGRA_SWGROUP_AFI,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 14,			},			.la = {				.reg = 0x2e0,				.shift = 0,				.mask = 0xff,				.def = 0x2e,			},		},	}, {		.id = TEGRA210_MC_AVPCARM7R,		.name = "avpcarm7r",		.swgroup = TEGRA_SWGROUP_AVPC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 15,			},			.la = {				.reg = 0x2e4,				.shift = 0,				.mask = 0xff,				.def = 0x04,			},		},	}, {		.id = TEGRA210_MC_DISPLAYHC,		.name = "displayhc",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 16,			},			.la = {				.reg = 0x2f0,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_DISPLAYHCB,		.name = "displayhcb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 17,			},			.la = {				.reg = 0x2fc,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_HDAR,		.name = "hdar",		.swgroup = TEGRA_SWGROUP_HDA,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 21,			},			.la = {				.reg = 0x318,				.shift = 0,				.mask = 0xff,				.def = 0x24,			},		},	}, {		.id = TEGRA210_MC_HOST1XDMAR,		.name = "host1xdmar",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 22,			},			.la = {				.reg = 0x310,				.shift = 0,				.mask = 0xff,				.def = 0x1e,			},		},	}, {		.id = TEGRA210_MC_HOST1XR,		.name = "host1xr",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 23,			},			.la = {				.reg = 0x310,				.shift = 16,				.mask = 0xff,				.def = 0x50,			},		},	}, {		.id = TEGRA210_MC_NVENCSRD,		.name = "nvencsrd",		.swgroup = TEGRA_SWGROUP_NVENC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 28,			},			.la = {				.reg = 0x328,				.shift = 0,				.mask = 0xff,				.def = 0x23,			},		},	}, {		.id = TEGRA210_MC_PPCSAHBDMAR,		.name = "ppcsahbdmar",		.swgroup = TEGRA_SWGROUP_PPCS,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 29,			},			.la = {				.reg = 0x344,				.shift = 0,				.mask = 0xff,				.def = 0x49,			},		},	}, {		.id = TEGRA210_MC_PPCSAHBSLVR,		.name = "ppcsahbslvr",		.swgroup = TEGRA_SWGROUP_PPCS,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 30,			},			.la = {				.reg = 0x344,				.shift = 16,				.mask = 0xff,				.def = 0x1a,			},		},	}, {		.id = TEGRA210_MC_SATAR,		.name = "satar",		.swgroup = TEGRA_SWGROUP_SATA,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 31,			},			.la = {				.reg = 0x350,				.shift = 0,				.mask = 0xff,				.def = 0x65,			},		},	}, {		.id = TEGRA210_MC_MPCORER,		.name = "mpcorer",		.swgroup = TEGRA_SWGROUP_MPCORE,		.regs = {			.la = {				.reg = 0x320,				.shift = 0,				.mask = 0xff,				.def = 0x04,			},		},	}, {		.id = TEGRA210_MC_NVENCSWR,		.name = "nvencswr",		.swgroup = TEGRA_SWGROUP_NVENC,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 11,			},			.la = {				.reg = 0x328,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_AFIW,		.name = "afiw",		.swgroup = TEGRA_SWGROUP_AFI,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 17,			},			.la = {				.reg = 0x2e0,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_AVPCARM7W,		.name = "avpcarm7w",		.swgroup = TEGRA_SWGROUP_AVPC,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 18,			},			.la = {				.reg = 0x2e4,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_HDAW,		.name = "hdaw",		.swgroup = TEGRA_SWGROUP_HDA,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 21,			},			.la = {				.reg = 0x318,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_HOST1XW,		.name = "host1xw",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 22,			},			.la = {				.reg = 0x314,				.shift = 0,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_MPCOREW,		.name = "mpcorew",		.swgroup = TEGRA_SWGROUP_MPCORE,		.regs = {			.la = {				.reg = 0x320,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_PPCSAHBDMAW,		.name = "ppcsahbdmaw",		.swgroup = TEGRA_SWGROUP_PPCS,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 27,			},			.la = {				.reg = 0x348,				.shift = 0,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_PPCSAHBSLVW,		.name = "ppcsahbslvw",		.swgroup = TEGRA_SWGROUP_PPCS,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 28,			},			.la = {				.reg = 0x348,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_SATAW,		.name = "sataw",		.swgroup = TEGRA_SWGROUP_SATA,		.regs = {			.smmu = {				.reg = 0x22c,				.bit = 29,			},			.la = {				.reg = 0x350,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_ISPRA,		.name = "ispra",		.swgroup = TEGRA_SWGROUP_ISP2,		.regs = {			.smmu = {				.reg = 0x230,				.bit = 4,			},			.la = {				.reg = 0x370,				.shift = 0,				.mask = 0xff,				.def = 0x18,			},		},	}, {		.id = TEGRA210_MC_ISPWA,		.name = "ispwa",		.swgroup = TEGRA_SWGROUP_ISP2,		.regs = {			.smmu = {				.reg = 0x230,				.bit = 6,			},			.la = {				.reg = 0x374,				.shift = 0,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_ISPWB,		.name = "ispwb",		.swgroup = TEGRA_SWGROUP_ISP2,		.regs = {			.smmu = {				.reg = 0x230,				.bit = 7,			},			.la = {				.reg = 0x374,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},	}, {		.id = TEGRA210_MC_XUSB_HOSTR,		.name = "xusb_hostr",		.swgroup = TEGRA_SWGROUP_XUSB_HOST,		.regs = {			.smmu = {				.reg = 0x230,				.bit = 10,			},			.la = {				.reg = 0x37c,				.shift = 0,				.mask = 0xff,				.def = 0x7a,

Lines 1–500 of 1303. Load more