Ketan Patilmemory: tegra: Prepare for supporting multiple intmask registers9f261458 months agoHistory
1415 lines · 25.1 KB · CRawDownload
// SPDX-License-Identifier: GPL-2.0-only/* * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved. */ #include <linux/device.h>#include <linux/of.h>#include <linux/slab.h> #include <dt-bindings/memory/tegra30-mc.h> #include "mc.h" static const unsigned long tegra30_mc_emem_regs[] = {	MC_EMEM_ARB_CFG,	MC_EMEM_ARB_OUTSTANDING_REQ,	MC_EMEM_ARB_TIMING_RCD,	MC_EMEM_ARB_TIMING_RP,	MC_EMEM_ARB_TIMING_RC,	MC_EMEM_ARB_TIMING_RAS,	MC_EMEM_ARB_TIMING_FAW,	MC_EMEM_ARB_TIMING_RRD,	MC_EMEM_ARB_TIMING_RAP2PRE,	MC_EMEM_ARB_TIMING_WAP2PRE,	MC_EMEM_ARB_TIMING_R2R,	MC_EMEM_ARB_TIMING_W2W,	MC_EMEM_ARB_TIMING_R2W,	MC_EMEM_ARB_TIMING_W2R,	MC_EMEM_ARB_DA_TURNS,	MC_EMEM_ARB_DA_COVERS,	MC_EMEM_ARB_MISC0,	MC_EMEM_ARB_RING1_THROTTLE,}; static const struct tegra_mc_client tegra30_mc_clients[] = {	{		.id = 0x00,		.name = "ptcr",		.swgroup = TEGRA_SWGROUP_PTC,		.regs = {			.la = {				.reg = 0x34c,				.shift = 0,				.mask = 0xff,				.def = 0x0,			},		},		.fifo_size = 16 * 2,	}, {		.id = 0x01,		.name = "display0a",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 1,			},			.la = {				.reg = 0x2e8,				.shift = 0,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 128,	}, {		.id = 0x02,		.name = "display0ab",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 2,			},			.la = {				.reg = 0x2f4,				.shift = 0,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 128,	}, {		.id = 0x03,		.name = "display0b",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 3,			},			.la = {				.reg = 0x2e8,				.shift = 16,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x04,		.name = "display0bb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 4,			},			.la = {				.reg = 0x2f4,				.shift = 16,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x05,		.name = "display0c",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 5,			},			.la = {				.reg = 0x2ec,				.shift = 0,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 128,	}, {		.id = 0x06,		.name = "display0cb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 6,			},			.la = {				.reg = 0x2f8,				.shift = 0,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 128,	}, {		.id = 0x07,		.name = "display1b",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 7,			},			.la = {				.reg = 0x2ec,				.shift = 16,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x08,		.name = "display1bb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 8,			},			.la = {				.reg = 0x2f8,				.shift = 16,				.mask = 0xff,				.def = 0x4e,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x09,		.name = "eppup",		.swgroup = TEGRA_SWGROUP_EPP,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 9,			},			.la = {				.reg = 0x300,				.shift = 0,				.mask = 0xff,				.def = 0x17,			},		},		.fifo_size = 16 * 8,	}, {		.id = 0x0a,		.name = "g2pr",		.swgroup = TEGRA_SWGROUP_G2,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 10,			},			.la = {				.reg = 0x308,				.shift = 0,				.mask = 0xff,				.def = 0x09,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x0b,		.name = "g2sr",		.swgroup = TEGRA_SWGROUP_G2,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 11,			},			.la = {				.reg = 0x308,				.shift = 16,				.mask = 0xff,				.def = 0x09,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x0c,		.name = "mpeunifbr",		.swgroup = TEGRA_SWGROUP_MPE,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 12,			},			.la = {				.reg = 0x328,				.shift = 0,				.mask = 0xff,				.def = 0x50,			},		},		.fifo_size = 16 * 8,	}, {		.id = 0x0d,		.name = "viruv",		.swgroup = TEGRA_SWGROUP_VI,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 13,			},			.la = {				.reg = 0x364,				.shift = 0,				.mask = 0xff,				.def = 0x2c,			},		},		.fifo_size = 16 * 8,	}, {		.id = 0x0e,		.name = "afir",		.swgroup = TEGRA_SWGROUP_AFI,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 14,			},			.la = {				.reg = 0x2e0,				.shift = 0,				.mask = 0xff,				.def = 0x10,			},		},		.fifo_size = 16 * 32,	}, {		.id = 0x0f,		.name = "avpcarm7r",		.swgroup = TEGRA_SWGROUP_AVPC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 15,			},			.la = {				.reg = 0x2e4,				.shift = 0,				.mask = 0xff,				.def = 0x04,			},		},		.fifo_size = 16 * 2,	}, {		.id = 0x10,		.name = "displayhc",		.swgroup = TEGRA_SWGROUP_DC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 16,			},			.la = {				.reg = 0x2f0,				.shift = 0,				.mask = 0xff,				.def = 0xff,			},		},		.fifo_size = 16 * 2,	}, {		.id = 0x11,		.name = "displayhcb",		.swgroup = TEGRA_SWGROUP_DCB,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 17,			},			.la = {				.reg = 0x2fc,				.shift = 0,				.mask = 0xff,				.def = 0xff,			},		},		.fifo_size = 16 * 2,	}, {		.id = 0x12,		.name = "fdcdrd",		.swgroup = TEGRA_SWGROUP_NV,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 18,			},			.la = {				.reg = 0x334,				.shift = 0,				.mask = 0xff,				.def = 0x0a,			},		},		.fifo_size = 16 * 48,	}, {		.id = 0x13,		.name = "fdcdrd2",		.swgroup = TEGRA_SWGROUP_NV2,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 19,			},			.la = {				.reg = 0x33c,				.shift = 0,				.mask = 0xff,				.def = 0x0a,			},		},		.fifo_size = 16 * 48,	}, {		.id = 0x14,		.name = "g2dr",		.swgroup = TEGRA_SWGROUP_G2,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 20,			},			.la = {				.reg = 0x30c,				.shift = 0,				.mask = 0xff,				.def = 0x0a,			},		},		.fifo_size = 16 * 48,	}, {		.id = 0x15,		.name = "hdar",		.swgroup = TEGRA_SWGROUP_HDA,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 21,			},			.la = {				.reg = 0x318,				.shift = 0,				.mask = 0xff,				.def = 0xff,			},		},		.fifo_size = 16 * 16,	}, {		.id = 0x16,		.name = "host1xdmar",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 22,			},			.la = {				.reg = 0x310,				.shift = 0,				.mask = 0xff,				.def = 0x05,			},		},		.fifo_size = 16 * 16,	}, {		.id = 0x17,		.name = "host1xr",		.swgroup = TEGRA_SWGROUP_HC,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 23,			},			.la = {				.reg = 0x310,				.shift = 16,				.mask = 0xff,				.def = 0x50,			},		},		.fifo_size = 16 * 8,	}, {		.id = 0x18,		.name = "idxsrd",		.swgroup = TEGRA_SWGROUP_NV,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 24,			},			.la = {				.reg = 0x334,				.shift = 16,				.mask = 0xff,				.def = 0x13,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x19,		.name = "idxsrd2",		.swgroup = TEGRA_SWGROUP_NV2,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 25,			},			.la = {				.reg = 0x33c,				.shift = 16,				.mask = 0xff,				.def = 0x13,			},		},		.fifo_size = 16 * 64,	}, {		.id = 0x1a,		.name = "mpe_ipred",		.swgroup = TEGRA_SWGROUP_MPE,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 26,			},			.la = {				.reg = 0x328,				.shift = 16,				.mask = 0xff,				.def = 0x80,			},		},		.fifo_size = 16 * 2,	}, {		.id = 0x1b,		.name = "mpeamemrd",		.swgroup = TEGRA_SWGROUP_MPE,		.regs = {			.smmu = {				.reg = 0x228,				.bit = 27,			},			.la = {

Lines 1–500 of 1415.