// SPDX-License-Identifier: GPL-2.0-only/* * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. * *  Copyright (C) 2005 James Chapman (ds1337 core) *  Copyright (C) 2006 David Brownell *  Copyright (C) 2009 Matthias Fuchs (rx8025 support) *  Copyright (C) 2012 Bertrand Achard (nvram access fixes) */ #include <linux/bcd.h>#include <linux/i2c.h>#include <linux/init.h>#include <linux/kstrtox.h>#include <linux/module.h>#include <linux/property.h>#include <linux/rtc/ds1307.h>#include <linux/rtc.h>#include <linux/slab.h>#include <linux/string.h>#include <linux/hwmon.h>#include <linux/hwmon-sysfs.h>#include <linux/clk-provider.h>#include <linux/regmap.h>#include <linux/watchdog.h> /* * We can't determine type by probing, but if we expect pre-Linux code * to have set the chip up as a clock (turning on the oscillator and * setting the date and time), Linux can ignore the non-clock features. * That's a natural job for a factory or repair bench. */enum ds_type {	unknown_ds_type, /* always first and 0 */	ds_1307,	ds_1308,	ds_1337,	ds_1338,	ds_1339,	ds_1340,	ds_1341,	ds_1388,	ds_3231,	m41t0,	m41t00,	m41t11,	mcp794xx,	rx_8025,	rx_8130,	last_ds_type /* always last */	/* rs5c372 too?  different address... */}; /* RTC registers don't differ much, except for the century flag */#define DS1307_REG_SECS		0x00	/* 00-59 */#	define DS1307_BIT_CH		0x80#	define DS1340_BIT_nEOSC		0x80#	define MCP794XX_BIT_ST		0x80#define DS1307_REG_MIN		0x01	/* 00-59 */#	define M41T0_BIT_OF		0x80#define DS1307_REG_HOUR		0x02	/* 00-23, or 1-12{am,pm} */#	define DS1307_BIT_12HR		0x40	/* in REG_HOUR */#	define DS1307_BIT_PM		0x20	/* in REG_HOUR */#	define DS1340_BIT_CENTURY_EN	0x80	/* in REG_HOUR */#	define DS1340_BIT_CENTURY	0x40	/* in REG_HOUR */#define DS1307_REG_WDAY		0x03	/* 01-07 */#	define MCP794XX_BIT_OSCRUN	BIT(5)#	define MCP794XX_BIT_VBATEN	0x08#define DS1307_REG_MDAY		0x04	/* 01-31 */#define DS1307_REG_MONTH	0x05	/* 01-12 */#	define DS1337_BIT_CENTURY	0x80	/* in REG_MONTH */#define DS1307_REG_YEAR		0x06	/* 00-99 */ /* * Other registers (control, status, alarms, trickle charge, NVRAM, etc) * start at 7, and they differ a LOT. Only control and status matter for * basic RTC date and time functionality; be careful using them. */#define DS1307_REG_CONTROL	0x07		/* or ds1338 */#	define DS1307_BIT_OUT		0x80#	define DS1338_BIT_OSF		0x20#	define DS1307_BIT_SQWE		0x10#	define DS1307_BIT_RS1		0x02#	define DS1307_BIT_RS0		0x01#define DS1337_REG_CONTROL	0x0e#	define DS1337_BIT_nEOSC		0x80#	define DS1339_BIT_BBSQI		0x20#	define DS3231_BIT_BBSQW		0x40 /* same as BBSQI */#	define DS1337_BIT_RS2		0x10#	define DS1337_BIT_RS1		0x08#	define DS1337_BIT_INTCN		0x04#	define DS1337_BIT_A2IE		0x02#	define DS1337_BIT_A1IE		0x01#define DS1340_REG_CONTROL	0x07#	define DS1340_BIT_OUT		0x80#	define DS1340_BIT_FT		0x40#	define DS1340_BIT_CALIB_SIGN	0x20#	define DS1340_M_CALIBRATION	0x1f#define DS1340_REG_FLAG		0x09#	define DS1340_BIT_OSF		0x80#define DS1337_REG_STATUS	0x0f#	define DS1337_BIT_OSF		0x80#	define DS3231_BIT_EN32KHZ	0x08#	define DS1337_BIT_A2I		0x02#	define DS1337_BIT_A1I		0x01#define DS1339_REG_ALARM1_SECS	0x07 #define DS13XX_TRICKLE_CHARGER_MAGIC	0xa0 #define RX8025_REG_CTRL1	0x0e#	define RX8025_BIT_2412		0x20#define RX8025_REG_CTRL2	0x0f#	define RX8025_BIT_PON		0x10#	define RX8025_BIT_VDET		0x40#	define RX8025_BIT_XST		0x20 #define RX8130_REG_ALARM_MIN		0x17#define RX8130_REG_ALARM_HOUR		0x18#define RX8130_REG_ALARM_WEEK_OR_DAY	0x19#define RX8130_REG_EXTENSION		0x1c#define RX8130_REG_EXTENSION_WADA	BIT(3)#define RX8130_REG_FLAG			0x1d#define RX8130_REG_FLAG_VLF		BIT(1)#define RX8130_REG_FLAG_AF		BIT(3)#define RX8130_REG_CONTROL0		0x1e#define RX8130_REG_CONTROL0_AIE		BIT(3)#define RX8130_REG_CONTROL1		0x1f#define RX8130_REG_CONTROL1_INIEN	BIT(4)#define RX8130_REG_CONTROL1_CHGEN	BIT(5) #define MCP794XX_REG_CONTROL		0x07#	define MCP794XX_BIT_ALM0_EN	0x10#	define MCP794XX_BIT_ALM1_EN	0x20#define MCP794XX_REG_ALARM0_BASE	0x0a#define MCP794XX_REG_ALARM0_CTRL	0x0d#define MCP794XX_REG_ALARM1_BASE	0x11#define MCP794XX_REG_ALARM1_CTRL	0x14#	define MCP794XX_BIT_ALMX_IF	BIT(3)#	define MCP794XX_BIT_ALMX_C0	BIT(4)#	define MCP794XX_BIT_ALMX_C1	BIT(5)#	define MCP794XX_BIT_ALMX_C2	BIT(6)#	define MCP794XX_BIT_ALMX_POL	BIT(7)#	define MCP794XX_MSK_ALMX_MATCH	(MCP794XX_BIT_ALMX_C0 | \					 MCP794XX_BIT_ALMX_C1 | \					 MCP794XX_BIT_ALMX_C2) #define M41TXX_REG_CONTROL	0x07#	define M41TXX_BIT_OUT		BIT(7)#	define M41TXX_BIT_FT		BIT(6)#	define M41TXX_BIT_CALIB_SIGN	BIT(5)#	define M41TXX_M_CALIBRATION	GENMASK(4, 0) #define DS1388_REG_WDOG_HUN_SECS	0x08#define DS1388_REG_WDOG_SECS		0x09#define DS1388_REG_FLAG			0x0b#	define DS1388_BIT_WF		BIT(6)#	define DS1388_BIT_OSF		BIT(7)#define DS1388_REG_CONTROL		0x0c#	define DS1388_BIT_RST		BIT(0)#	define DS1388_BIT_WDE		BIT(1)#	define DS1388_BIT_nEOSC		BIT(7) /* negative offset step is -2.034ppm */#define M41TXX_NEG_OFFSET_STEP_PPB	2034/* positive offset step is +4.068ppm */#define M41TXX_POS_OFFSET_STEP_PPB	4068/* Min and max values supported with 'offset' interface by M41TXX */#define M41TXX_MIN_OFFSET	((-31) * M41TXX_NEG_OFFSET_STEP_PPB)#define M41TXX_MAX_OFFSET	((31) * M41TXX_POS_OFFSET_STEP_PPB) struct ds1307 {	enum ds_type		type;	struct device		*dev;	struct regmap		*regmap;	const char		*name;	struct rtc_device	*rtc;#ifdef CONFIG_COMMON_CLK	struct clk_hw		clks[2];#endif}; struct chip_desc {	unsigned		alarm:1;	u16			nvram_offset;	u16			nvram_size;	u8			offset; /* register's offset */	u8			century_reg;	u8			century_enable_bit;	u8			century_bit;	u8			bbsqi_bit;	irq_handler_t		irq_handler;	const struct rtc_class_ops *rtc_ops;	u16			trickle_charger_reg;	u8			(*do_trickle_setup)(struct ds1307 *, u32,						    bool);	/* Does the RTC require trickle-resistor-ohms to select the value of	 * the resistor between Vcc and Vbackup?	 */	bool			requires_trickle_resistor;	/* Some RTC's batteries and supercaps were charged by default, others	 * allow charging but were not configured previously to do so.	 * Remember this behavior to stay backwards compatible.	 */	bool			charge_default;}; static const struct chip_desc chips[last_ds_type]; static int ds1307_get_time(struct device *dev, struct rtc_time *t){	struct ds1307	*ds1307 = dev_get_drvdata(dev);	int		tmp, ret;	const struct chip_desc *chip = &chips[ds1307->type];	u8 regs[7]; 	if (ds1307->type == rx_8130) {		unsigned int regflag;		ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);		if (ret) {			dev_err(dev, "%s error %d\n", "read", ret);			return ret;		} 		if (regflag & RX8130_REG_FLAG_VLF) {			dev_warn_once(dev, "oscillator failed, set time!\n");			return -EINVAL;		}	} 	/* read the RTC date and time registers all at once */	ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,			       sizeof(regs));	if (ret) {		dev_err(dev, "%s error %d\n", "read", ret);		return ret;	} 	dev_dbg(dev, "%s: %7ph\n", "read", regs); 	/* if oscillator fail bit is set, no data can be trusted */	if (ds1307->type == m41t0 &&	    regs[DS1307_REG_MIN] & M41T0_BIT_OF) {		dev_warn_once(dev, "oscillator failed, set time!\n");		return -EINVAL;	} else if (ds1307->type == mcp794xx &&	    !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_OSCRUN)) {		dev_warn_once(dev, "oscillator failed, set time!\n");		return -EINVAL;	} 	tmp = regs[DS1307_REG_SECS];	switch (ds1307->type) {	case ds_1307:	case m41t0:	case m41t00:	case m41t11:		if (tmp & DS1307_BIT_CH)			return -EINVAL;		break;	case ds_1308:	case ds_1338:		if (tmp & DS1307_BIT_CH)			return -EINVAL; 		ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);		if (ret)			return ret;		if (tmp & DS1338_BIT_OSF)			return -EINVAL;		break;	case ds_1337:	case ds_1339:	case ds_1341:	case ds_3231:		ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &tmp);		if (ret)			return ret;		if (tmp & DS1337_BIT_OSF)			return -EINVAL;		break;	case ds_1340:		if (tmp & DS1340_BIT_nEOSC)			return -EINVAL; 		ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);		if (ret)			return ret;		if (tmp & DS1340_BIT_OSF)			return -EINVAL;		break;	case ds_1388:		ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);		if (ret)			return ret;		if (tmp & DS1388_BIT_OSF)			return -EINVAL;		break;	case mcp794xx:		if (!(tmp & MCP794XX_BIT_ST))			return -EINVAL; 		break;	default:		break;	} 	t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);	t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);	tmp = regs[DS1307_REG_HOUR] & 0x3f;	t->tm_hour = bcd2bin(tmp);	/* rx8130 is bit position, not BCD */	if (ds1307->type == rx_8130)		t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f) - 1;	else		t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;	t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);	tmp = regs[DS1307_REG_MONTH] & 0x1f;	t->tm_mon = bcd2bin(tmp) - 1;	t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 	if (regs[chip->century_reg] & chip->century_bit &&	    IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))		t->tm_year += 100; 	dev_dbg(dev, "%s secs=%d, mins=%d, "		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",		"read", t->tm_sec, t->tm_min,		t->tm_hour, t->tm_mday,		t->tm_mon, t->tm_year, t->tm_wday); 	return 0;} static int ds1307_set_time(struct device *dev, struct rtc_time *t){	struct ds1307	*ds1307 = dev_get_drvdata(dev);	const struct chip_desc *chip = &chips[ds1307->type];	int		result;	int		tmp;	u8		regs[7]; 	dev_dbg(dev, "%s secs=%d, mins=%d, "		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",		"write", t->tm_sec, t->tm_min,		t->tm_hour, t->tm_mday,		t->tm_mon, t->tm_year, t->tm_wday); 	if (t->tm_year < 100)		return -EINVAL; #ifdef CONFIG_RTC_DRV_DS1307_CENTURY	if (t->tm_year > (chip->century_bit ? 299 : 199))		return -EINVAL;#else	if (t->tm_year > 199)		return -EINVAL;#endif 	regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);	regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);	regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);	/* rx8130 is bit position, not BCD */	if (ds1307->type == rx_8130)		regs[DS1307_REG_WDAY] = 1 << t->tm_wday;	else		regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);	regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);	regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 	/* assume 20YY not 19YY */	tmp = t->tm_year % 100;	regs[DS1307_REG_YEAR] = bin2bcd(tmp); 	if (chip->century_enable_bit)		regs[chip->century_reg] |= chip->century_enable_bit;	if (t->tm_year > 199 && chip->century_bit)		regs[chip->century_reg] |= chip->century_bit; 	switch (ds1307->type) {	case ds_1308:	case ds_1338:		regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,				   DS1338_BIT_OSF, 0);		break;	case ds_1337:	case ds_1339:	case ds_1341:	case ds_3231:		regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,				   DS1337_BIT_OSF, 0);		break;	case ds_1340:		regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,				   DS1340_BIT_OSF, 0);		break;	case ds_1388:		regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,				   DS1388_BIT_OSF, 0);		break;	case mcp794xx:		/*		 * these bits were cleared when preparing the date/time		 * values and need to be set again before writing the		 * regsfer out to the device.		 */		regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;		regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;		break;	default:		break;	} 	dev_dbg(dev, "%s: %7ph\n", "write", regs); 	result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,				   sizeof(regs));	if (result) {		dev_err(dev, "%s error %d\n", "write", result);		return result;	} 	if (ds1307->type == rx_8130) {		/* clear Voltage Loss Flag as data is available now */		result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,				      ~(u8)RX8130_REG_FLAG_VLF);		if (result) {			dev_err(dev, "%s error %d\n", "write", result);			return result;		}	} 	return 0;} static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t){	struct ds1307		*ds1307 = dev_get_drvdata(dev);	int			ret;	u8			regs[9]; 	/* read all ALARM1, ALARM2, and status registers at once */	ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,			       regs, sizeof(regs));	if (ret) {		dev_err(dev, "%s error %d\n", "alarm read", ret);		return ret;	} 	dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",		&regs[0], &regs[4], &regs[7]); 	/*	 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,	 * and that all four fields are checked matches	 */	t->time.tm_sec = bcd2bin(regs[0] & 0x7f);	t->time.tm_min = bcd2bin(regs[1] & 0x7f);	t->time.tm_hour = bcd2bin(regs[2] & 0x3f);	t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 	/* ... and status */	t->enabled = !!(regs[7] & DS1337_BIT_A1IE);	t->pending = !!(regs[8] & DS1337_BIT_A1I); 	dev_dbg(dev, "%s secs=%d, mins=%d, "		"hours=%d, mday=%d, enabled=%d, pending=%d\n",		"alarm read", t->time.tm_sec, t->time.tm_min,		t->time.tm_hour, t->time.tm_mday,		t->enabled, t->pending); 	return 0;} static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t){	struct ds1307		*ds1307 = dev_get_drvdata(dev);	unsigned char		regs[9];	u8			control, status;	int			ret; 	dev_dbg(dev, "%s secs=%d, mins=%d, "		"hours=%d, mday=%d, enabled=%d, pending=%d\n",		"alarm set", t->time.tm_sec, t->time.tm_min,		t->time.tm_hour, t->time.tm_mday,		t->enabled, t->pending); 	/* read current status of both alarms and the chip */	ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,			       sizeof(regs));	if (ret) {		dev_err(dev, "%s error %d\n", "alarm write", ret);		return ret;	}	control = regs[7];	status = regs[8]; 	dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",		&regs[0], &regs[4], control, status); 	/* set ALARM1, using 24 hour and day-of-month modes */

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