// SPDX-License-Identifier: GPL-2.0-or-later/* * An RTC driver for Allwinner A31/A23 * * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> * * based on rtc-sunxi.c * * An RTC driver for Allwinner A10/A20 * * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> */ #include <linux/clk.h>#include <linux/clk-provider.h>#include <linux/clk/sunxi-ng.h>#include <linux/delay.h>#include <linux/err.h>#include <linux/fs.h>#include <linux/init.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/platform_device.h>#include <linux/rtc.h>#include <linux/slab.h>#include <linux/types.h> /* Control register */#define SUN6I_LOSC_CTRL				0x0000#define SUN6I_LOSC_CTRL_KEY			(0x16aa << 16)#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS		BIT(15)#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC		BIT(9)#define SUN6I_LOSC_CTRL_RTC_HMS_ACC		BIT(8)#define SUN6I_LOSC_CTRL_RTC_YMD_ACC		BIT(7)#define SUN6I_LOSC_CTRL_EXT_LOSC_EN		BIT(4)#define SUN6I_LOSC_CTRL_EXT_OSC			BIT(0)#define SUN6I_LOSC_CTRL_ACC_MASK		GENMASK(9, 7) #define SUN6I_LOSC_CLK_PRESCAL			0x0008 /* RTC */#define SUN6I_RTC_YMD				0x0010#define SUN6I_RTC_HMS				0x0014 /* Alarm 0 (counter) */#define SUN6I_ALRM_COUNTER			0x0020/* This holds the remaining alarm seconds on older SoCs (current value) */#define SUN6I_ALRM_COUNTER_HMS			0x0024#define SUN6I_ALRM_EN				0x0028#define SUN6I_ALRM_EN_CNT_EN			BIT(0)#define SUN6I_ALRM_IRQ_EN			0x002c#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN		BIT(0)#define SUN6I_ALRM_IRQ_STA			0x0030#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND		BIT(0) /* Alarm 1 (wall clock) */#define SUN6I_ALRM1_EN				0x0044#define SUN6I_ALRM1_IRQ_EN			0x0048#define SUN6I_ALRM1_IRQ_STA			0x004c#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND	BIT(0) /* Alarm config */#define SUN6I_ALARM_CONFIG			0x0050#define SUN6I_ALARM_CONFIG_WAKEUP		BIT(0) #define SUN6I_LOSC_OUT_GATING			0x0060#define SUN6I_LOSC_OUT_GATING_EN_OFFSET		0 /* General-purpose data */#define SUN6I_GP_DATA				0x0100#define SUN6I_GP_DATA_SIZE			0x20 /* * Get date values */#define SUN6I_DATE_GET_DAY_VALUE(x)		((x)  & 0x0000001f)#define SUN6I_DATE_GET_MON_VALUE(x)		(((x) & 0x00000f00) >> 8)#define SUN6I_DATE_GET_YEAR_VALUE(x)		(((x) & 0x003f0000) >> 16)#define SUN6I_LEAP_GET_VALUE(x)			(((x) & 0x00400000) >> 22) /* * Get time values */#define SUN6I_TIME_GET_SEC_VALUE(x)		((x)  & 0x0000003f)#define SUN6I_TIME_GET_MIN_VALUE(x)		(((x) & 0x00003f00) >> 8)#define SUN6I_TIME_GET_HOUR_VALUE(x)		(((x) & 0x001f0000) >> 16) /* * Set date values */#define SUN6I_DATE_SET_DAY_VALUE(x)		((x)       & 0x0000001f)#define SUN6I_DATE_SET_MON_VALUE(x)		((x) <<  8 & 0x00000f00)#define SUN6I_DATE_SET_YEAR_VALUE(x)		((x) << 16 & 0x003f0000)#define SUN6I_LEAP_SET_VALUE(x)			((x) << 22 & 0x00400000) /* * Set time values */#define SUN6I_TIME_SET_SEC_VALUE(x)		((x)       & 0x0000003f)#define SUN6I_TIME_SET_MIN_VALUE(x)		((x) <<  8 & 0x00003f00)#define SUN6I_TIME_SET_HOUR_VALUE(x)		((x) << 16 & 0x001f0000) /* * The year parameter passed to the driver is usually an offset relative to * the year 1900. This macro is used to convert this offset to another one * relative to the minimum year allowed by the hardware. * * The year range is 1970 - 2033. This range is selected to match Allwinner's * driver, even though it is somewhat limited. */#define SUN6I_YEAR_MIN				1970#define SUN6I_YEAR_OFF				(SUN6I_YEAR_MIN - 1900) #define SECS_PER_DAY				(24 * 3600ULL) /* * There are other differences between models, including: * *   - number of GPIO pins that can be configured to hold a certain level *   - crypto-key related registers (H5, H6) *   - boot process related (super standby, secondary processor entry address) *     registers (R40, H6) *   - SYS power domain controls (R40) *   - DCXO controls (H6) *   - RC oscillator calibration (H6) * * These functions are not covered by this driver. */struct sun6i_rtc_clk_data {	unsigned long rc_osc_rate;	unsigned int fixed_prescaler : 16;	unsigned int has_prescaler : 1;	unsigned int has_out_clk : 1;	unsigned int has_losc_en : 1;	unsigned int has_auto_swt : 1;}; #define RTC_LINEAR_DAY	BIT(0) struct sun6i_rtc_dev {	struct rtc_device *rtc;	const struct sun6i_rtc_clk_data *data;	void __iomem *base;	int irq;	time64_t alarm;	unsigned long flags; 	struct clk_hw hw;	struct clk_hw *int_osc;	struct clk *losc;	struct clk *ext_losc; 	spinlock_t lock;}; static struct sun6i_rtc_dev *sun6i_rtc; static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,					       unsigned long parent_rate){	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);	u32 val = 0; 	val = readl(rtc->base + SUN6I_LOSC_CTRL);	if (val & SUN6I_LOSC_CTRL_EXT_OSC)		return parent_rate; 	if (rtc->data->fixed_prescaler)		parent_rate /= rtc->data->fixed_prescaler; 	if (rtc->data->has_prescaler) {		val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);		val &= GENMASK(4, 0);	} 	return parent_rate / (val + 1);} static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw){	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 	return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;} static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index){	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);	unsigned long flags;	u32 val; 	if (index > 1)		return -EINVAL; 	spin_lock_irqsave(&rtc->lock, flags);	val = readl(rtc->base + SUN6I_LOSC_CTRL);	val &= ~SUN6I_LOSC_CTRL_EXT_OSC;	val |= SUN6I_LOSC_CTRL_KEY;	val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;	if (rtc->data->has_losc_en) {		val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;		val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;	}	writel(val, rtc->base + SUN6I_LOSC_CTRL);	spin_unlock_irqrestore(&rtc->lock, flags); 	return 0;} static const struct clk_ops sun6i_rtc_osc_ops = {	.recalc_rate	= sun6i_rtc_osc_recalc_rate,	.determine_rate	= clk_hw_determine_rate_no_reparent, 	.get_parent	= sun6i_rtc_osc_get_parent,	.set_parent	= sun6i_rtc_osc_set_parent,}; static void __init sun6i_rtc_clk_init(struct device_node *node,				      const struct sun6i_rtc_clk_data *data){	struct clk_hw_onecell_data *clk_data;	struct sun6i_rtc_dev *rtc;	struct clk_init_data init = {		.ops		= &sun6i_rtc_osc_ops,		.name		= "losc",	};	const char *iosc_name = "rtc-int-osc";	const char *clkout_name = "osc32k-out";	const char *parents[2];	u32 reg; 	rtc = kzalloc_obj(*rtc);	if (!rtc)		return; 	rtc->data = data;	clk_data = kzalloc_flex(*clk_data, hws, 3);	if (!clk_data) {		kfree(rtc);		return;	} 	spin_lock_init(&rtc->lock); 	rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));	if (IS_ERR(rtc->base)) {		pr_crit("Can't map RTC registers");		goto err;	} 	reg = SUN6I_LOSC_CTRL_KEY;	if (rtc->data->has_auto_swt) {		/* Bypass auto-switch to int osc, on ext losc failure */		reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;		writel(reg, rtc->base + SUN6I_LOSC_CTRL);	} 	/* Switch to the external, more precise, oscillator, if present */	if (of_property_present(node, "clocks")) {		reg |= SUN6I_LOSC_CTRL_EXT_OSC;		if (rtc->data->has_losc_en)			reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;	}	writel(reg, rtc->base + SUN6I_LOSC_CTRL); 	/* Yes, I know, this is ugly. */	sun6i_rtc = rtc; 	of_property_read_string_index(node, "clock-output-names", 2,				      &iosc_name); 	rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,								iosc_name,								NULL, 0,								rtc->data->rc_osc_rate,								300000000);	if (IS_ERR(rtc->int_osc)) {		pr_crit("Couldn't register the internal oscillator\n");		goto err;	} 	parents[0] = clk_hw_get_name(rtc->int_osc);	/* If there is no external oscillator, this will be NULL and ... */	parents[1] = of_clk_get_parent_name(node, 0); 	rtc->hw.init = &init; 	init.parent_names = parents;	/* ... number of clock parents will be 1. */	init.num_parents = of_clk_get_parent_count(node) + 1;	of_property_read_string_index(node, "clock-output-names", 0,				      &init.name); 	rtc->losc = clk_register(NULL, &rtc->hw);	if (IS_ERR(rtc->losc)) {		pr_crit("Couldn't register the LOSC clock\n");		goto err_register;	} 	of_property_read_string_index(node, "clock-output-names", 1,				      &clkout_name);	rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,					  0, rtc->base + SUN6I_LOSC_OUT_GATING,					  SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,					  &rtc->lock);	if (IS_ERR(rtc->ext_losc)) {		pr_crit("Couldn't register the LOSC external gate\n");		goto err_register;	} 	clk_data->num = 3;	clk_data->hws[0] = &rtc->hw;	clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);	clk_data->hws[2] = rtc->int_osc;	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);	return; err_register:	clk_hw_unregister_fixed_rate(rtc->int_osc);err:	kfree(clk_data);} static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {	.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */	.has_prescaler = 1,}; static void __init sun6i_a31_rtc_clk_init(struct device_node *node){	sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);}CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",		      sun6i_a31_rtc_clk_init); static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {	.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */	.has_prescaler = 1,	.has_out_clk = 1,}; static void __init sun8i_a23_rtc_clk_init(struct device_node *node){	sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);}CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",		      sun8i_a23_rtc_clk_init); static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {	.rc_osc_rate = 16000000,	.fixed_prescaler = 32,	.has_prescaler = 1,	.has_out_clk = 1,}; static void __init sun8i_h3_rtc_clk_init(struct device_node *node){	sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);}CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",		      sun8i_h3_rtc_clk_init);/* As far as we are concerned, clocks for H5 are the same as H3 */CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",		      sun8i_h3_rtc_clk_init); static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {	.rc_osc_rate = 16000000,	.fixed_prescaler = 32,	.has_prescaler = 1,	.has_out_clk = 1,	.has_losc_en = 1,	.has_auto_swt = 1,}; static void __init sun50i_h6_rtc_clk_init(struct device_node *node){	sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);}CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",		      sun50i_h6_rtc_clk_init); /* * The R40 user manual is self-conflicting on whether the prescaler is * fixed or configurable. The clock diagram shows it as fixed, but there * is also a configurable divider in the RTC block. */static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {	.rc_osc_rate = 16000000,	.fixed_prescaler = 512,};static void __init sun8i_r40_rtc_clk_init(struct device_node *node){	sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);}CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",		      sun8i_r40_rtc_clk_init); static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {	.rc_osc_rate = 32000,	.has_out_clk = 1,	.has_auto_swt = 1,}; static void __init sun8i_v3_rtc_clk_init(struct device_node *node){	sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);}CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",		      sun8i_v3_rtc_clk_init); static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id){	struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;	irqreturn_t ret = IRQ_NONE;	u32 val; 	spin_lock(&chip->lock);	val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 	if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {		val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;		writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 		rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 		ret = IRQ_HANDLED;	}	spin_unlock(&chip->lock); 	return ret;} static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip){	u32 alrm_val = 0;	u32 alrm_irq_val = 0;	u32 alrm_wake_val = 0;	unsigned long flags; 	if (to) {		alrm_val = SUN6I_ALRM_EN_CNT_EN;		alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;		alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;	} else {		writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,		       chip->base + SUN6I_ALRM_IRQ_STA);	} 	spin_lock_irqsave(&chip->lock, flags);	writel(alrm_val, chip->base + SUN6I_ALRM_EN);	writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);	writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);	spin_unlock_irqrestore(&chip->lock, flags);} static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm){	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);	u32 date, time; 	/*	 * read again in case it changes	 */	do {		date = readl(chip->base + SUN6I_RTC_YMD);		time = readl(chip->base + SUN6I_RTC_HMS);	} while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||		 (time != readl(chip->base + SUN6I_RTC_HMS))); 	if (chip->flags & RTC_LINEAR_DAY) {		/*		 * Newer chips store a linear day number, the manual		 * does not mandate any epoch base. The BSP driver uses		 * the UNIX epoch, let's just copy that, as it's the		 * easiest anyway.		 */		rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm);	} else {		rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);		rtc_tm->tm_mon  = SUN6I_DATE_GET_MON_VALUE(date) - 1;		rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 		/*		 * switch from (data_year->min)-relative offset to		 * a (1900)-relative one		 */		rtc_tm->tm_year += SUN6I_YEAR_OFF;	} 	rtc_tm->tm_sec  = SUN6I_TIME_GET_SEC_VALUE(time);	rtc_tm->tm_min  = SUN6I_TIME_GET_MIN_VALUE(time);	rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 	return 0;} 

Lines 1–500 of 883. Load more