Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd: - build fix to export the clk_bulk_prepare() symbol - suspend fix for Samsung Exynos SoCs where we need to keep clks on across suspend - two critical clk markings for clks that shouldn't ever turn off on Rockchip SoCs - a fix for a copy-paste mistake on Rockchip rk3128 causing some clks to touch the same bit and trample over one another * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle clk: Export clk_bulk_prepare() clk: rockchip: add sclk_timer5 as critical clock on rk3128 clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error clk: rockchip: add pclk_pmu as critical clock on rk3128

Linus Torvalds committed 9 years ago

Commit dbeb1a82 parents ed0f72f 5dcbeca3 files · +23 −5Browse files

Unified · Split

3 files

drivers/clk/clk-bulk.c +1 −0
drivers/clk/rockchip/clk-rk3128.c +7 −5
drivers/clk/samsung/clk-exynos4.c +15 −0

drivers/clk/clk-bulk.c+1−0

@@ -105,6 +105,7 @@ err: · 104 unmodified lines
105	105
106	106	return ret;
107	107	}
	108	+EXPORT_SYMBOL_GPL(clk_bulk_prepare);
108	109
109	110	#endif /* CONFIG_HAVE_CLK_PREPARE */
110	111

drivers/clk/rockchip/clk-rk3128.c+7−5

@@ -315,13 +315,13 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { · 314 unmodified lines
315	315	RK2928_CLKGATE_CON(10), 8, GFLAGS),
316	316
317	317	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
318		− RK2928_CLKGATE_CON(10), 8, GFLAGS),
	318	+ RK2928_CLKGATE_CON(10), 0, GFLAGS),
319	319	GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,
320		− RK2928_CLKGATE_CON(10), 8, GFLAGS),
	320	+ RK2928_CLKGATE_CON(10), 1, GFLAGS),
321	321	GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
322		− RK2928_CLKGATE_CON(10), 8, GFLAGS),
	322	+ RK2928_CLKGATE_CON(10), 2, GFLAGS),
323	323	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
324		− RK2928_CLKGATE_CON(10), 8, GFLAGS),
	324	+ RK2928_CLKGATE_CON(2), 15, GFLAGS),
325	325
326	326	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
327	327	RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
@@ -541,7 +541,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { · 213 unmodified lines
541	541	GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
542	542	GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),
543	543
544		− GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 2, GFLAGS),
	544	+ GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
545	545	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
546	546
547	547	/* PD_MMC */
@@ -577,6 +577,8 @@ static const char *const rk3128_critical_clocks[] __initconst = { · 29 unmodified lines
577	577	"aclk_peri",
578	578	"hclk_peri",
579	579	"pclk_peri",
	580	+ "pclk_pmu",
	581	+ "sclk_timer5",
580	582	};
581	583
582	584	static struct rockchip_clk_provider __init rk3128_common_clk_init(struct device_node np)

drivers/clk/samsung/clk-exynos4.c+15−0

@@ -294,6 +294,18 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { · 293 unmodified lines
294	294	#define PLL_ENABLED (1 << 31)
295	295	#define PLL_LOCKED (1 << 29)
296	296
	297	+static void exynos4_clk_enable_pll(u32 reg)
	298	+{
	299	+ u32 pll_con = readl(reg_base + reg);
	300	+ pll_con \|= PLL_ENABLED;
	301	+ writel(pll_con, reg_base + reg);
	302	+
	303	+ while (!(pll_con & PLL_LOCKED)) {
	304	+ cpu_relax();
	305	+ pll_con = readl(reg_base + reg);
	306	+ }
	307	+}
	308	+
297	309	static void exynos4_clk_wait_for_pll(u32 reg)
298	310	{
299	311	u32 pll_con;
@@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) · 15 unmodified lines
315	327	samsung_clk_save(reg_base, exynos4_save_pll,
316	328	ARRAY_SIZE(exynos4_clk_pll_regs));
317	329
	330	+ exynos4_clk_enable_pll(EPLL_CON0);
	331	+ exynos4_clk_enable_pll(VPLL_CON0);
	332	+
318	333	if (exynos4_soc == EXYNOS4210) {
319	334	samsung_clk_save(reg_base, exynos4_save_soc,
320	335	ARRAY_SIZE(exynos4210_clk_save));

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

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