/* * bootstrap driver for * Intel RS-82543GC Gigabit Ethernet PCI Controllers * as found on the Intel PRO/1000[FT] Server Adapter. * The older non-[FT] cards use the 82542 (LSI L2A1157) chip; no attempt * is made to handle the older chip although it should be possible. * * updated just enough to cope with the * Intel 8254[0347]NN Gigabit Ethernet Controller * as found on the Intel PRO/1000 series of adapters: *	82540EM Intel PRO/1000 MT *	82543GC	Intel PRO/1000 T *	82544EI Intel PRO/1000 XT *	82547EI built-in * * The datasheet is not very clear about running on a big-endian system * and this driver assumes little-endian throughout. * To do: *	GMII/MII *	check recovery from receive no buffers condition *	automatic ett adjustment */#include "u.h"#include "lib.h"#include "mem.h"#include "dat.h"#include "fns.h"#include "io.h" #include "etherif.h"#include "ethermii.h" enum {	Debug = 0,		/* mostly for X60 debugging */};enum {	i82542		= (0x1000<<16)|0x8086,	i82543gc	= (0x1004<<16)|0x8086,	i82544ei	= (0x1008<<16)|0x8086,	i82547ei	= (0x1019<<16)|0x8086,	i82540em	= (0x100E<<16)|0x8086,	i82540eplp	= (0x101E<<16)|0x8086,	i82545em	= (0x100F<<16)|0x8086,	i82545gmc	= (0x1026<<16)|0x8086,	i82547gi	= (0x1075<<16)|0x8086,	i82541gi	= (0x1076<<16)|0x8086,	i82541gi2	= (0x1077<<16)|0x8086,	i82546gb	= (0x1079<<16)|0x8086,	i82541pi	= (0x107c<<16)|0x8086,	i82546eb	= (0x1010<<16)|0x8086,}; /* compatibility with cpu kernels */#define iallocb allocb#ifndef CACHELINESZ#define CACHELINESZ	32		/* pentium & later */#endif /* from pci.c */enum{					/* command register (pcidev->pcr) */	IOen		= (1<<0),	MEMen		= (1<<1),	MASen		= (1<<2),	MemWrInv	= (1<<4),	PErrEn		= (1<<6),	SErrEn		= (1<<8),};enum {	Ctrl		= 0x00000000,	/* Device Control */	Status		= 0x00000008,	/* Device Status */	Eecd		= 0x00000010,	/* EEPROM/Flash Control/Data */	Ctrlext		= 0x00000018,	/* Extended Device Control */	Mdic		= 0x00000020,	/* MDI Control */	Fcal		= 0x00000028,	/* Flow Control Address Low */	Fcah		= 0x0000002C,	/* Flow Control Address High */	Fct		= 0x00000030,	/* Flow Control Type */	Icr		= 0x000000C0,	/* Interrupt Cause Read */	Ics		= 0x000000C8,	/* Interrupt Cause Set */	Ims		= 0x000000D0,	/* Interrupt Mask Set/Read */	Imc		= 0x000000D8,	/* Interrupt mask Clear */	Rctl		= 0x00000100,	/* Receive Control */	Fcttv		= 0x00000170,	/* Flow Control Transmit Timer Value */	Txcw		= 0x00000178,	/* Transmit Configuration Word */	Tctl		= 0x00000400,	/* Transmit Control */	Tipg		= 0x00000410,	/* Transmit IPG */	Tbt		= 0x00000448,	/* Transmit Burst Timer */	Ait		= 0x00000458,	/* Adaptive IFS Throttle */	Fcrtl		= 0x00002160,	/* Flow Control RX Threshold Low */	Fcrth		= 0x00002168,	/* Flow Control Rx Threshold High */	Rdbal		= 0x00002800,	/* Rdesc Base Address Low */	Rdbah		= 0x00002804,	/* Rdesc Base Address High */	Rdlen		= 0x00002808,	/* Receive Descriptor Length */	Rdh		= 0x00002810,	/* Receive Descriptor Head */	Rdt		= 0x00002818,	/* Receive Descriptor Tail */	Rdtr		= 0x00002820,	/* Receive Descriptor Timer Ring */	Rxdctl		= 0x00002828,	/* Receive Descriptor Control */	Radv		= 0x0000282C,	/* Receive Interrupt Absolute Delay Timer */	Txdmac		= 0x00003000,	/* Transfer DMA Control */	Ett		= 0x00003008,	/* Early Transmit Control */	Tdbal		= 0x00003800,	/* Tdesc Base Address Low */	Tdbah		= 0x00003804,	/* Tdesc Base Address High */	Tdlen		= 0x00003808,	/* Transmit Descriptor Length */	Tdh		= 0x00003810,	/* Transmit Descriptor Head */	Tdt		= 0x00003818,	/* Transmit Descriptor Tail */	Tidv		= 0x00003820,	/* Transmit Interrupt Delay Value */	Txdctl		= 0x00003828,	/* Transmit Descriptor Control */	Tadv		= 0x0000382C,	/* Transmit Interrupt Absolute Delay Timer */ 	Statistics	= 0x00004000,	/* Start of Statistics Area */	Gorcl		= 0x88/4,	/* Good Octets Received Count */	Gotcl		= 0x90/4,	/* Good Octets Transmitted Count */	Torl		= 0xC0/4,	/* Total Octets Received */	Totl		= 0xC8/4,	/* Total Octets Transmitted */ 	Rxcsum		= 0x00005000,	/* Receive Checksum Control */	Mta		= 0x00005200,	/* Multicast Table Array */	Ral		= 0x00005400,	/* Receive Address Low */	Rah		= 0x00005404,	/* Receive Address High */	Manc		= 0x00005820,	/* Management Control */}; enum {					/* Ctrl */	Bem		= 0x00000002,	/* Big Endian Mode */	Prior		= 0x00000004,	/* Priority on the PCI bus */	Lrst		= 0x00000008,	/* Link Reset */	Asde		= 0x00000020,	/* Auto-Speed Detection Enable */	Slu		= 0x00000040,	/* Set Link Up */	Ilos		= 0x00000080,	/* Invert Loss of Signal (LOS) */	SspeedMASK	= 0x00000300,	/* Speed Selection */	SspeedSHIFT	= 8,	Sspeed10	= 0x00000000,	/* 10Mb/s */	Sspeed100	= 0x00000100,	/* 100Mb/s */	Sspeed1000	= 0x00000200,	/* 1000Mb/s */	Frcspd		= 0x00000800,	/* Force Speed */	Frcdplx		= 0x00001000,	/* Force Duplex */	SwdpinsloMASK	= 0x003C0000,	/* Software Defined Pins - lo nibble */	SwdpinsloSHIFT	= 18,	SwdpioloMASK	= 0x03C00000,	/* Software Defined Pins - I or O */	SwdpioloSHIFT	= 22,	Devrst		= 0x04000000,	/* Device Reset */	Rfce		= 0x08000000,	/* Receive Flow Control Enable */	Tfce		= 0x10000000,	/* Transmit Flow Control Enable */	Vme		= 0x40000000,	/* VLAN Mode Enable */}; /* * can't find Tckok nor Rbcok in any Intel docs, * but even 82543gc docs define Lanid. */enum {					/* Status */	Lu		= 0x00000002,	/* Link Up */	Lanid		= 0x0000000C,	/* mask for Lan ID. (function id) *///	Tckok		= 0x00000004,	/* Transmit clock is running *///	Rbcok		= 0x00000008,	/* Receive clock is running */	Txoff		= 0x00000010,	/* Transmission Paused */	Tbimode		= 0x00000020,	/* TBI Mode Indication */	SpeedMASK	= 0x000000C0,	Speed10		= 0x00000000,	/* 10Mb/s */	Speed100	= 0x00000040,	/* 100Mb/s */	Speed1000	= 0x00000080,	/* 1000Mb/s */	Mtxckok		= 0x00000400,	/* MTX clock is running */	Pci66		= 0x00000800,	/* PCI Bus speed indication */	Bus64		= 0x00001000,	/* PCI Bus width indication */}; enum {					/* Ctrl and Status */	Fd		= 0x00000001,	/* Full-Duplex */	AsdvMASK	= 0x00000300,	Asdv10		= 0x00000000,	/* 10Mb/s */	Asdv100		= 0x00000100,	/* 100Mb/s */	Asdv1000	= 0x00000200,	/* 1000Mb/s */}; enum {					/* Eecd */	Sk		= 0x00000001,	/* Clock input to the EEPROM */	Cs		= 0x00000002,	/* Chip Select */	Di		= 0x00000004,	/* Data Input to the EEPROM */	Do		= 0x00000008,	/* Data Output from the EEPROM */	Areq		= 0x00000040,	/* EEPROM Access Request */	Agnt		= 0x00000080,	/* EEPROM Access Grant */	Eepresent	= 0x00000100,	/* EEPROM Present */	Eesz256		= 0x00000200,	/* EEPROM is 256 words not 64 */	Eeszaddr	= 0x00000400,	/* EEPROM size for 8254[17] */	Spi		= 0x00002000,	/* EEPROM is SPI not Microwire */}; enum {					/* Ctrlext */	Gpien		= 0x0000000F,	/* General Purpose Interrupt Enables */	SwdpinshiMASK	= 0x000000F0,	/* Software Defined Pins - hi nibble */	SwdpinshiSHIFT	= 4,	SwdpiohiMASK	= 0x00000F00,	/* Software Defined Pins - I or O */	SwdpiohiSHIFT	= 8,	Asdchk		= 0x00001000,	/* ASD Check */	Eerst		= 0x00002000,	/* EEPROM Reset */	Ips		= 0x00004000,	/* Invert Power State */	Spdbyps		= 0x00008000,	/* Speed Select Bypass */}; enum {					/* EEPROM content offsets */	Ea		= 0x00,		/* Ethernet Address */	Cf		= 0x03,		/* Compatibility Field */	Pba		= 0x08,		/* Printed Board Assembly number */	Icw1		= 0x0A,		/* Initialization Control Word 1 */	Sid		= 0x0B,		/* Subsystem ID */	Svid		= 0x0C,		/* Subsystem Vendor ID */	Did		= 0x0D,		/* Device ID */	Vid		= 0x0E,		/* Vendor ID */	Icw2		= 0x0F,		/* Initialization Control Word 2 */}; enum {					/* Mdic */	MDIdMASK	= 0x0000FFFF,	/* Data */	MDIdSHIFT	= 0,	MDIrMASK	= 0x001F0000,	/* PHY Register Address */	MDIrSHIFT	= 16,	MDIpMASK	= 0x03E00000,	/* PHY Address */	MDIpSHIFT	= 21,	MDIwop		= 0x04000000,	/* Write Operation */	MDIrop		= 0x08000000,	/* Read Operation */	MDIready	= 0x10000000,	/* End of Transaction */	MDIie		= 0x20000000,	/* Interrupt Enable */	MDIe		= 0x40000000,	/* Error */}; enum {					/* Icr, Ics, Ims, Imc */	Txdw		= 0x00000001,	/* Transmit Descriptor Written Back */	Txqe		= 0x00000002,	/* Transmit Queue Empty */	Lsc		= 0x00000004,	/* Link Status Change */	Rxseq		= 0x00000008,	/* Receive Sequence Error */	Rxdmt0		= 0x00000010,	/* Rdesc Minimum Threshold Reached */	Rxo		= 0x00000040,	/* Receiver Overrun */	Rxt0		= 0x00000080,	/* Receiver Timer Interrupt */	Mdac		= 0x00000200,	/* MDIO Access Completed */	Rxcfg		= 0x00000400,	/* Receiving /C/ ordered sets */	Gpi0		= 0x00000800,	/* General Purpose Interrupts */	Gpi1		= 0x00001000,	Gpi2		= 0x00002000,	Gpi3		= 0x00004000,}; /* * The Mdic register isn't implemented on the 82543GC, * the software defined pins are used instead. * These definitions work for the Intel PRO/1000 T Server Adapter. * The direction pin bits are read from the EEPROM. */enum {	Mdd		= ((1<<2)<<SwdpinsloSHIFT),	/* data */	Mddo		= ((1<<2)<<SwdpioloSHIFT),	/* pin direction */	Mdc		= ((1<<3)<<SwdpinsloSHIFT),	/* clock */	Mdco		= ((1<<3)<<SwdpioloSHIFT),	/* pin direction */	Mdr		= ((1<<0)<<SwdpinshiSHIFT),	/* reset */	Mdro		= ((1<<0)<<SwdpiohiSHIFT),	/* pin direction */}; enum {					/* Txcw */	TxcwFd		= 0x00000020,	/* Full Duplex */	TxcwHd		= 0x00000040,	/* Half Duplex */	TxcwPauseMASK	= 0x00000180,	/* Pause */	TxcwPauseSHIFT	= 7,	TxcwPs		= (1<<TxcwPauseSHIFT),	/* Pause Supported */	TxcwAs		= (2<<TxcwPauseSHIFT),	/* Asymmetric FC desired */	TxcwRfiMASK	= 0x00003000,	/* Remote Fault Indication */	TxcwRfiSHIFT	= 12,	TxcwNpr		= 0x00008000,	/* Next Page Request */	TxcwConfig	= 0x40000000,	/* Transmit COnfig Control */	TxcwAne		= 0x80000000,	/* Auto-Negotiation Enable */}; enum {					/* Rctl */	Rrst		= 0x00000001,	/* Receiver Software Reset */	Ren		= 0x00000002,	/* Receiver Enable */	Sbp		= 0x00000004,	/* Store Bad Packets */	Upe		= 0x00000008,	/* Unicast Promiscuous Enable */	Mpe		= 0x00000010,	/* Multicast Promiscuous Enable */	Lpe		= 0x00000020,	/* Long Packet Reception Enable */	LbmMASK		= 0x000000C0,	/* Loopback Mode */	LbmOFF		= 0x00000000,	/* No Loopback */	LbmTBI		= 0x00000040,	/* TBI Loopback */	LbmMII		= 0x00000080,	/* GMII/MII Loopback */	LbmXCVR		= 0x000000C0,	/* Transceiver Loopback */	RdtmsMASK	= 0x00000300,	/* Rdesc Minimum Threshold Size */	RdtmsHALF	= 0x00000000,	/* Threshold is 1/2 Rdlen */	RdtmsQUARTER	= 0x00000100,	/* Threshold is 1/4 Rdlen */	RdtmsEIGHTH	= 0x00000200,	/* Threshold is 1/8 Rdlen */	MoMASK		= 0x00003000,	/* Multicast Offset */	Bam		= 0x00008000,	/* Broadcast Accept Mode */	BsizeMASK	= 0x00030000,	/* Receive Buffer Size */	Bsize2048	= 0x00000000,	Bsize1024	= 0x00010000,	Bsize512	= 0x00020000,	Bsize256	= 0x00030000,	Vfe		= 0x00040000,	/* VLAN Filter Enable */	Cfien		= 0x00080000,	/* Canonical Form Indicator Enable */	Cfi		= 0x00100000,	/* Canonical Form Indicator value */	Dpf		= 0x00400000,	/* Discard Pause Frames */	Pmcf		= 0x00800000,	/* Pass MAC Control Frames */	Bsex		= 0x02000000,	/* Buffer Size Extension */	Secrc		= 0x04000000,	/* Strip CRC from incoming packet */}; enum {					/* Tctl */	Trst		= 0x00000001,	/* Transmitter Software Reset */	Ten		= 0x00000002,	/* Transmit Enable */	Psp		= 0x00000008,	/* Pad Short Packets */	CtMASK		= 0x00000FF0,	/* Collision Threshold */	CtSHIFT		= 4,	ColdMASK	= 0x003FF000,	/* Collision Distance */	ColdSHIFT	= 12,	Swxoff		= 0x00400000,	/* Sofware XOFF Transmission */	Pbe		= 0x00800000,	/* Packet Burst Enable */	Rtlc		= 0x01000000,	/* Re-transmit on Late Collision */	Nrtu		= 0x02000000,	/* No Re-transmit on Underrrun */}; enum {					/* [RT]xdctl */	PthreshMASK	= 0x0000003F,	/* Prefetch Threshold */	PthreshSHIFT	= 0,	HthreshMASK	= 0x00003F00,	/* Host Threshold */	HthreshSHIFT	= 8,	WthreshMASK	= 0x003F0000,	/* Writebacj Threshold */	WthreshSHIFT	= 16,	Gran		= 0x01000000,	/* Granularity */}; enum {					/* Rxcsum */	PcssMASK	= 0x000000FF,	/* Packet Checksum Start */	PcssSHIFT	= 0,	Ipofl		= 0x00000100,	/* IP Checksum Off-load Enable */	Tuofl		= 0x00000200,	/* TCP/UDP Checksum Off-load Enable */}; enum {					/* Manc */	Arpen		= 0x00002000,	/* Enable ARP Request Filtering */}; typedef struct Rdesc {			/* Receive Descriptor */	uint	addr[2];	ushort	length;	ushort	checksum;	uchar	status;	uchar	errors;	ushort	special;} Rdesc; enum {					/* Rdesc status */	Rdd		= 0x01,		/* Descriptor Done */	Reop		= 0x02,		/* End of Packet */	Ixsm		= 0x04,		/* Ignore Checksum Indication */	Vp		= 0x08,		/* Packet is 802.1Q (matched VET) */	Tcpcs		= 0x20,		/* TCP Checksum Calculated on Packet */	Ipcs		= 0x40,		/* IP Checksum Calculated on Packet */	Pif		= 0x80,		/* Passed in-exact filter */}; enum {					/* Rdesc errors */	Ce		= 0x01,		/* CRC Error or Alignment Error */	Se		= 0x02,		/* Symbol Error */	Seq		= 0x04,		/* Sequence Error */	Cxe		= 0x10,		/* Carrier Extension Error */	Tcpe		= 0x20,		/* TCP/UDP Checksum Error */	Ipe		= 0x40,		/* IP Checksum Error */	Rxe		= 0x80,		/* RX Data Error */}; typedef struct Tdesc {			/* Legacy+Normal Transmit Descriptor */	uint	addr[2];	uint	control;		/* varies with descriptor type */	uint	status;			/* varies with descriptor type */} Tdesc; enum {					/* Tdesc control */	LenMASK		= 0x000FFFFF,	/* Data/Packet Length Field */	LenSHIFT	= 0,	DtypeCD		= 0x00000000,	/* Data Type 'Context Descriptor' */	DtypeDD		= 0x00100000,	/* Data Type 'Data Descriptor' */	PtypeTCP	= 0x01000000,	/* TCP/UDP Packet Type (CD) */	Teop		= 0x01000000,	/* End of Packet (DD) */	PtypeIP		= 0x02000000,	/* IP Packet Type (CD) */	Ifcs		= 0x02000000,	/* Insert FCS (DD) */	Tse		= 0x04000000,	/* TCP Segmentation Enable */	Rs		= 0x08000000,	/* Report Status */	Rps		= 0x10000000,	/* Report Status Sent */	Dext		= 0x20000000,	/* Descriptor Extension */	Vle		= 0x40000000,	/* VLAN Packet Enable */	Ide		= 0x80000000,	/* Interrupt Delay Enable */}; enum {					/* Tdesc status */	Tdd		= 0x00000001,	/* Descriptor Done */	Ec		= 0x00000002,	/* Excess Collisions */	Lc		= 0x00000004,	/* Late Collision */	Tu		= 0x00000008,	/* Transmit Underrun */	CssMASK		= 0x0000FF00,	/* Checksum Start Field */	CssSHIFT	= 8,}; enum {	Nrdesc		= 32,		/* multiple of 8 */	Ntdesc		= 8,		/* multiple of 8 */}; typedef struct Ctlr Ctlr;typedef struct Ctlr {	int	port;	Pcidev*	pcidev;	Ctlr*	next;	int	active;	int	id;	int	cls;	ushort	eeprom[0x40]; 	int*	nic;	Lock	imlock;	int	im;			/* interrupt mask */ 	Mii*	mii; 	Lock	slock; 	uchar	ra[Eaddrlen];		/* receive address */ 	Rdesc*	rdba;			/* receive descriptor base address */	Block**	rb;			/* receive buffers */	int	rdh;			/* receive descriptor head */	int	rdt;			/* receive descriptor tail */ 	Tdesc*	tdba;			/* transmit descriptor base address */	Lock	tdlock;	Block**	tb;			/* transmit buffers */	int	tdh;			/* transmit descriptor head */	int	tdt;			/* transmit descriptor tail */	int	ett;			/* early transmit threshold */ 	int	txcw;	int	fcrtl;	int	fcrth; 	/* bootstrap goo */	Block*	bqhead;	/* transmission queue */	Block*	bqtail;} Ctlr; static Ctlr* ctlrhead;static Ctlr* ctlrtail; #define csr32r(c, r)	(*((c)->nic+((r)/4)))#define csr32w(c, r, v)	(*((c)->nic+((r)/4)) = (v)) static voidigbeim(Ctlr* ctlr, int im){	ilock(&ctlr->imlock);	ctlr->im |= im;	csr32w(ctlr, Ims, ctlr->im);	iunlock(&ctlr->imlock);} static voidigbeattach(Ether* edev){	int ctl;	Ctlr *ctlr; 	/*	 * To do here:	 *	one-time stuff;	 *	start off a kproc for link status change:	 *		adjust queue length depending on speed;	 *		flow control.	 *	more needed here...	 */	ctlr = edev->ctlr;	igbeim(ctlr, 0);	ctl = csr32r(ctlr, Rctl)|Ren;	csr32w(ctlr, Rctl, ctl);	ctl = csr32r(ctlr, Tctl)|Ten;	csr32w(ctlr, Tctl, ctl);} static voidtxstart(Ether *edev){	int tdh, tdt, len, olen;	Ctlr *ctlr = edev->ctlr;	Block *bp;	Tdesc *tdesc; 	/*	 * Try to fill the ring back up, moving buffers from the transmit q.	 */	tdh = PREV(ctlr->tdh, Ntdesc);	for(tdt = ctlr->tdt; tdt != tdh; tdt = NEXT(tdt, Ntdesc)){		/* pull off the head of the transmission queue */		if((bp = ctlr->bqhead) == nil)		/* was qget(edev->oq) */			break;		ctlr->bqhead = bp->next;		if (ctlr->bqtail == bp)			ctlr->bqtail = nil;

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