/* * marvell 88e8057 yukon2 boot driver * copyright © 2009-10 erik quanstrom */#include "u.h"#include "lib.h"#include "mem.h"#include "dat.h"#include "fns.h"#include "io.h"#include "etherif.h" #define Pciwaddrh(x) 0#define Pciwaddrl(x) PCIWADDR(x)#define is64() (sizeof(uintptr) == 8)#define dprint(...) if(debug) print(__VA_ARGS__); else {}#define sfence() coherence()#define debug _debug#define qinit _qinit#define Fprobe _Fprobe#define Nrb _Nrb enum { Nctlr = 2, Nrb = 1024, Rbalign = 64, Fprobe = 1<<0, Sringcnt = 2048, Tringcnt = 512,// Rringcnt = Nrbyuk, Rringcnt = 512, Rringl = Rringcnt - 8,}; enum { /* pci registers */ Pciphy = 0x40, Pciclk = 0x80, Pciasp = 0x84, Pcistate = 0x88, Pcicf0 = 0x90, Pcicf1 = 0x94, /* “csr” registers */ Ctst = 0x0004/2, /* control and status */ Pwrctl = 0x0007, /* power control */ Isr = 0x0008/4, /* interrupt src */ Ism = 0x000c/4, /* interrupt mask */ Hwe = 0x0010/4, /* hw error */ Hwem = 0x0014/4, /* hw error mask*/ Isrc2 = 0x001c/4, Eisr = 0x0024/4, Lisr = 0x0028/4, /* leave isr */ Macadr = 0x0100, /* mac address 2ports*3 */ Pmd = 0x0119, Maccfg = 0x011a, Chip = 0x011b, Ramcnt = 0x011c, /* # of 4k blocks */ Hres = 0x011e, Clkgate = 0x011d, Clkctl = 0x0120/4, Tstctl1 = 0x0158, Tstctl2 = 0x0159, Gpio = 0x015c/4, Rictl = 0x01a0, /* ri ram buffer ctl */ Rib = 0x0190, /* ri buffer0 */ /* other unoffset registers */ Asfcs = 0x0e68, /* asf command and status */ Asfhost = 0x0e6c/4, Statctl = 0x0e80/4, /* status */ Stattl = 0x0e84/2, /* tail (previous) status addr */ Stataddr = 0x0e88/4, /* status address low */ Statth = 0x0e98/2, Stathd = 0x0e9c/2, Statwm = 0x0eac, /* stat watermark */ Statiwm = 0x0ead, /* isr stat watermark */ Dpolltm = 0x0e08/4, /* descriptor pool timer */ /* timers */ Tgv = 0x0e14/4, /* gmac timer current value */ Tgc = 0x0e18, /* gmac timer ctl */ Tgt = 0x0e1a, /* gmac timer test */ Tsti = 0x0ec0/4, /* stat tx timer ini */ Tlti = 0x0eb0/4, /* level */ Titi = 0x0ed0/4, /* isr */ Tstc = 0x0ec8, /* stat tx timer ctl */ Tltc = 0x0eb8, /* level timer ctl */ Titc = 0x0ed8, /* isr timer ctl */ /* “gmac” registers */ Stat = 0x000/2, Ctl = 0x004/2, Txctl = 0x008/2, Rxctl = 0x00c/2, Txflow = 0x010/2, Txparm = 0x014/2, Serctl = 0x018/2, /* serial mode */ Mchash = 0x034/2, /* 4 registers; 4 bytes apart */ /* interrupt sources and masks */ Txirq = 0x044/2, Rxirq = 0x048/2, Trirq = 0x04c/2, /* tx/rx overflow irq source */ Txmask = 0x050/2, Rxmask = 0x054/2, Trmask = 0x058/2, Smictl = 0x080/2, /* serial mode control */ Smidata = 0x084/2, Phyaddr = 0x088/2, Ea0 = 0x01c/2, /* 3 16 bit gmac registers */ Ea1 = 0x028/2, Stats = 0x0100/4, /* mac registers */ Txactl = 0x210, /* transmit arbiter ctl */ Grxea = 0x0c40/4, /* rx fifo end address */ Gfrxctl = 0x0c48/4, /* gmac rxfifo ctl */ Grxfm = 0x0c4c/4, /* fifo flush mask */ Grxft = 0x0c50/4, /* fifo flush threshold */ Grxtt = 0x0c54/4, /* rx truncation threshold */ Gmfea = 0x0d40/4, /* end address */ Gmfae = 0x0d44/4, /* almost empty thresh */ Gmfctl = 0x0d48/4, /* tx gmac fifo ctl */ Rxphi = 0x0c58, /* pause high watermark */ Rxplo = 0x0c5c, /* pause low watermark */ Rxwp = 0x0c60/4, Rxwlev = 0x0c68/4, Rxrp = 0x0c70/4, Rxrlev = 0x0c78/4, Mac = 0x0f00/4, /* global mac control */ Phy = 0x0f04/4, /* phy control register */ Irq = 0x0f08, /* irq source */ Irqm = 0x0f0c, /* irq mask */ Linkctl = 0x0f10, /* queue registers; all offsets from Qbase*/ Qbase = 0x0400, Qportsz = 0x0080, /* BOTCH; tx diff is 2x rx diff */ Qr = 0x000, Qtxs = 0x200, Qtx = 0x280, /* queue offsets */ Qd = 0x00, Qvlan = 0x20, Qdone = 0x24, Qaddrl = 0x28, Qaddrh = 0x2c, Qbc = 0x30, Qcsr = 0x34, /* 32bit */ Qtest = 0x38, Qwm = 0x40, /* buffer registers; all offsets from Rbase */ Rbase = 0x0800, Rstart = 0x00, Rend = 0x04, Rwp = 0x08, Rrp = 0x0c, Rpon = 0x10, /* pause frames on */ Rpoff = 0x14, /* pause frames off */ Rhon = 0x18, /* high-priority frames on */ Rhoff = 0x1c, /* high-priority frames off */ Rctl = 0x28, /* prefetch */ Pbase = 0x450, Pctl = 0x00, Plidx = 0x04, /* last addr; 16 bit */ Paddrl = 0x08, Paddrh = 0x0c, Pgetidx = 0x10, /* 16 bit */ Pputidx = 0x14, /* 16 bit */ Pfifow = 0x20, /* 8 bit */ Pfifor = 0x24, /* 8 bit */ Pfifowm = 0x20, /* 8 bit */ /* indirect phy registers */ Phyctl = 0x000, Phystat = 0x001, Phyid0 = 0x002, Phyid1 = 0x003, Phyana = 0x004, /* auto neg advertisement */ Phylpa = 0x005, /* link partner ability */ Phyanee = 0x006, /* auto neg adv expansion */ Phynp = 0x007, /* next page */ Phylnp = 0x008, /* link partner next page */ Gbectl = 0x009, Gbestat = 0x00a, Phyphy = 0x010, /* phy specific ctl */ Phylstat = 0x011, Phyintm = 0x012, /* phy interrupt mask */ Phyint = 0x013, Phyextctl = 0x014, Phyrxe = 0x015, /* rx error counter */ Phypage = 0x016, /* external address */ Phypadr = 0x01d, /* phy page address */}; enum { /* Pciasp */ Aspforce = 1<<15, Aspglinkdn = 1<<14, /* gphy link down */ Aspfempty = 1<<13, Aspclkrun = 1<<12, Aspmsk = Aspforce | Aspglinkdn | Aspfempty | Aspclkrun, /* Pcistate */ Vmain = 3<<27, /* Stat */ Sfast = 1<<15, /* 100mbit */ Duplex = 1<<14, Txnofc = 1<<13, /* tx flow control disabled */ Link = 1<<12, /* link up */ Pausest = 1<<11, /* pause state */ Txactive = 1<<10, Excesscol = 1<<9, Latecol = 1<<8, Physc = 1<<5, /* phy status change */ Sgbe = 1<<4, /* gbe speed */ Rxnofc = 1<<2, /* rx flow control disabled */ Promisc = 1<<1, /* promiscuous mode enabled */ /* Ctl */ Promiscen = 1<<14, Txfcdis = 1<<13, Txen = 1<<12, Rxen = 1<<11, Bursten = 1<<10, Loopen = 1<<9, Gbeen = 1<<7, Fpass = 1<<6, /* "force link pass" ? */ Duplexen = 1<<5, Rxfcdis = 1<<4, Fasten = 1<<3, /* enable 100mbit */ Adudis = 1<<2, /* disable auto upd duplex */ Afcdis = 1<<1, /* disable auto upd flow ctl */ Aspddis = 1<<0, /* disable auto upd speed */ /* Rxctl */ Ufilter = 1<<15, /* unicast filter */ Mfilter = 1<<14, /* multicast filter */ Rmcrc = 1<<13, /* remove frame crc */ /* Serctl */ Vlanen = 1<<9, Jumboen = 1<<8, /* Txactl */ Txaclr = 1<<1, Txarst = 1<<0, /* Asfcs: yukex only */ Asfbrrst = 1<<9, /* bridge reset */ Asfcpurst = 1<<8, /* cpu reset */ Asfucrst = 3<<0, /* µctlr reset */ /* Asfcs */ Asfhvos = 1<<4, /* os present */ Asfrst = 1<<3, Asfrun = 1<<2, Asfcirq = 1<<1, Afsirq = 1<<0, /* Statctl */ Statirqclr = 1<<4, Staton = 1<<3, Statoff = 1<<2, Statclr = 1<<1, Statrst = 1<<0, /* Mac */ Nomacsec = 1<<13 | 1<<11, Nortx = 1<<9, Macpause = 1<<3, Macpauseoff = 1<<2, Macrstclr = 1<<1, Macrst = 1<<0, /* Phy */ Gphyrstclr = 1<<1, Gphyrst = 1<<0, /* Irqm */ Txovfl = 1<<5, /* tx counter overflow */ Rxovfl = 1<<4, /* rx counter overflow */ Txurun = 1<<3, /* transmit fifo underrun */ Txdone = 1<<2, /* frame tx done */ Rxorun = 1<<1, /* rx fifo overrun */ Rxdone = 1<<0, /* frame rx done */ /* Linkctl */ Linkclr = 1<<1, Linkrst = 1<<0, /* Smictl */ Smiread = 1<<5, Smiwrite = 0<<5, Smirdone = 1<<4, Smibusy = 1<<3, /* Phyaddr */ Mibclear = 1<<5, /* Ctst */ Asfdis = 1<<12, /* asf disable */ Clken = 1<<11, /* enable clock */ Swirq = 1<<7, Swirqclr = 1<<6, Mstopped = 1<<5, /* master is stopped */ Mstop = 1<<4, /* stop master */ Mstrclr = 1<<3, /* master reset clear */ Mstrrset = 1<<2, /* master reset */ Swclr = 1<<1, Swrst = 1<<0, /* Pwrctl */ Vauxen = 1<<7, Vauxdis = 1<<6, Vccen = 1<<5, Vccdis = 1<<4, Vauxon = 1<<3, Vauxoff = 1<<2, Vccon = 1<<1, Vccoff = 1<<0, /* timers */ Tstart = 1<<2, Tstop = 1<<1, Tclrirq = 1<<0, /* Dpolltm */ Pollstart = 1<<1, Pollstop = 1<<0, /* csr interrupts: Isrc2, Eisr, etc. */ Ihwerr = 1<<31, Ibmu = 1<<30, /* sring irq */ Isoftware = 1<<25, Iphy = 1<<4, Imac = 1<<3, Irx = 1<<2, Itxs = 1<<1, /* descriptor error */ Itx = 1<<0, /* descriptor error */ Iport = 0x1f, Iphy2base = 8, Ierror = (Imac | Itx | Irx)*(1 | 1<<Iphy2base), /* hwe interrupts: Hwe Hwem */ Htsof = 1<<29, /* timer stamp overflow */ Hsensor = 1<<28, Hmerr = 1<<27, /* master error */ Hstatus = 1<<26, /* status exception */ Hpcie = 1<<25, /* pcie error */ Hpcie2 = 1<<24, /* " */ Hrparity = 1<<5, /* ram read parity error */ Hwparity = 1<<4, /* ram write parity error */ Hmfault = 1<<3, /* mac fault */ Hrxparity = 1<<2, /* rx parity */ Htcptxs = 1<<1, /* tcp length mismatch */ Htcptxa = 1<<0, /* tcp length mismatch */ H1base = 1<<0, H2base = 1<<8, Hmask = 0x3f, Hdflt = Htsof | Hmerr | Hstatus | Hmask*(H1base | H2base), /* Clkctl */ Clkdiven = 1<<1, Clkdivdis = 1<<0, /* Clkgate */ Link2inactive = 1<<7, /* Phyctl */ Phyrst = 1<<15, Phy100 = 1<<14, /* manual enable 100mbit */ Aneen = 1<<12, /* auto negotiation enable */ Phyoff = 1<<11, /* turn phy off */ Anerst = 1<<9, /* auto neg reset */ Phydpx = 1<<8, Phy1000 = 1<<5, /* manual enable gbe */ /* Phyana */ Annp = 1<<15, /* request next page */ Anack = 1<<14, /* ack rx (read only) */ Anrf = 1<<13, /* remote fault */ Anpa = 1<<11, /* try asymmetric pause */ Anp = 1<<10, /* try pause */ An100f = 1<<8, An100h = 1<<7, An10f = 1<<6, An10h = 1<<5, Anonly = 1<<0, Anall = An100f | An100h | An10f | An10h | Anonly, /* Gbectl */ Gbef = 1<<9, /* auto neg gbe full */ Gbeh = 1<<8, /* auto neg gbe half */ Gbexf = 1<<6, /* auto neg gbe full fiber */ Gbexh = 1<<5, /* auto neg gbe full fiber */ /* Phyphy */ Pptf = 3<<14, /* tx fifo depth */ Pprf = 3<<12, /* rx fifo depth */ Pped = 3<<8, /* energy detect */ Ppmdix = 3<<5, /* mdix conf */ Ppmdixa = 3<<5, /* automdix */ Ppengy = 1<<14, /* fe+ enable energy detect */ Ppscrdis = 1<<9, /* fe+ scrambler disable */ Ppnpe = 1<<12, /* fe+ enable next page */ /* Phylstat */ Physpd = 3<<14, Phydupx = 1<<13, Phypr = 1<<12, /* page rx */ Phydone = 1<<11, /* speed and duplex neg. done */ Plink = 1<<10, Pwirelen = 7<<7, Pmdi = 1<<6, Pdwnsh = 1<<5, /* downshift */ Penergy = 1<<4, /* energy detect */ Ptxpause = 1<<3, /* tx pause enabled */ Prxpause = 1<<2, /* rx pause enabled */ Ppol = 1<<2, /* polarity */ Pjarjar = 1<<1, /* mesa no understasa */ /* Phyintm */ Anerr = 1<<15, /* an error */ Lsp = 1<<14, /* link speed change */ Andc = 1<<13, /* an duplex change */ Anok = 1<<11, Lsc = 1<<10, /* link status change */ Symerr = 1<<9, /* symbol error */ Fcarr = 1<<8, /* false carrier */ Fifoerr = 1<<7, Mdich = 1<<6, Downsh = 1<<5, Engych = 1<<4, /* energy change */ Dtech = 1<<2, /* dte power det status */ Polch = 1<<1, /* polarity change */ Jabber = 1<<0, /* Phyextctl */ Dnmstr = 1<<9, /* master downshift; 0: 1x; 1: 2x; 2: 3x */ Dnslv = 1<<8, /* Tgc */ Tgstart = 1<<2, Tgstop = 1<<1, Tgclr = 1<<0, /* clear irq */ /* Tstctl1 */ Tstwen = 1<<1, /* enable config reg r/w */ Tstwdis = 1<<0, /* disable config reg r/w */ /* Gpio */ Norace = 1<<13, /* Rictl */ Rirpclr = 1<<9, Riwpclr = 1<<8, Riclr = 1<<1, Rirst = 1<<0, /* Rbase opcodes */ Rsfon = 1<<5, /* enable store/fwd */ Rsfoff = 1<<4, Renable = 1<<3, Rdisable = 1<<2, Rrstclr = 1<<1, Rrst = 1<<0, /* Qbase opcodes */ Qidle = 1<<31, Qtcprx = 1<<30, Qiprx = 1<<29, Qrssen = 1<<15,Lines 1–500 of 1988. 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/* * marvell 88e8057 yukon2 boot driver * copyright © 2009-10 erik quanstrom */ #include "u.h" #include "lib.h" #include "mem.h" #include "dat.h" #include "fns.h" #include "io.h" #include "etherif.h" #define Pciwaddrh(x) 0 #define Pciwaddrl(x) PCIWADDR(x) #define is64() (sizeof(uintptr) == 8) #define dprint(...) if(debug) print(__VA_ARGS__); else {} #define sfence() coherence() #define debug _debug #define qinit _qinit #define Fprobe _Fprobe #define Nrb _Nrb enum { Nctlr = 2, Nrb = 1024, Rbalign = 64, Fprobe = 1<<0, Sringcnt = 2048, Tringcnt = 512, // Rringcnt = Nrbyuk, Rringcnt = 512, Rringl = Rringcnt - 8, }; enum { /* pci registers */ Pciphy = 0x40, Pciclk = 0x80, Pciasp = 0x84, Pcistate = 0x88, Pcicf0 = 0x90, Pcicf1 = 0x94, /* “csr” registers */ Ctst = 0x0004/2, /* control and status */ Pwrctl = 0x0007, /* power control */ Isr = 0x0008/4, /* interrupt src */ Ism = 0x000c/4, /* interrupt mask */ Hwe = 0x0010/4, /* hw error */ Hwem = 0x0014/4, /* hw error mask*/ Isrc2 = 0x001c/4, Eisr = 0x0024/4, Lisr = 0x0028/4, /* leave isr */ Macadr = 0x0100, /* mac address 2ports*3 */ Pmd = 0x0119, Maccfg = 0x011a, Chip = 0x011b, Ramcnt = 0x011c, /* # of 4k blocks */ Hres = 0x011e, Clkgate = 0x011d, Clkctl = 0x0120/4, Tstctl1 = 0x0158, Tstctl2 = 0x0159, Gpio = 0x015c/4, Rictl = 0x01a0, /* ri ram buffer ctl */ Rib = 0x0190, /* ri buffer0 */ /* other unoffset registers */ Asfcs = 0x0e68, /* asf command and status */ Asfhost = 0x0e6c/4, Statctl = 0x0e80/4, /* status */ Stattl = 0x0e84/2, /* tail (previous) status addr */ Stataddr = 0x0e88/4, /* status address low */ Statth = 0x0e98/2, Stathd = 0x0e9c/2, Statwm = 0x0eac, /* stat watermark */ Statiwm = 0x0ead, /* isr stat watermark */ Dpolltm = 0x0e08/4, /* descriptor pool timer */ /* timers */ Tgv = 0x0e14/4, /* gmac timer current value */ Tgc = 0x0e18, /* gmac timer ctl */ Tgt = 0x0e1a, /* gmac timer test */ Tsti = 0x0ec0/4, /* stat tx timer ini */ Tlti = 0x0eb0/4, /* level */ Titi = 0x0ed0/4, /* isr */ Tstc = 0x0ec8, /* stat tx timer ctl */ Tltc = 0x0eb8, /* level timer ctl */ Titc = 0x0ed8, /* isr timer ctl */ /* “gmac” registers */ Stat = 0x000/2, Ctl = 0x004/2, Txctl = 0x008/2, Rxctl = 0x00c/2, Txflow = 0x010/2, Txparm = 0x014/2, Serctl = 0x018/2, /* serial mode */ Mchash = 0x034/2, /* 4 registers; 4 bytes apart */ /* interrupt sources and masks */ Txirq = 0x044/2, Rxirq = 0x048/2, Trirq = 0x04c/2, /* tx/rx overflow irq source */ Txmask = 0x050/2, Rxmask = 0x054/2, Trmask = 0x058/2, Smictl = 0x080/2, /* serial mode control */ Smidata = 0x084/2, Phyaddr = 0x088/2, Ea0 = 0x01c/2, /* 3 16 bit gmac registers */ Ea1 = 0x028/2, Stats = 0x0100/4, /* mac registers */ Txactl = 0x210, /* transmit arbiter ctl */ Grxea = 0x0c40/4, /* rx fifo end address */ Gfrxctl = 0x0c48/4, /* gmac rxfifo ctl */ Grxfm = 0x0c4c/4, /* fifo flush mask */ Grxft = 0x0c50/4, /* fifo flush threshold */ Grxtt = 0x0c54/4, /* rx truncation threshold */ Gmfea = 0x0d40/4, /* end address */ Gmfae = 0x0d44/4, /* almost empty thresh */ Gmfctl = 0x0d48/4, /* tx gmac fifo ctl */ Rxphi = 0x0c58, /* pause high watermark */ Rxplo = 0x0c5c, /* pause low watermark */ Rxwp = 0x0c60/4, Rxwlev = 0x0c68/4, Rxrp = 0x0c70/4, Rxrlev = 0x0c78/4, Mac = 0x0f00/4, /* global mac control */ Phy = 0x0f04/4, /* phy control register */ Irq = 0x0f08, /* irq source */ Irqm = 0x0f0c, /* irq mask */ Linkctl = 0x0f10, /* queue registers; all offsets from Qbase*/ Qbase = 0x0400, Qportsz = 0x0080, /* BOTCH; tx diff is 2x rx diff */ Qr = 0x000, Qtxs = 0x200, Qtx = 0x280, /* queue offsets */ Qd = 0x00, Qvlan = 0x20, Qdone = 0x24, Qaddrl = 0x28, Qaddrh = 0x2c, Qbc = 0x30, Qcsr = 0x34, /* 32bit */ Qtest = 0x38, Qwm = 0x40, /* buffer registers; all offsets from Rbase */ Rbase = 0x0800, Rstart = 0x00, Rend = 0x04, Rwp = 0x08, Rrp = 0x0c, Rpon = 0x10, /* pause frames on */ Rpoff = 0x14, /* pause frames off */ Rhon = 0x18, /* high-priority frames on */ Rhoff = 0x1c, /* high-priority frames off */ Rctl = 0x28, /* prefetch */ Pbase = 0x450, Pctl = 0x00, Plidx = 0x04, /* last addr; 16 bit */ Paddrl = 0x08, Paddrh = 0x0c, Pgetidx = 0x10, /* 16 bit */ Pputidx = 0x14, /* 16 bit */ Pfifow = 0x20, /* 8 bit */ Pfifor = 0x24, /* 8 bit */ Pfifowm = 0x20, /* 8 bit */ /* indirect phy registers */ Phyctl = 0x000, Phystat = 0x001, Phyid0 = 0x002, Phyid1 = 0x003, Phyana = 0x004, /* auto neg advertisement */ Phylpa = 0x005, /* link partner ability */ Phyanee = 0x006, /* auto neg adv expansion */ Phynp = 0x007, /* next page */ Phylnp = 0x008, /* link partner next page */ Gbectl = 0x009, Gbestat = 0x00a, Phyphy = 0x010, /* phy specific ctl */ Phylstat = 0x011, Phyintm = 0x012, /* phy interrupt mask */ Phyint = 0x013, Phyextctl = 0x014, Phyrxe = 0x015, /* rx error counter */ Phypage = 0x016, /* external address */ Phypadr = 0x01d, /* phy page address */ }; enum { /* Pciasp */ Aspforce = 1<<15, Aspglinkdn = 1<<14, /* gphy link down */ Aspfempty = 1<<13, Aspclkrun = 1<<12, Aspmsk = Aspforce | Aspglinkdn | Aspfempty | Aspclkrun, /* Pcistate */ Vmain = 3<<27, /* Stat */ Sfast = 1<<15, /* 100mbit */ Duplex = 1<<14, Txnofc = 1<<13, /* tx flow control disabled */ Link = 1<<12, /* link up */ Pausest = 1<<11, /* pause state */ Txactive = 1<<10, Excesscol = 1<<9, Latecol = 1<<8, Physc = 1<<5, /* phy status change */ Sgbe = 1<<4, /* gbe speed */ Rxnofc = 1<<2, /* rx flow control disabled */ Promisc = 1<<1, /* promiscuous mode enabled */ /* Ctl */ Promiscen = 1<<14, Txfcdis = 1<<13, Txen = 1<<12, Rxen = 1<<11, Bursten = 1<<10, Loopen = 1<<9, Gbeen = 1<<7, Fpass = 1<<6, /* "force link pass" ? */ Duplexen = 1<<5, Rxfcdis = 1<<4, Fasten = 1<<3, /* enable 100mbit */ Adudis = 1<<2, /* disable auto upd duplex */ Afcdis = 1<<1, /* disable auto upd flow ctl */ Aspddis = 1<<0, /* disable auto upd speed */ /* Rxctl */ Ufilter = 1<<15, /* unicast filter */ Mfilter = 1<<14, /* multicast filter */ Rmcrc = 1<<13, /* remove frame crc */ /* Serctl */ Vlanen = 1<<9, Jumboen = 1<<8, /* Txactl */ Txaclr = 1<<1, Txarst = 1<<0, /* Asfcs: yukex only */ Asfbrrst = 1<<9, /* bridge reset */ Asfcpurst = 1<<8, /* cpu reset */ Asfucrst = 3<<0, /* µctlr reset */ /* Asfcs */ Asfhvos = 1<<4, /* os present */ Asfrst = 1<<3, Asfrun = 1<<2, Asfcirq = 1<<1, Afsirq = 1<<0, /* Statctl */ Statirqclr = 1<<4, Staton = 1<<3, Statoff = 1<<2, Statclr = 1<<1, Statrst = 1<<0, /* Mac */ Nomacsec = 1<<13 | 1<<11, Nortx = 1<<9, Macpause = 1<<3, Macpauseoff = 1<<2, Macrstclr = 1<<1, Macrst = 1<<0, /* Phy */ Gphyrstclr = 1<<1, Gphyrst = 1<<0, /* Irqm */ Txovfl = 1<<5, /* tx counter overflow */ Rxovfl = 1<<4, /* rx counter overflow */ Txurun = 1<<3, /* transmit fifo underrun */ Txdone = 1<<2, /* frame tx done */ Rxorun = 1<<1, /* rx fifo overrun */ Rxdone = 1<<0, /* frame rx done */ /* Linkctl */ Linkclr = 1<<1, Linkrst = 1<<0, /* Smictl */ Smiread = 1<<5, Smiwrite = 0<<5, Smirdone = 1<<4, Smibusy = 1<<3, /* Phyaddr */ Mibclear = 1<<5, /* Ctst */ Asfdis = 1<<12, /* asf disable */ Clken = 1<<11, /* enable clock */ Swirq = 1<<7, Swirqclr = 1<<6, Mstopped = 1<<5, /* master is stopped */ Mstop = 1<<4, /* stop master */ Mstrclr = 1<<3, /* master reset clear */ Mstrrset = 1<<2, /* master reset */ Swclr = 1<<1, Swrst = 1<<0, /* Pwrctl */ Vauxen = 1<<7, Vauxdis = 1<<6, Vccen = 1<<5, Vccdis = 1<<4, Vauxon = 1<<3, Vauxoff = 1<<2, Vccon = 1<<1, Vccoff = 1<<0, /* timers */ Tstart = 1<<2, Tstop = 1<<1, Tclrirq = 1<<0, /* Dpolltm */ Pollstart = 1<<1, Pollstop = 1<<0, /* csr interrupts: Isrc2, Eisr, etc. */ Ihwerr = 1<<31, Ibmu = 1<<30, /* sring irq */ Isoftware = 1<<25, Iphy = 1<<4, Imac = 1<<3, Irx = 1<<2, Itxs = 1<<1, /* descriptor error */ Itx = 1<<0, /* descriptor error */ Iport = 0x1f, Iphy2base = 8, Ierror = (Imac | Itx | Irx)*(1 | 1<<Iphy2base), /* hwe interrupts: Hwe Hwem */ Htsof = 1<<29, /* timer stamp overflow */ Hsensor = 1<<28, Hmerr = 1<<27, /* master error */ Hstatus = 1<<26, /* status exception */ Hpcie = 1<<25, /* pcie error */ Hpcie2 = 1<<24, /* " */ Hrparity = 1<<5, /* ram read parity error */ Hwparity = 1<<4, /* ram write parity error */ Hmfault = 1<<3, /* mac fault */ Hrxparity = 1<<2, /* rx parity */ Htcptxs = 1<<1, /* tcp length mismatch */ Htcptxa = 1<<0, /* tcp length mismatch */ H1base = 1<<0, H2base = 1<<8, Hmask = 0x3f, Hdflt = Htsof | Hmerr | Hstatus | Hmask*(H1base | H2base), /* Clkctl */ Clkdiven = 1<<1, Clkdivdis = 1<<0, /* Clkgate */ Link2inactive = 1<<7, /* Phyctl */ Phyrst = 1<<15, Phy100 = 1<<14, /* manual enable 100mbit */ Aneen = 1<<12, /* auto negotiation enable */ Phyoff = 1<<11, /* turn phy off */ Anerst = 1<<9, /* auto neg reset */ Phydpx = 1<<8, Phy1000 = 1<<5, /* manual enable gbe */ /* Phyana */ Annp = 1<<15, /* request next page */ Anack = 1<<14, /* ack rx (read only) */ Anrf = 1<<13, /* remote fault */ Anpa = 1<<11, /* try asymmetric pause */ Anp = 1<<10, /* try pause */ An100f = 1<<8, An100h = 1<<7, An10f = 1<<6, An10h = 1<<5, Anonly = 1<<0, Anall = An100f | An100h | An10f | An10h | Anonly, /* Gbectl */ Gbef = 1<<9, /* auto neg gbe full */ Gbeh = 1<<8, /* auto neg gbe half */ Gbexf = 1<<6, /* auto neg gbe full fiber */ Gbexh = 1<<5, /* auto neg gbe full fiber */ /* Phyphy */ Pptf = 3<<14, /* tx fifo depth */ Pprf = 3<<12, /* rx fifo depth */ Pped = 3<<8, /* energy detect */ Ppmdix = 3<<5, /* mdix conf */ Ppmdixa = 3<<5, /* automdix */ Ppengy = 1<<14, /* fe+ enable energy detect */ Ppscrdis = 1<<9, /* fe+ scrambler disable */ Ppnpe = 1<<12, /* fe+ enable next page */ /* Phylstat */ Physpd = 3<<14, Phydupx = 1<<13, Phypr = 1<<12, /* page rx */ Phydone = 1<<11, /* speed and duplex neg. done */ Plink = 1<<10, Pwirelen = 7<<7, Pmdi = 1<<6, Pdwnsh = 1<<5, /* downshift */ Penergy = 1<<4, /* energy detect */ Ptxpause = 1<<3, /* tx pause enabled */ Prxpause = 1<<2, /* rx pause enabled */ Ppol = 1<<2, /* polarity */ Pjarjar = 1<<1, /* mesa no understasa */ /* Phyintm */ Anerr = 1<<15, /* an error */ Lsp = 1<<14, /* link speed change */ Andc = 1<<13, /* an duplex change */ Anok = 1<<11, Lsc = 1<<10, /* link status change */ Symerr = 1<<9, /* symbol error */ Fcarr = 1<<8, /* false carrier */ Fifoerr = 1<<7, Mdich = 1<<6, Downsh = 1<<5, Engych = 1<<4, /* energy change */ Dtech = 1<<2, /* dte power det status */ Polch = 1<<1, /* polarity change */ Jabber = 1<<0, /* Phyextctl */ Dnmstr = 1<<9, /* master downshift; 0: 1x; 1: 2x; 2: 3x */ Dnslv = 1<<8, /* Tgc */ Tgstart = 1<<2, Tgstop = 1<<1, Tgclr = 1<<0, /* clear irq */ /* Tstctl1 */ Tstwen = 1<<1, /* enable config reg r/w */ Tstwdis = 1<<0, /* disable config reg r/w */ /* Gpio */ Norace = 1<<13, /* Rictl */ Rirpclr = 1<<9, Riwpclr = 1<<8, Riclr = 1<<1, Rirst = 1<<0, /* Rbase opcodes */ Rsfon = 1<<5, /* enable store/fwd */ Rsfoff = 1<<4, Renable = 1<<3, Rdisable = 1<<2, Rrstclr = 1<<1, Rrst = 1<<0, /* Qbase opcodes */ Qidle = 1<<31, Qtcprx = 1<<30, Qiprx = 1<<29, Qrssen = 1<<15,