2012-12-17 Nick Clifton <nickc@redhat.com> * MAINTAINERS: Add copyright notice. * Makefile.am: Likewise. * configure.com: Likewise. * configure.in: Likewise. * makefile.vms: Likewise. * rl78-decode.c: Likewise. * rl78-decode.opc: Likewise. * rx-decode.c: Likewise. * rx-decode.opc: Likewise. * Makefile.in: Regenerate. 2012-12-13 Alan Modra <amodra@gmail.com> PR binutils/14950 * ppc-opc.c (insert_sci8, extract_sci8): Rewrite. (insert_sci8n, extract_sci8n): Likewise. 2012-11-30 Oleg Raikhman <oleg@adapteva.com> Joern Rennecke <joern.rennecke@embecosm.com> * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate. 2012-11-29 Roland McGrath <mcgrathr@google.com> * s390-mkopc.c (file_header): Add const. 2012-11-29 David Holsgrove <david.holsgrove@xilinx.com> * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to INST_TYPE_R1_R2_SPECIAL * microblaze-dis.c (print_insn_microblaze): Same. 2012-11-23 Alan Modra <amodra@gmail.com> * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits set from ppc_opts.sticky in it. Delete "retain_mask". (powerpc_init_dialect): Choose default dialect from info->mach before parsing -M options. Handle more bfd_mach_ppc variants. Update common default to power7. 2012-11-21 David Holsgrove <david.holsgrove@xilinx.com> * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES. * microblaze-opcm.h (microblaze_instr): Likewise 2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK 2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/14859 * i386-opc.tbl: Fix opcode for 64-bit jecxz. * i386-tbl.h: Regenerated. 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: Fix srstu and strag opcodes. 2012-11-14 David Holsgrove <david.holsgrove@xilinx.com> * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5, update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5, and increase MAX_OPCODES. (op_code_struct): add mbar and sleep * microblaze-opcm.h (microblaze_instr): add mbar Define IMM_MBAR and IMM5_MBAR_MASK * microblaze-dis.c: Add get_field_imm5_mbar (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn * microblaze-opcm.h (microblaze_instr): add clz 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur, lhur, lwr, sbr, shr, swr * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr, swr 2012-11-09 Nick Clifton <nickc@redhat.com> * configure.in: Add bfd_v850_rh850_arch. * configure: Regenerate. * disassemble.c (disassembler): Likewise. 2012-11-09 H.J. Lu <hongjiu.lu@intel.com> * aarch64-opc.h (gen_mask): Remove trailing redundant `;'. * ia64-gen.c (fetch_insn_class): Likewise. 2012-11-08 Alan Modra <amodra@gmail.com> * po/POTFILES.in: Regenerate. 2012-11-05 Alan Modra <amodra@gmail.com> * configure.in: Apply 2012-09-10 change to config.in here. 2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c: Accept empty lines in s390-opc.txt. * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2 and RRF_RMRR. * s390-opc.txt: Add new instructions. New instruction type for lptea. 2012-10-26 Christian Groessler <chris@groessler.org> * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb, trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove non-existing opcode trtrb. * z8k-opc.h: Regenerate. 2012-10-26 Alan Modra <amodra@gmail.com> * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset. 2012-10-24 Roland McGrath <mcgrathr@google.com> * i386-dis.c (ckprefix): When bailing out for fwait with prefixes, set rex_used to rex. 2012-10-22 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling. 2012-10-18 Tom Tromey <tromey@redhat.com> * tic54x-dis.c (print_instruction): Don't use K&R style. (print_parallel_instruction, sprint_dual_address) (sprint_indirect_address, sprint_direct_address, sprint_mmr) (sprint_cc2, sprint_condition): Likewise. 2012-10-18 Kai Tietz <ktietz@redhat.com> * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize value with a default. (do_special_encoding): Likewise. (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2 variables with default. * arc-dis.c (write_comments_): Don't use strncat due size of state->commentBuffer pointer isn't predictable. 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and rmr_el3; remove daifset and daifclr. 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Change to check the alignment of addr.offset.imm instead of that of shifter.amount for operand type AARCH64_OPND_ADDR_UIMM12. 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c: Use preferred form of vrint instruction variants for disassembly. 2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS. * i386-init.h: Regenerated. 2012-10-05 Peter Bergner <bergner@vnet.ibm.com> * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2; * ppc-opc.c (VBA): New define. (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot, mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics. 2012-10-04 Nick Clifton <nickc@redhat.com> * v850-dis.c (disassemble): Place square parentheses around second register operand of clr1, not1, set1 and tst1 instructions. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c: Support new option zEC12. * s390-opc.c: Add new instruction formats. * s390-opc.txt: Add new instructions for zEC12. 2012-09-27 Anthony Green <green@moxielogic.com> * moxie-dis.c (print_insn_moxie): Print 'bad' instructions. * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD. 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> * i386-gen.c (cpu_flag_init): Add missing Cpu flags in CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-init.h: Regenerated. 2012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS, CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS, CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS, CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS. (cpu_flags): Add CpuCX16. * i386-opc.h (CpuCX16): New. (i386_cpu_flags): Add cpucx16. * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b. * i386-tbl.h: Regenerate. * i386-init.h: Likewise. 2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c: Changed ldra and strl-form mnemonics to lda and stl-form. 2012-09-18 Chao-ying Fu <fu@mips.com> * micromips-opc.c (micromips_opcodes): Correct the encoding of the "swxc1" instruction. 2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from the parameter 'inst'. (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'. (convert_mov_to_movewide): Change to assert (0) when aarch64_wide_constant_p returns FALSE. 2012-09-14 David Edelsohn <dje.gcc@gmail.com> * configure: Regenerate. 2012-09-14 Anthony Green <green@moxielogic.com> * moxie-dis.c (print_insn_moxie): Branch targets are relative to the address after the branch instruction. 2012-09-13 Anthony Green <green@moxielogic.com> * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings. 2012-09-10 Matthias Klose <doko@ubuntu.com> * config.in: Disable sanity check for kfreebsd. 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * ia64-asmtab.h (completer_index): Extend bitfield to full uint. * ia64-gen.c: Promote completer index type to longlong. (irf_operand): Add new register recognition. (in_iclass_mov_x): Add an entry for the new mov_* instruction type. (lookup_specifier): Add new resource recognition. (insert_bit_table_ent): Relax abort condition according to the changed completer index type. (print_dis_table): Fix printf format for completer index. * ia64-ic.tbl: Add a new instruction class. * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions. * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions. * ia64-opc.h: Define short names for new operand types. * ia64-raw.tbl: Add new RAW resource for DAHR register. * ia64-waw.tbl: Add new WAW resource for DAHR register. * ia64-asmtab.c: Regenerate. 2012-08-29 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (VXASHB_MASK): New define. (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK. 2012-08-28 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK, VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines. (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip, vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb, vupklsh>: Use VXVA_MASK. <vspltisb, vspltish, vspltisw>: Use VXVB_MASK. <mfvscr>: Use VXVAVB_MASK. <mtvscr>: Use VXVDVA_MASK. <vspltb>: Use VXUIMM4_MASK. <vsplth>: Use VXUIMM3_MASK. <vspltw>: Use VXUIMM2_MASK. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Add 2 operand sha instructions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Handle VMULL.P64. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Add support for AES instructions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add support for HP/DP conversions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add VRINT. (neon_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add support for new VCVT variants. (neon_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM. (neon_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add VSEL. (print_insn_coprocessor): Add new %<>c bitfield format specifier. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions. (thumb32_opcodes): Likewise. (print_arm_insn): Add support for %<>T formatter. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (arm_opcodes): Add HLT. (thumb_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (thumb32_opcodes): Add DCPS instruction. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (arm_opcodes): Add SEVL. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (data_barrier_option): New function. (print_insn_arm): Use data_barrier_option. (print_insn_thumb32): Use data_barrier_option. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com * arm-dis.c (COND_UNCOND): New constant. (print_insn_coprocessor): Add support for %u format specifier. (print_insn_neon): Likewise. 2012-08-21 David S. Miller <davem@davemloft.net> * sparc-opc.c (4-argument crypto instructions): Fix encoding using F3F4 macro. 2012-08-20 Edmar Wienskoski <edmar@freescale.com> * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub, vabsduh, vabsduw, mviwsplt. 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-opc.h: Update CpuPRFCHW comment. * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. 2012-08-17 Nick Clifton <nickc@redhat.com> * po/uk.po: New Ukranian translation. * configure.in (ALL_LINGUAS): Add uk. * configure: Regenerate. 2012-08-16 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and RBX for the third operand. <"lswi">: Use RAX for second and NBI for the third operand. 2012-08-15 DJ Delorie <dj@redhat.com> * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01] operands, so that data addresses can be corrected when not ES-overridden. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Make order of modifiers irrelevent. When the 'e' specifier is used on an operand and no ES prefix is provided, adjust address to make it absolute. 2012-08-15 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR. 2012-08-15 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics. 2012-08-14 Maciej W. Rozycki <macro@codesourcery.com> * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local macros, use local variables for info struct member accesses, update the type of the variable used to hold the instruction word. (print_insn_mips, print_mips16_insn_arg): Likewise. (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use local variables for info struct member accesses. (print_insn_micromips): Add GET_OP_S local macro. (_print_insn_mips): Update the type of the variable used to hold the instruction word. 2012-08-13 Ian Bolton <ian.bolton@arm.com> Laurent Desnogues <laurent.desnogues@arm.com> Jim MacArthur <jim.macarthur@arm.com> Marcus Shawcroft <marcus.shawcroft@arm.com> Nigel Stephens <nigel.stephens@arm.com> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Richard Earnshaw <rearnsha@arm.com> Sofiane Naci <sofiane.naci@arm.com> Tejas Belagod <tejas.belagod@arm.com> Yufeng Zhang <yufeng.zhang@arm.com> * Makefile.am: Add AArch64. * Makefile.in: Regenerate. * aarch64-asm.c: New file. * aarch64-asm.h: New file. * aarch64-dis.c: New file. * aarch64-dis.h: New file. * aarch64-gen.c: New file. * aarch64-opc.c: New file. * aarch64-opc.h: New file. * aarch64-tbl.h: New file. * configure.in: Add AArch64. * configure: Regenerate. * disassemble.c: Add AArch64. * aarch64-asm-2.c: New file (automatically generated). * aarch64-dis-2.c: New file (automatically generated). * aarch64-opc-2.c: New file (automatically generated). * po/POTFILES.in: Regenerate. 2012-08-13 Maciej W. Rozycki <macro@codesourcery.com> * micromips-opc.c (micromips_opcodes): Update comment. * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor instructions for IOCT as appropriate. * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with opcode_is_member. * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with the result of a check for the -Wno-missing-field-initializers GCC option. * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to compilation. (mips16-opc.lo): Likewise. (micromips-opc.lo): Likewise. * aclocal.m4: Regenerate. * configure: Regenerate. * Makefile.in: Regenerate. 2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com> PR gas/14423 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS. * i386-init.h: Regenerated. 2012-08-09 Nick Clifton <nickc@redhat.com> * po/vi.po: Updated Vietnamese translation. 2012-08-07 Roland McGrath <mcgrathr@google.com> * i386-dis.c (reg_table): Fill out REG_0F0D table with AMD-reserved cases as "prefetch". (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants. (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise. (reg_table): Use those under REG_0F18. (mod_table): Add those cases as "nop/reserved". 2012-08-07 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl: Remove "FIXME" comments from SVME instructions. Lines 1–500 of 1066. Load more
2012-12-17 Nick Clifton <nickc@redhat.com> * MAINTAINERS: Add copyright notice. * Makefile.am: Likewise. * configure.com: Likewise. * configure.in: Likewise. * makefile.vms: Likewise. * rl78-decode.c: Likewise. * rl78-decode.opc: Likewise. * rx-decode.c: Likewise. * rx-decode.opc: Likewise. * Makefile.in: Regenerate. 2012-12-13 Alan Modra <amodra@gmail.com> PR binutils/14950 * ppc-opc.c (insert_sci8, extract_sci8): Rewrite. (insert_sci8n, extract_sci8n): Likewise. 2012-11-30 Oleg Raikhman <oleg@adapteva.com> Joern Rennecke <joern.rennecke@embecosm.com> * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate. 2012-11-29 Roland McGrath <mcgrathr@google.com> * s390-mkopc.c (file_header): Add const. 2012-11-29 David Holsgrove <david.holsgrove@xilinx.com> * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to INST_TYPE_R1_R2_SPECIAL * microblaze-dis.c (print_insn_microblaze): Same. 2012-11-23 Alan Modra <amodra@gmail.com> * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits set from ppc_opts.sticky in it. Delete "retain_mask". (powerpc_init_dialect): Choose default dialect from info->mach before parsing -M options. Handle more bfd_mach_ppc variants. Update common default to power7. 2012-11-21 David Holsgrove <david.holsgrove@xilinx.com> * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES. * microblaze-opcm.h (microblaze_instr): Likewise 2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK 2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/14859 * i386-opc.tbl: Fix opcode for 64-bit jecxz. * i386-tbl.h: Regenerated. 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: Fix srstu and strag opcodes. 2012-11-14 David Holsgrove <david.holsgrove@xilinx.com> * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5, update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5, and increase MAX_OPCODES. (op_code_struct): add mbar and sleep * microblaze-opcm.h (microblaze_instr): add mbar Define IMM_MBAR and IMM5_MBAR_MASK * microblaze-dis.c: Add get_field_imm5_mbar (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn * microblaze-opcm.h (microblaze_instr): add clz 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur, lhur, lwr, sbr, shr, swr * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr, swr 2012-11-09 Nick Clifton <nickc@redhat.com> * configure.in: Add bfd_v850_rh850_arch. * configure: Regenerate. * disassemble.c (disassembler): Likewise. 2012-11-09 H.J. Lu <hongjiu.lu@intel.com> * aarch64-opc.h (gen_mask): Remove trailing redundant `;'. * ia64-gen.c (fetch_insn_class): Likewise. 2012-11-08 Alan Modra <amodra@gmail.com> * po/POTFILES.in: Regenerate. 2012-11-05 Alan Modra <amodra@gmail.com> * configure.in: Apply 2012-09-10 change to config.in here. 2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c: Accept empty lines in s390-opc.txt. * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2 and RRF_RMRR. * s390-opc.txt: Add new instructions. New instruction type for lptea. 2012-10-26 Christian Groessler <chris@groessler.org> * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb, trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove non-existing opcode trtrb. * z8k-opc.h: Regenerate. 2012-10-26 Alan Modra <amodra@gmail.com> * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset. 2012-10-24 Roland McGrath <mcgrathr@google.com> * i386-dis.c (ckprefix): When bailing out for fwait with prefixes, set rex_used to rex. 2012-10-22 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling. 2012-10-18 Tom Tromey <tromey@redhat.com> * tic54x-dis.c (print_instruction): Don't use K&R style. (print_parallel_instruction, sprint_dual_address) (sprint_indirect_address, sprint_direct_address, sprint_mmr) (sprint_cc2, sprint_condition): Likewise. 2012-10-18 Kai Tietz <ktietz@redhat.com> * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize value with a default. (do_special_encoding): Likewise. (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2 variables with default. * arc-dis.c (write_comments_): Don't use strncat due size of state->commentBuffer pointer isn't predictable. 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and rmr_el3; remove daifset and daifclr. 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Change to check the alignment of addr.offset.imm instead of that of shifter.amount for operand type AARCH64_OPND_ADDR_UIMM12. 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c: Use preferred form of vrint instruction variants for disassembly. 2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS. * i386-init.h: Regenerated. 2012-10-05 Peter Bergner <bergner@vnet.ibm.com> * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2; * ppc-opc.c (VBA): New define. (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot, mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics. 2012-10-04 Nick Clifton <nickc@redhat.com> * v850-dis.c (disassemble): Place square parentheses around second register operand of clr1, not1, set1 and tst1 instructions. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c: Support new option zEC12. * s390-opc.c: Add new instruction formats. * s390-opc.txt: Add new instructions for zEC12. 2012-09-27 Anthony Green <green@moxielogic.com> * moxie-dis.c (print_insn_moxie): Print 'bad' instructions. * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD. 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> * i386-gen.c (cpu_flag_init): Add missing Cpu flags in CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-init.h: Regenerated. 2012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS, CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS, CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS, CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS. (cpu_flags): Add CpuCX16. * i386-opc.h (CpuCX16): New. (i386_cpu_flags): Add cpucx16. * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b. * i386-tbl.h: Regenerate. * i386-init.h: Likewise. 2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c: Changed ldra and strl-form mnemonics to lda and stl-form. 2012-09-18 Chao-ying Fu <fu@mips.com> * micromips-opc.c (micromips_opcodes): Correct the encoding of the "swxc1" instruction. 2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from the parameter 'inst'. (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'. (convert_mov_to_movewide): Change to assert (0) when aarch64_wide_constant_p returns FALSE. 2012-09-14 David Edelsohn <dje.gcc@gmail.com> * configure: Regenerate. 2012-09-14 Anthony Green <green@moxielogic.com> * moxie-dis.c (print_insn_moxie): Branch targets are relative to the address after the branch instruction. 2012-09-13 Anthony Green <green@moxielogic.com> * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings. 2012-09-10 Matthias Klose <doko@ubuntu.com> * config.in: Disable sanity check for kfreebsd. 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * ia64-asmtab.h (completer_index): Extend bitfield to full uint. * ia64-gen.c: Promote completer index type to longlong. (irf_operand): Add new register recognition. (in_iclass_mov_x): Add an entry for the new mov_* instruction type. (lookup_specifier): Add new resource recognition. (insert_bit_table_ent): Relax abort condition according to the changed completer index type. (print_dis_table): Fix printf format for completer index. * ia64-ic.tbl: Add a new instruction class. * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions. * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions. * ia64-opc.h: Define short names for new operand types. * ia64-raw.tbl: Add new RAW resource for DAHR register. * ia64-waw.tbl: Add new WAW resource for DAHR register. * ia64-asmtab.c: Regenerate. 2012-08-29 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (VXASHB_MASK): New define. (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK. 2012-08-28 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK, VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines. (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip, vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb, vupklsh>: Use VXVA_MASK. <vspltisb, vspltish, vspltisw>: Use VXVB_MASK. <mfvscr>: Use VXVAVB_MASK. <mtvscr>: Use VXVDVA_MASK. <vspltb>: Use VXUIMM4_MASK. <vsplth>: Use VXUIMM3_MASK. <vspltw>: Use VXUIMM2_MASK. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Add 2 operand sha instructions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Handle VMULL.P64. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (neon_opcodes): Add support for AES instructions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add support for HP/DP conversions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add VRINT. (neon_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add support for new VCVT variants. (neon_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM. (neon_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add VSEL. (print_insn_coprocessor): Add new %<>c bitfield format specifier. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions. (thumb32_opcodes): Likewise. (print_arm_insn): Add support for %<>T formatter. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (arm_opcodes): Add HLT. (thumb_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (thumb32_opcodes): Add DCPS instruction. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (arm_opcodes): Add SEVL. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (data_barrier_option): New function. (print_insn_arm): Use data_barrier_option. (print_insn_thumb32): Use data_barrier_option. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com * arm-dis.c (COND_UNCOND): New constant. (print_insn_coprocessor): Add support for %u format specifier. (print_insn_neon): Likewise. 2012-08-21 David S. Miller <davem@davemloft.net> * sparc-opc.c (4-argument crypto instructions): Fix encoding using F3F4 macro. 2012-08-20 Edmar Wienskoski <edmar@freescale.com> * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub, vabsduh, vabsduw, mviwsplt. 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-opc.h: Update CpuPRFCHW comment. * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. 2012-08-17 Nick Clifton <nickc@redhat.com> * po/uk.po: New Ukranian translation. * configure.in (ALL_LINGUAS): Add uk. * configure: Regenerate. 2012-08-16 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and RBX for the third operand. <"lswi">: Use RAX for second and NBI for the third operand. 2012-08-15 DJ Delorie <dj@redhat.com> * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01] operands, so that data addresses can be corrected when not ES-overridden. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Make order of modifiers irrelevent. When the 'e' specifier is used on an operand and no ES prefix is provided, adjust address to make it absolute. 2012-08-15 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR. 2012-08-15 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics. 2012-08-14 Maciej W. Rozycki <macro@codesourcery.com> * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local macros, use local variables for info struct member accesses, update the type of the variable used to hold the instruction word. (print_insn_mips, print_mips16_insn_arg): Likewise. (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use local variables for info struct member accesses. (print_insn_micromips): Add GET_OP_S local macro. (_print_insn_mips): Update the type of the variable used to hold the instruction word. 2012-08-13 Ian Bolton <ian.bolton@arm.com> Laurent Desnogues <laurent.desnogues@arm.com> Jim MacArthur <jim.macarthur@arm.com> Marcus Shawcroft <marcus.shawcroft@arm.com> Nigel Stephens <nigel.stephens@arm.com> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Richard Earnshaw <rearnsha@arm.com> Sofiane Naci <sofiane.naci@arm.com> Tejas Belagod <tejas.belagod@arm.com> Yufeng Zhang <yufeng.zhang@arm.com> * Makefile.am: Add AArch64. * Makefile.in: Regenerate. * aarch64-asm.c: New file. * aarch64-asm.h: New file. * aarch64-dis.c: New file. * aarch64-dis.h: New file. * aarch64-gen.c: New file. * aarch64-opc.c: New file. * aarch64-opc.h: New file. * aarch64-tbl.h: New file. * configure.in: Add AArch64. * configure: Regenerate. * disassemble.c: Add AArch64. * aarch64-asm-2.c: New file (automatically generated). * aarch64-dis-2.c: New file (automatically generated). * aarch64-opc-2.c: New file (automatically generated). * po/POTFILES.in: Regenerate. 2012-08-13 Maciej W. Rozycki <macro@codesourcery.com> * micromips-opc.c (micromips_opcodes): Update comment. * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor instructions for IOCT as appropriate. * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with opcode_is_member. * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with the result of a check for the -Wno-missing-field-initializers GCC option. * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to compilation. (mips16-opc.lo): Likewise. (micromips-opc.lo): Likewise. * aclocal.m4: Regenerate. * configure: Regenerate. * Makefile.in: Regenerate. 2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com> PR gas/14423 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS. * i386-init.h: Regenerated. 2012-08-09 Nick Clifton <nickc@redhat.com> * po/vi.po: Updated Vietnamese translation. 2012-08-07 Roland McGrath <mcgrathr@google.com> * i386-dis.c (reg_table): Fill out REG_0F0D table with AMD-reserved cases as "prefetch". (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants. (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise. (reg_table): Use those under REG_0F18. (mod_table): Add those cases as "nop/reserved". 2012-08-07 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.