2016-12-31  Alan Modra  <amodra@gmail.com> 	* disassemble.c (disassembler): Add break accidentally removed	by PRU patch. 2016-12-31  Dimitar Dimitrov  <dimitar@dinux.eu> 	* Makefile.am: Add PRU source files.	* configure.ac: Add PRU target.	* disassemble.c (disassembler): Register PRU arch.	* pru-dis.c: New file.	* pru-opc.c: New file.	* Makefile.in: Regenerate.	* configure: Regenerate. 2016-12-29  Yao Qi  <yao.qi@linaro.org> 	* avr-dis.c: Include "bfd_stdint.h"	(avrdis_opcode): Change return type to int, add argument	insn.  Set *INSN on success.	(print_insn_avr): Check return value of avrdis_opcode, and	return -1 on error. 2016-12-28  Alan Modra  <amodra@gmail.com> 	* configure.ac: Revert 2016-12-23.	* Makefile.am: Likewise.	(MIPS_DEFS): Define.	(mips-dis.lo): Add rule.	* Makefile.in: Regenerate.	* aclocal.m4: Regenerate.	* config.in: Regenerate.	* configure: Regenerate. 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',	`4' and `s' operand codes.	(mips16_opcodes): Add "asmacro" entry. 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_mips16_insn_arg): Simplify processing of	extended operands.	* mips16-opc.c (decode_mips16_operand): Switch the extended	form of the `<' operand type to LSB position 22. 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'	operand codes with `.' and `F' respectively.	(mips16_opcodes): Likewise. 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix	matching for INSN2_SHORT_ONLY opcode table entries.	* mips16-opc.c (SH): New macro.	(mips16_opcodes): Set SH in `pinfo2' for non-extensible	instruction entries: "nop", "addu", "and", "break", "cmp",	"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",	"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",	"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",	"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",	"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",	"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",	"seh", "sew", "zeb", "zeh", "zew" and "extend". 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended	encoding support. 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for	"extend". 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (set_default_mips_dis_options): Use	HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the	call to `bfd_mips_elf_get_abiflags'.	* configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.	* aclocal.m4: Regenerate.	* configure: Regenerate.	* config.in: Regenerate.	* Makefile.in: Regenerate. 2016-12-23  Tristan Gingold  <gingold@adacore.com> 	* configure: Regenerate. 2016-12-23  Tristan Gingold  <gingold@adacore.com> 	* po/opcodes.pot: Regenerate. 2016-12-21  Andrew Waterman  <andrew@sifive.com> 	* riscv-opc.c (riscv_opcodes): Reorder jal and call entries. 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than	ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.	(print_insn_mips16): Check opcode entries for validity against	the ISA level and ASE set selected. 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and	`insn' together, with `extend' as the high-order 16 bits.	(match_kind): New enum.	(print_insn_mips16): Rework for 32-bit instruction matching.	Do not dump EXTEND prefixes here.	* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.	Recode `match' and `mask' fields as 32-bit in absolute "jal" and	"jalx" entries. 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (mips16_opcodes): Set membership to I3 rather	than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"	INSN_MACRO entries. 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (mips16_opcodes): Set membership to I3 rather	than I1 for the SP-relative "sd"/$ra entry (SDRASP minor	opcode). 2016-12-20  Andrew Waterman  <andrew@sifive.com> 	* riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to	"*.aqrl". 2016-12-20  Andrew Waterman  <andrew@sifive.com> 	* riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as	INSN_ALIAS. 2016-12-20  Andrew Waterman  <andrew@sifive.com> 	* riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"	format. 2016-12-20  Andrew Waterman  <andrew@sifive.com> 	* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's	XLEN when none is provided. 2016-12-20  Andrew Waterman  <andrew@sifive.com> 	* riscv-opc.c: Formatting fixes. 2016-12-20  Alan Modra  <amodra@gmail.com> 	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.	* Makefile.in: Regenerate.	* po/POTFILES.in: Regenerate. 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:	Only examine ELF file structures here. 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call	`bfd_mips_elf_get_abiflags' here. 2016-12-16  Nick Clifton  <nickc@redhat.com> 	* arm-dis.c (print_insn_thumb32): Fix compile time warning	computing value_in_comment. 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (mips_convert_abiflags_ases): New function.	(set_default_mips_dis_options): Also infer ASE flags from ELF	file structures. 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (set_default_mips_dis_options): Reorder ELF file	header flag interpretation code. 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in	`pinfo2' with SP-relative "sd" entries. 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (mips16_opcodes): Update comments on MIPS16e	compact jumps. 2016-12-13 Renlin Li <renlin.li@arm.com> 	* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range	qualifier.	(operand_general_constraint_met_p): Remove case for CP_REG.	(aarch64_print_operand): Print CRn, CRm operand using imm field.	* aarch64-tbl.h (QL_SYS): Use CR qualifier.	(QL_SYSL): Likewise.	(aarch64_opcode_table): Change CRn, CRm operand class and type.	* aarch64-opc-2.c : Regenerate.	* aarch64-asm-2.c : Likewise.	* aarch64-dis-2.c : Likewise. 2016-12-12  Yao Qi  <yao.qi@linaro.org> 	* rx-dis.c: Include <setjmp.h>	(struct private): New.	(rx_get_byte): Check return value of read_memory_func, and	call memory_error_func and OPCODES_SIGLONGJMP on error.	(print_insn_rx): Call OPCODES_SIGSETJMP. 2016-12-12  Yao Qi  <yao.qi@linaro.org> 	* rl78-dis.c: Include <setjmp.h>.	(struct private): New.	(rl78_get_byte): Check return value of read_memory_func, and	call memory_error_func and OPCODES_SIGLONGJMP on error.	(print_insn_rl78_common): Call OPCODES_SIGJMP. 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases. 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather	than UINT. 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_insn_mips16): Use a tab rather than a space	to separate `extend' and its uninterpreted argument output.	Separate hexadecimal halves of undecoded extended instructions	output. 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_mips16_insn_arg): Remove extraneous	indentation space across. 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_mips16_insn_arg): Avoid delay-slot	adjustment for PC-relative operations following MIPS16e compact	jumps or undefined RR/J(AL)R(C) encodings. 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com> 	* aarch64-asm.c (aarch64_ins_reglane): Rename `index' local	variable to `reglane_index'. 2016-12-08  Luis Machado  <lgustavo@codesourcery.com> 	* ppc-dis.c (get_powerpc_dialect): Check NULL info->section. 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_mips16_insn_arg): Fix comment typo. 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com> 	* mips16-opc.c (mips16_opcodes): Update comment naming structure	members. 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com> 	* mips-dis.c (print_mips_disassembler_options): Reformat output. 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.	(print_insn_coprocessor): Add 'V' format for neon D or Q regs. 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* arm-dis.c (coprocessor_opcodes): Add vjcvt. 2016-12-01  Nick Clifton  <nickc@redhat.com> 	PR binutils/20893	* i386-dis.c (OP_VEX): Replace call to abort with a append of bad	opcode designator. 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com> 	* arc-opc.c (insert_ra_chk): New function.	(insert_rb_chk): Likewise.	(insert_rad): Update text error message.	(insert_rcd): Likewise.	(insert_rhv2): Likewise.	(insert_r0): Likewise.	(insert_r1): Likewise.	(insert_r2): Likewise.	(insert_r3): Likewise.	(insert_sp): Likewise.	(insert_gp): Likewise.	(insert_pcl): Likewise.	(insert_blink): Likewise.	(insert_ilink1): Likewise.	(insert_ilink2): Likewise.	(insert_ras): Likewise.	(insert_rbs): Likewise.	(insert_rcs): Likewise.	(insert_simm3s): Likewise.	(insert_rrange): Likewise.	(insert_fpel): Likewise.	(insert_blinkel): Likewise.	(insert_pcel): Likewise.	(insert_nps_3bit_dst): Likewise.	(insert_nps_3bit_dst_short): Likewise.	(insert_nps_3bit_src2_short): Likewise.	(insert_nps_bitop_size_2b): Likewise.	(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.	(RA_CHK): Define.	(RB): Adjust.	(RB_CHK): Define.	(RC): Adjust.	* arc-dis.c (print_insn_arc): Add LOAD and STORE class.	* arc-tbl.h (div, divu): All instructions are DIVREM class.	Change first insn argument to check for LP_COUNT usage.	(rem): Likewise.	(ld, ldd): All instructions are LOAD class.  Change first insn	argument to check for LP_COUNT usage.	(st, std): All instructions are STORE class.	(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.	Change first insn argument to check for LP_COUNT usage.	(mov): All instructions are MOVE class.  Change first insn	argument to check for LP_COUNT usage. 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com> 	* arc-dis.c (is_compatible_p): Remove function.	(skip_this_opcode): Don't add any decoding class to decode list.	Remove warning.	(find_format_from_table): Go through all opcodes, and warn if we	use a guessed mnemonic. 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>	    Amit Pawar  <amit.pawar@amd.com> 	PR binutils/20637	* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP	instructions. 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>         * configure: Regenerate. 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com> 	* sparc-opc.c (HWS_V8): Definition moved from	gas/config/tc-sparc.c.	(HWS_V9): Likewise.	(HWS_VA): Likewise.	(HWS_VB): Likewise.	(HWS_VC): Likewise.	(HWS_VD): Likewise.	(HWS_VE): Likewise.	(HWS_VV): Likewise.	(HWS_VM): Likewise.	(HWS2_VM): Likewise.	(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of	existing entries. 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com> 	* arc-tbl.h: Reorder conditional flags with delay flags for 'b'	instructions. 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.	(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.	(aarch64_opcode_table): Add fcmla and fcadd.	(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.	* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.	* aarch64-asm.c (aarch64_ins_imm_rotate): Define.	* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.	* aarch64-dis.c (aarch64_ext_imm_rotate): Define.	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.	* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.	(operand_general_constraint_met_p): Rotate and index range check.	(aarch64_print_operand): Handle rotate operand.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Likewise.	* aarch64-opc-2.c: Likewise. 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Regenerate.	* aarch64-opc-2.c: Regenerate. 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.	(QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Regenerate.	* aarch64-opc-2.c: Regenerate. 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (QL_X1NIL): New.	(arch64_opcode_table): Add ldraa, ldrab.	(AARCH64_OPERANDS): Add "ADDR_SIMM10".	* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.	* aarch64-asm.c (aarch64_ins_addr_simm10): Define.	* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.	* aarch64-dis.c (aarch64_ext_addr_simm10): Define.	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.	* aarch64-opc.c (fields): Add data for FLD_S_simm10.	(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.	(aarch64_print_operand): Likewise.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Regenerate.	* aarch64-opc-2.c: Regenerate. 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,	brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Regenerate.	* aarch64-opc-2.c: Regenerate. 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (arch64_opcode_table): Add pacga.	(AARCH64_OPERANDS): Add Rm_SP.	* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Regenerate.	* aarch64-opc-2.c: Regenerate. 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,	autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,	autdzb, xpaci, xpacd.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Regenerate.	* aarch64-opc-2.c: Regenerate. 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,	apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,	apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.	(aarch64_sys_reg_supported_p): Add feature test for new registers. 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.	(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,	autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,	autibsp.	* aarch64-asm-2.c: Regenerate.	* aarch64-dis-2.c: Regenerate. 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com> 	* aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32. 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com> 	PR binutils/20799	* i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.	* i386-dis.c (EdqwS): Removed.	(dqw_swap_mode): Likewise.	(intel_operand_size): Don't check dqw_swap_mode.	(OP_E_register): Likewise.	(OP_E_memory): Likewise.	(OP_G): Likewise.	(OP_EX): Likewise.	* i386-opc.tbl: Remove "S" from EVEX vpextrw.	* i386-tbl.h: Regerated. 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com> 	* i386-opc.tbl: Merge AVX512F vmovq.	* i386-tbl.h: Regerated. 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com> 	PR binutils/20701	* i386-dis.c (THREE_BYTE_0F7A): Removed.	(dis386_twobyte): Don't use THREE_BYTE_0F7A.	(three_byte_table): Remove THREE_BYTE_0F7A. 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>

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