/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */ #include "amdgpu.h"#include "amdgpu_atombios.h"#include "amdgpu_i2c.h"#include "amdgpu_dpm.h"#include "atom.h"#include "amd_pcie.h"#include "amdgpu_display.h"#include "hwmgr.h"#include <linux/power_supply.h>#include "amdgpu_smu.h" #define amdgpu_dpm_notify_ac_dc(adev) \		((adev)->powerplay.pp_funcs->notify_ac_dc((adev)->powerplay.pp_handle)) #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	int ret = 0; 	if (!pp_funcs->get_sclk)		return 0; 	mutex_lock(&adev->pm.mutex);	ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle,				 low);	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	int ret = 0; 	if (!pp_funcs->get_mclk)		return 0; 	mutex_lock(&adev->pm.mutex);	ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle,				 low);	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,				       uint32_t block_type,				       bool gate,				       int inst){	int ret = 0;	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;	bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; 	mutex_lock(&adev->pm.mutex); 	if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state &&			(!is_vcn || adev->vcn.num_vcn_inst == 1)) {		dev_dbg(adev->dev, "IP block%d already in the target %s state!",				block_type, gate ? "gate" : "ungate");		goto out_unlock;	} 	switch (block_type) {	case AMD_IP_BLOCK_TYPE_UVD:	case AMD_IP_BLOCK_TYPE_VCE:	case AMD_IP_BLOCK_TYPE_GFX:	case AMD_IP_BLOCK_TYPE_SDMA:	case AMD_IP_BLOCK_TYPE_JPEG:	case AMD_IP_BLOCK_TYPE_GMC:	case AMD_IP_BLOCK_TYPE_ACP:	case AMD_IP_BLOCK_TYPE_VPE:	case AMD_IP_BLOCK_TYPE_ISP:		if (pp_funcs && pp_funcs->set_powergating_by_smu)			ret = (pp_funcs->set_powergating_by_smu(				(adev)->powerplay.pp_handle, block_type, gate, 0));		break;	case AMD_IP_BLOCK_TYPE_VCN:		if (pp_funcs && pp_funcs->set_powergating_by_smu)			ret = (pp_funcs->set_powergating_by_smu(				(adev)->powerplay.pp_handle, block_type, gate, inst));		break;	default:		break;	} 	if (!ret)		atomic_set(&adev->pm.pwr_state[block_type], pwr_state); out_unlock:	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev){	struct smu_context *smu = adev->powerplay.pp_handle;	int ret = -EOPNOTSUPP; 	mutex_lock(&adev->pm.mutex);	ret = smu_set_gfx_power_up_by_imu(smu);	mutex_unlock(&adev->pm.mutex); 	msleep(10); 	return ret;} int amdgpu_dpm_baco_enter(struct amdgpu_device *adev){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	void *pp_handle = adev->powerplay.pp_handle;	int ret = 0; 	if (!pp_funcs || !pp_funcs->set_asic_baco_state)		return -ENOENT; 	mutex_lock(&adev->pm.mutex); 	/* enter BACO state */	ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_baco_exit(struct amdgpu_device *adev){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	void *pp_handle = adev->powerplay.pp_handle;	int ret = 0; 	if (!pp_funcs || !pp_funcs->set_asic_baco_state)		return -ENOENT; 	mutex_lock(&adev->pm.mutex); 	/* exit BACO state */	ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,			     enum pp_mp1_state mp1_state){	int ret = 0;	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 	if (mp1_state == PP_MP1_STATE_FLR) {		/* VF lost access to SMU */		if (amdgpu_sriov_vf(adev))			adev->pm.dpm_enabled = false;	} else if (pp_funcs && pp_funcs->set_mp1_state) {		mutex_lock(&adev->pm.mutex); 		ret = pp_funcs->set_mp1_state(				adev->powerplay.pp_handle,				mp1_state); 		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	void *pp_handle = adev->powerplay.pp_handle;	int ret; 	if (!pp_funcs || !pp_funcs->get_asic_baco_capability)		return 0;	/* Don't use baco for reset in S3.	 * This is a workaround for some platforms	 * where entering BACO during suspend	 * seems to cause reboots or hangs.	 * This might be related to the fact that BACO controls	 * power to the whole GPU including devices like audio and USB.	 * Powering down/up everything may adversely affect these other	 * devices.  Needs more investigation.	 */	if (adev->in_s3)		return 0; 	mutex_lock(&adev->pm.mutex); 	ret = pp_funcs->get_asic_baco_capability(pp_handle); 	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	void *pp_handle = adev->powerplay.pp_handle;	int ret = 0; 	if (!pp_funcs || !pp_funcs->asic_reset_mode_2)		return -ENOENT; 	mutex_lock(&adev->pm.mutex); 	ret = pp_funcs->asic_reset_mode_2(pp_handle); 	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	void *pp_handle = adev->powerplay.pp_handle;	int ret = 0; 	if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features)		return -ENOENT; 	mutex_lock(&adev->pm.mutex); 	ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); 	mutex_unlock(&adev->pm.mutex); 	return ret;} int amdgpu_dpm_baco_reset(struct amdgpu_device *adev){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	void *pp_handle = adev->powerplay.pp_handle;	int ret = 0; 	if (!pp_funcs || !pp_funcs->set_asic_baco_state)		return -ENOENT; 	mutex_lock(&adev->pm.mutex); 	/* enter BACO state */	ret = pp_funcs->set_asic_baco_state(pp_handle, 1);	if (ret)		goto out; 	/* exit BACO state */	ret = pp_funcs->set_asic_baco_state(pp_handle, 0); out:	mutex_unlock(&adev->pm.mutex);	return ret;} bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev){	struct smu_context *smu = adev->powerplay.pp_handle;	bool support_mode1_reset = false; 	if (is_support_sw_smu(adev)) {		mutex_lock(&adev->pm.mutex);		support_mode1_reset = smu_mode1_reset_is_support(smu);		mutex_unlock(&adev->pm.mutex);	} 	return support_mode1_reset;} int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev){	struct smu_context *smu = adev->powerplay.pp_handle;	int ret = -EOPNOTSUPP; 	if (is_support_sw_smu(adev)) {		mutex_lock(&adev->pm.mutex);		ret = smu_mode1_reset(smu);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev){	struct smu_context *smu = adev->powerplay.pp_handle;	bool support_link_reset = false; 	if (is_support_sw_smu(adev)) {		mutex_lock(&adev->pm.mutex);		support_link_reset = smu_link_reset_is_support(smu);		mutex_unlock(&adev->pm.mutex);	} 	return support_link_reset;} int amdgpu_dpm_link_reset(struct amdgpu_device *adev){	struct smu_context *smu = adev->powerplay.pp_handle;	int ret = -EOPNOTSUPP; 	if (is_support_sw_smu(adev)) {		mutex_lock(&adev->pm.mutex);		ret = smu_link_reset(smu);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,				    enum PP_SMC_POWER_PROFILE type,				    bool en){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	int ret = 0; 	if (amdgpu_sriov_vf(adev))		return 0; 	if (pp_funcs && pp_funcs->switch_power_profile) {		mutex_lock(&adev->pm.mutex);		ret = pp_funcs->switch_power_profile(			adev->powerplay.pp_handle, type, en);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev,				   bool pause){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	int ret = 0; 	if (amdgpu_sriov_vf(adev))		return 0; 	if (pp_funcs && pp_funcs->pause_power_profile) {		mutex_lock(&adev->pm.mutex);		ret = pp_funcs->pause_power_profile(			adev->powerplay.pp_handle, pause);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,			       uint32_t pstate){	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	int ret = 0; 	if (pp_funcs && pp_funcs->set_xgmi_pstate) {		mutex_lock(&adev->pm.mutex);		ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,								pstate);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,			     uint32_t cstate){	int ret = 0;	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;	void *pp_handle = adev->powerplay.pp_handle; 	if (pp_funcs && pp_funcs->set_df_cstate) {		mutex_lock(&adev->pm.mutex);		ret = pp_funcs->set_df_cstate(pp_handle, cstate);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev,				      enum pp_pm_policy p_type, char *buf){	struct smu_context *smu = adev->powerplay.pp_handle;	int ret = -EOPNOTSUPP; 	if (is_support_sw_smu(adev)) {		mutex_lock(&adev->pm.mutex);		ret = smu_get_pm_policy_info(smu, p_type, buf);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type,			     int policy_level){	struct smu_context *smu = adev->powerplay.pp_handle;	int ret = -EOPNOTSUPP; 	if (is_support_sw_smu(adev)) {		mutex_lock(&adev->pm.mutex);		ret = smu_set_pm_policy(smu, policy_type, policy_level);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev){	void *pp_handle = adev->powerplay.pp_handle;	const struct amd_pm_funcs *pp_funcs =			adev->powerplay.pp_funcs;	int ret = 0; 	if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) {		mutex_lock(&adev->pm.mutex);		ret = pp_funcs->enable_mgpu_fan_boost(pp_handle);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,				      uint32_t msg_id){	void *pp_handle = adev->powerplay.pp_handle;	const struct amd_pm_funcs *pp_funcs =			adev->powerplay.pp_funcs;	int ret = 0; 	if (pp_funcs && pp_funcs->set_clockgating_by_smu) {		mutex_lock(&adev->pm.mutex);		ret = pp_funcs->set_clockgating_by_smu(pp_handle,						       msg_id);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,				  bool acquire){	void *pp_handle = adev->powerplay.pp_handle;	const struct amd_pm_funcs *pp_funcs =			adev->powerplay.pp_funcs;	int ret = -EOPNOTSUPP; 	if (pp_funcs && pp_funcs->smu_i2c_bus_access) {		mutex_lock(&adev->pm.mutex);		ret = pp_funcs->smu_i2c_bus_access(pp_handle,						   acquire);		mutex_unlock(&adev->pm.mutex);	} 	return ret;} void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev){	if (adev->pm.dpm_enabled) {		mutex_lock(&adev->pm.mutex);

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