// SPDX-License-Identifier: GPL-2.0/* * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO) * *  Copyright (C) 2002 - 2011  Paul Mundt *  Copyright (C) 2015 Glider bvba *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). * * based off of the old drivers/char/sh-sci.c by: * *   Copyright (C) 1999, 2000  Niibe Yutaka *   Copyright (C) 2000  Sugioka Toshinobu *   Modified to support multiple serial ports. Stuart Menefy (May 2000). *   Modified to support SecureEdge. David McCullough (2002) *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). *   Removed SH7300 support (Jul 2007). */#undef DEBUG #include <linux/bitops.h>#include <linux/clk.h>#include <linux/console.h>#include <linux/cpufreq.h>#include <linux/ctype.h>#include <linux/delay.h>#include <linux/dma-mapping.h>#include <linux/dmaengine.h>#include <linux/err.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/ioport.h>#include <linux/ktime.h>#include <linux/major.h>#include <linux/minmax.h>#include <linux/mm.h>#include <linux/module.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/reset.h>#include <linux/scatterlist.h>#include <linux/serial.h>#include <linux/serial_core.h>#include <linux/serial_sci.h>#include <linux/sh_dma.h>#include <linux/slab.h>#include <linux/string.h>#include <linux/sysrq.h>#include <linux/timer.h>#include <linux/tty.h>#include <linux/tty_flip.h> #ifdef CONFIG_SUPERH#include <asm/platform_early.h>#include <asm/sh_bios.h>#endif #include "rsci.h"#include "serial_mctrl_gpio.h"#include "sh-sci-common.h" #define SCI_MAJOR		204#define SCI_MINOR_START		8 /* * SCI register subset common for all port types. * Not all registers will exist on all parts. */enum {	SCSMR,		/* Serial Mode Register */	SCBRR,		/* Bit Rate Register */	SCSCR,		/* Serial Control Register */	SCxSR,		/* Serial Status Register */	SCFCR,		/* FIFO Control Register */	SCFDR,		/* FIFO Data Count Register */	SCxTDR,		/* Transmit (FIFO) Data Register */	SCxRDR,		/* Receive (FIFO) Data Register */	SCLSR,		/* Line Status Register */	SCTFDR,		/* Transmit FIFO Data Count Register */	SCRFDR,		/* Receive FIFO Data Count Register */	SCSPTR,		/* Serial Port Register */	HSSRR,		/* Sampling Rate Register */	SCPCR,		/* Serial Port Control Register */	SCPDR,		/* Serial Port Data Register */	SCDL,		/* BRG Frequency Division Register */	SCCKS,		/* BRG Clock Select Register */	HSRTRGR,	/* Rx FIFO Data Count Trigger Register */	HSTTRGR,	/* Tx FIFO Data Count Trigger Register */	SEMR,		/* Serial extended mode register */}; /* SCSMR (Serial Mode Register) */#define SCSMR_C_A	BIT(7)	/* Communication Mode */#define SCSMR_CSYNC	BIT(7)	/*   - Clocked synchronous mode */#define SCSMR_ASYNC	0	/*   - Asynchronous mode */#define SCSMR_CHR	BIT(6)	/* 7-bit Character Length */#define SCSMR_PE	BIT(5)	/* Parity Enable */#define SCSMR_ODD	BIT(4)	/* Odd Parity */#define SCSMR_STOP	BIT(3)	/* Stop Bit Length */#define SCSMR_CKS	0x0003	/* Clock Select */ /* Serial Mode Register, SCIFA/SCIFB only bits */#define SCSMR_CKEDG	BIT(12)	/* Transmit/Receive Clock Edge Select */#define SCSMR_SRC_MASK	0x0700	/* Sampling Control */#define SCSMR_SRC_16	0x0000	/* Sampling rate 1/16 */#define SCSMR_SRC_5	0x0100	/* Sampling rate 1/5 */#define SCSMR_SRC_7	0x0200	/* Sampling rate 1/7 */#define SCSMR_SRC_11	0x0300	/* Sampling rate 1/11 */#define SCSMR_SRC_13	0x0400	/* Sampling rate 1/13 */#define SCSMR_SRC_17	0x0500	/* Sampling rate 1/17 */#define SCSMR_SRC_19	0x0600	/* Sampling rate 1/19 */#define SCSMR_SRC_27	0x0700	/* Sampling rate 1/27 */ /* Serial Control Register, SCI only bits */#define SCSCR_TEIE	BIT(2)  /* Transmit End Interrupt Enable */ /* Serial Control Register, SCIFA/SCIFB only bits */#define SCSCR_TDRQE	BIT(15)	/* Tx Data Transfer Request Enable */#define SCSCR_RDRQE	BIT(14)	/* Rx Data Transfer Request Enable */ /* Serial Control Register, HSCIF-only bits */#define HSSCR_TOT_SHIFT	14 /* SCxSR (Serial Status Register) on SCI */#define SCI_TDRE	BIT(7)	/* Transmit Data Register Empty */#define SCI_RDRF	BIT(6)	/* Receive Data Register Full */#define SCI_ORER	BIT(5)	/* Overrun Error */#define SCI_FER		BIT(4)	/* Framing Error */#define SCI_PER		BIT(3)	/* Parity Error */#define SCI_TEND	BIT(2)	/* Transmit End */#define SCI_RESERVED	0x03	/* All reserved bits */ #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) #define SCI_RDxF_CLEAR	(u32)(~(SCI_RESERVED | SCI_RDRF))#define SCI_ERROR_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))#define SCI_TDxE_CLEAR	(u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))#define SCI_BREAK_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */#define SCIF_ER		BIT(7)	/* Receive Error */#define SCIF_TEND	BIT(6)	/* Transmission End */#define SCIF_TDFE	BIT(5)	/* Transmit FIFO Data Empty */#define SCIF_BRK	BIT(4)	/* Break Detect */#define SCIF_FER	BIT(3)	/* Framing Error */#define SCIF_PER	BIT(2)	/* Parity Error */#define SCIF_RDF	BIT(1)	/* Receive FIFO Data Full */#define SCIF_DR		BIT(0)	/* Receive Data Ready *//* SCIF only (optional) */#define SCIF_PERC	0xf000	/* Number of Parity Errors */#define SCIF_FERC	0x0f00	/* Number of Framing Errors *//*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */#define SCIFA_ORER	BIT(9)	/* Overrun Error */ #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER) #define SCIF_RDxF_CLEAR		(u32)(~(SCIF_DR | SCIF_RDF))#define SCIF_ERROR_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))#define SCIF_TDxE_CLEAR		(u32)(~(SCIF_TDFE))#define SCIF_BREAK_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) /* SCFCR (FIFO Control Register) */#define SCFCR_RTRG1	BIT(7)	/* Receive FIFO Data Count Trigger */#define SCFCR_RTRG0	BIT(6)#define SCFCR_TTRG1	BIT(5)	/* Transmit FIFO Data Count Trigger */#define SCFCR_TTRG0	BIT(4)#define SCFCR_MCE	BIT(3)	/* Modem Control Enable */#define SCFCR_TFRST	BIT(2)	/* Transmit FIFO Data Register Reset */#define SCFCR_RFRST	BIT(1)	/* Receive FIFO Data Register Reset */#define SCFCR_LOOP	BIT(0)	/* Loopback Test */ /* SCLSR (Line Status Register) on (H)SCIF */#define SCLSR_TO	BIT(2)	/* Timeout */#define SCLSR_ORER	BIT(0)	/* Overrun Error */ /* SCSPTR (Serial Port Register), optional */#define SCSPTR_RTSIO	BIT(7)	/* Serial Port RTS# Pin Input/Output */#define SCSPTR_RTSDT	BIT(6)	/* Serial Port RTS# Pin Data */#define SCSPTR_CTSIO	BIT(5)	/* Serial Port CTS# Pin Input/Output */#define SCSPTR_CTSDT	BIT(4)	/* Serial Port CTS# Pin Data */#define SCSPTR_SCKIO	BIT(3)	/* Serial Port Clock Pin Input/Output */#define SCSPTR_SCKDT	BIT(2)	/* Serial Port Clock Pin Data */#define SCSPTR_SPB2IO	BIT(1)	/* Serial Port Break Input/Output */#define SCSPTR_SPB2DT	BIT(0)	/* Serial Port Break Data */ /* HSSRR HSCIF */#define HSCIF_SRE	BIT(15)	/* Sampling Rate Register Enable */#define HSCIF_SRDE	BIT(14) /* Sampling Point Register Enable */ #define HSCIF_SRHP_SHIFT	8#define HSCIF_SRHP_MASK		0x0f00 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */#define SCPCR_RTSC	BIT(4)	/* Serial Port RTS# Pin / Output Pin */#define SCPCR_CTSC	BIT(3)	/* Serial Port CTS# Pin / Input Pin */#define SCPCR_SCKC	BIT(2)	/* Serial Port SCK Pin / Output Pin */#define SCPCR_RXDC	BIT(1)	/* Serial Port RXD Pin / Input Pin */#define SCPCR_TXDC	BIT(0)	/* Serial Port TXD Pin / Output Pin */ /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */#define SCPDR_RTSD	BIT(4)	/* Serial Port RTS# Output Pin Data */#define SCPDR_CTSD	BIT(3)	/* Serial Port CTS# Input Pin Data */#define SCPDR_SCKD	BIT(2)	/* Serial Port SCK Output Pin Data */#define SCPDR_RXDD	BIT(1)	/* Serial Port RXD Input Pin Data */#define SCPDR_TXDD	BIT(0)	/* Serial Port TXD Output Pin Data */ /* * BRG Clock Select Register (Some SCIF and HSCIF) * The Baud Rate Generator for external clock can provide a clock source for * the sampling clock. It outputs either its frequency divided clock, or the * (undivided) (H)SCK external clock. */#define SCCKS_CKS	BIT(15)	/* Select (H)SCK (1) or divided SC_CLK (0) */#define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ #define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)#define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_DR | SCIF_RDF)#define SCxSR_TDxE(port)	(((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)#define SCxSR_FER(port)		(((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)#define SCxSR_PER(port)		(((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)#define SCxSR_BRK(port)		(((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK) #define SCxSR_ERRORS(port)	(to_sci_port(port)->params->error_mask) #define SCxSR_RDxF_CLEAR(port) \	(((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)#define SCxSR_ERROR_CLEAR(port) \	(to_sci_port(port)->params->error_clear)#define SCxSR_TDxE_CLEAR(port) \	(((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)#define SCxSR_BREAK_CLEAR(port) \	(((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR) #define SCIx_IRQ_IS_MUXED(port)			\	((port)->irqs[SCIx_ERI_IRQ] ==	\	 (port)->irqs[SCIx_RXI_IRQ]) ||	\	((port)->irqs[SCIx_ERI_IRQ] &&	\	 ((port)->irqs[SCIx_RXI_IRQ] < 0)) #define SCI_SR_SCIFAB		SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \				SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \				SCI_SR(19) | SCI_SR(27) /* Iterate over all supported sampling rates, from high to low */#define for_each_sr(_sr, _port)						\	for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)	\		if ((_port)->sampling_rate_mask & SCI_SR((_sr))) #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS #define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port)) static struct sci_port sci_ports[SCI_NPORTS];static unsigned long sci_ports_in_use;static struct uart_driver sci_uart_driver;static bool sci_uart_earlycon;static bool sci_uart_earlycon_dev_probing; static const struct sci_port_params_bits sci_sci_port_params_bits = {	.rxtx_enable = SCSCR_RE | SCSCR_TE,	.te_clear = SCSCR_TE | SCSCR_TEIE,	.poll_sent_bits = SCI_TDRE | SCI_TEND}; static const struct sci_port_params_bits sci_scif_port_params_bits = {	.rxtx_enable = SCSCR_RE | SCSCR_TE,	.te_clear = SCSCR_TE | SCSCR_TEIE,	.poll_sent_bits = SCIF_TDFE | SCIF_TEND}; static const struct sci_common_regs sci_common_regs = {	.status = SCxSR,	.control = SCSCR,}; struct sci_suspend_regs {	u16 scdl;	u16 sccks;	u16 scsmr;	u16 scscr;	u16 scfcr;	u16 scsptr;	u16 hssrr;	u16 scpcr;	u16 scpdr;	u8 scbrr;	u8 semr;}; static size_t sci_suspend_regs_size(void){	return sizeof(struct sci_suspend_regs);} static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {	/*	 * Common SCI definitions, dependent on the port's regshift	 * value.	 */	[SCIx_SCI_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00,  8 },			[SCBRR]		= { 0x01,  8 },			[SCSCR]		= { 0x02,  8 },			[SCxTDR]	= { 0x03,  8 },			[SCxSR]		= { 0x04,  8 },			[SCxRDR]	= { 0x05,  8 },		},		.fifosize = 1,		.overrun_reg = SCxSR,		.overrun_mask = SCI_ORER,		.sampling_rate_mask = SCI_SR(32),		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,		.param_bits = &sci_sci_port_params_bits,		.common_regs = &sci_common_regs,	}, 	/*	 * Common definitions for legacy IrDA ports.	 */	[SCIx_IRDA_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00,  8 },			[SCBRR]		= { 0x02,  8 },			[SCSCR]		= { 0x04,  8 },			[SCxTDR]	= { 0x06,  8 },			[SCxSR]		= { 0x08, 16 },			[SCxRDR]	= { 0x0a,  8 },			[SCFCR]		= { 0x0c,  8 },			[SCFDR]		= { 0x0e, 16 },		},		.fifosize = 1,		.overrun_reg = SCxSR,		.overrun_mask = SCI_ORER,		.sampling_rate_mask = SCI_SR(32),		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,		.param_bits = &sci_scif_port_params_bits,		.common_regs = &sci_common_regs,	}, 	/*	 * Common SCIFA definitions.	 */	[SCIx_SCIFA_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00, 16 },			[SCBRR]		= { 0x04,  8 },			[SCSCR]		= { 0x08, 16 },			[SCxTDR]	= { 0x20,  8 },			[SCxSR]		= { 0x14, 16 },			[SCxRDR]	= { 0x24,  8 },			[SCFCR]		= { 0x18, 16 },			[SCFDR]		= { 0x1c, 16 },			[SCPCR]		= { 0x30, 16 },			[SCPDR]		= { 0x34, 16 },		},		.fifosize = 64,		.overrun_reg = SCxSR,		.overrun_mask = SCIFA_ORER,		.sampling_rate_mask = SCI_SR_SCIFAB,		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,		.param_bits = &sci_scif_port_params_bits,		.common_regs = &sci_common_regs,	}, 	/*	 * Common SCIFB definitions.	 */	[SCIx_SCIFB_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00, 16 },			[SCBRR]		= { 0x04,  8 },			[SCSCR]		= { 0x08, 16 },			[SCxTDR]	= { 0x40,  8 },			[SCxSR]		= { 0x14, 16 },			[SCxRDR]	= { 0x60,  8 },			[SCFCR]		= { 0x18, 16 },			[SCTFDR]	= { 0x38, 16 },			[SCRFDR]	= { 0x3c, 16 },			[SCPCR]		= { 0x30, 16 },			[SCPDR]		= { 0x34, 16 },		},		.fifosize = 256,		.overrun_reg = SCxSR,		.overrun_mask = SCIFA_ORER,		.sampling_rate_mask = SCI_SR_SCIFAB,		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,		.param_bits = &sci_scif_port_params_bits,		.common_regs = &sci_common_regs,	}, 	/*	 * Common SH-2(A) SCIF definitions for ports with FIFO data	 * count registers.	 */	[SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00, 16 },			[SCBRR]		= { 0x04,  8 },			[SCSCR]		= { 0x08, 16 },			[SCxTDR]	= { 0x0c,  8 },			[SCxSR]		= { 0x10, 16 },			[SCxRDR]	= { 0x14,  8 },			[SCFCR]		= { 0x18, 16 },			[SCFDR]		= { 0x1c, 16 },			[SCSPTR]	= { 0x20, 16 },			[SCLSR]		= { 0x24, 16 },		},		.fifosize = 16,		.overrun_reg = SCLSR,		.overrun_mask = SCLSR_ORER,		.sampling_rate_mask = SCI_SR(32),		.error_mask = SCIF_DEFAULT_ERROR_MASK,		.error_clear = SCIF_ERROR_CLEAR,		.param_bits = &sci_scif_port_params_bits,		.common_regs = &sci_common_regs,	}, 	/*	 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.	 * It looks like a normal SCIF with FIFO data, but with a	 * compressed address space. Also, the break out of interrupts	 * are different: ERI/BRI, RXI, TXI, TEI, DRI.	 */	[SCIx_RZ_SCIFA_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00, 16 },			[SCBRR]		= { 0x02,  8 },			[SCSCR]		= { 0x04, 16 },			[SCxTDR]	= { 0x06,  8 },			[SCxSR]		= { 0x08, 16 },			[SCxRDR]	= { 0x0A,  8 },			[SCFCR]		= { 0x0C, 16 },			[SCFDR]		= { 0x0E, 16 },			[SCSPTR]	= { 0x10, 16 },			[SCLSR]		= { 0x12, 16 },			[SEMR]		= { 0x14, 8 },		},		.fifosize = 16,		.overrun_reg = SCLSR,		.overrun_mask = SCLSR_ORER,		.sampling_rate_mask = SCI_SR(32),		.error_mask = SCIF_DEFAULT_ERROR_MASK,		.error_clear = SCIF_ERROR_CLEAR,		.param_bits = &sci_scif_port_params_bits,		.common_regs = &sci_common_regs,	}, 	/*	 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC	 * with below differences,	 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,	 *   TEI-DRI, RXI-EDGE and TXI-EDGE.	 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.	 * - SCFCR register does not have SCFCR_MCE bit.	 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.	 */	[SCIx_RZV2H_SCIF_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00, 16 },			[SCBRR]		= { 0x02,  8 },			[SCSCR]		= { 0x04, 16 },			[SCxTDR]	= { 0x06,  8 },			[SCxSR]		= { 0x08, 16 },			[SCxRDR]	= { 0x0a,  8 },			[SCFCR]		= { 0x0c, 16 },			[SCFDR]		= { 0x0e, 16 },			[SCSPTR]	= { 0x10, 16 },			[SCLSR]		= { 0x12, 16 },			[SEMR]		= { 0x14, 8 },		},		.fifosize = 16,		.overrun_reg = SCLSR,		.overrun_mask = SCLSR_ORER,		.sampling_rate_mask = SCI_SR(32),		.error_mask = SCIF_DEFAULT_ERROR_MASK,		.error_clear = SCIF_ERROR_CLEAR,		.param_bits = &sci_scif_port_params_bits,		.common_regs = &sci_common_regs,	}, 	/*	 * Common SH-3 SCIF definitions.	 */	[SCIx_SH3_SCIF_REGTYPE] = {		.regs = {			[SCSMR]		= { 0x00,  8 },			[SCBRR]		= { 0x02,  8 },			[SCSCR]		= { 0x04,  8 },			[SCxTDR]	= { 0x06,  8 },			[SCxSR]		= { 0x08, 16 },			[SCxRDR]	= { 0x0a,  8 },			[SCFCR]		= { 0x0c,  8 },			[SCFDR]		= { 0x0e, 16 },

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