// SPDX-License-Identifier: GPL-2.0/* * uartlite.c: Serial driver for Xilinx uartlite serial controller * * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> * Copyright (C) 2007 Secret Lab Technologies Ltd. */ #include <linux/platform_device.h>#include <linux/module.h>#include <linux/bitfield.h>#include <linux/console.h>#include <linux/serial.h>#include <linux/serial_core.h>#include <linux/tty.h>#include <linux/tty_flip.h>#include <linux/delay.h>#include <linux/interrupt.h>#include <linux/init.h>#include <linux/io.h>#include <linux/iopoll.h>#include <linux/of.h>#include <linux/clk.h>#include <linux/pm_runtime.h> #define ULITE_NAME "ttyUL"#if CONFIG_SERIAL_UARTLITE_NR_UARTS > 4#define ULITE_MAJOR 0 /* use dynamic node allocation */#define ULITE_MINOR 0#else#define ULITE_MAJOR 204#define ULITE_MINOR 187#endif#define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS /* --------------------------------------------------------------------- * Register definitions * * For register details see datasheet: * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf */ #define ULITE_RX 0x00#define ULITE_TX 0x04#define ULITE_STATUS 0x08#define ULITE_CONTROL 0x0c #define ULITE_REGION 16 #define ULITE_STATUS_RXVALID 0x01#define ULITE_STATUS_RXFULL 0x02#define ULITE_STATUS_TXEMPTY 0x04#define ULITE_STATUS_TXFULL 0x08#define ULITE_STATUS_IE 0x10#define ULITE_STATUS_OVERRUN 0x20#define ULITE_STATUS_FRAME 0x40#define ULITE_STATUS_PARITY 0x80 #define ULITE_CONTROL_RST_TX 0x01#define ULITE_CONTROL_RST_RX 0x02#define ULITE_CONTROL_IE 0x10#define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */ /* Static pointer to console port */#ifdef CONFIG_SERIAL_UARTLITE_CONSOLEstatic struct uart_port *console_port;#endif /** * struct uartlite_data - Driver private data * @reg_ops: Functions to read/write registers * @clk: Our parent clock, if present * @baud: The baud rate configured when this device was synthesized * @cflags: The cflags for parity and data bits */struct uartlite_data { const struct uartlite_reg_ops *reg_ops; struct clk *clk; unsigned int baud; tcflag_t cflags;}; struct uartlite_reg_ops { u32 (*in)(void __iomem *addr); void (*out)(u32 val, void __iomem *addr);}; static u32 uartlite_inbe32(void __iomem *addr){ return ioread32be(addr);} static void uartlite_outbe32(u32 val, void __iomem *addr){ iowrite32be(val, addr);} static const struct uartlite_reg_ops uartlite_be = { .in = uartlite_inbe32, .out = uartlite_outbe32,}; static u32 uartlite_inle32(void __iomem *addr){ return ioread32(addr);} static void uartlite_outle32(u32 val, void __iomem *addr){ iowrite32(val, addr);} static const struct uartlite_reg_ops uartlite_le = { .in = uartlite_inle32, .out = uartlite_outle32,}; static inline u32 uart_in32(u32 offset, struct uart_port *port){ struct uartlite_data *pdata = port->private_data; return pdata->reg_ops->in(port->membase + offset);} static inline void uart_out32(u32 val, u32 offset, struct uart_port *port){ struct uartlite_data *pdata = port->private_data; pdata->reg_ops->out(val, port->membase + offset);} static struct uart_port ulite_ports[ULITE_NR_UARTS]; static struct uart_driver ulite_uart_driver; /* --------------------------------------------------------------------- * Core UART driver operations */ static int ulite_receive(struct uart_port *port, int stat){ struct tty_port *tport = &port->state->port; unsigned char ch = 0; char flag = TTY_NORMAL; if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN | ULITE_STATUS_FRAME)) == 0) return 0; /* stats */ if (stat & ULITE_STATUS_RXVALID) { port->icount.rx++; ch = uart_in32(ULITE_RX, port); if (stat & ULITE_STATUS_PARITY) port->icount.parity++; } if (stat & ULITE_STATUS_OVERRUN) port->icount.overrun++; if (stat & ULITE_STATUS_FRAME) port->icount.frame++; /* drop byte with parity error if IGNPAR specificed */ if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) stat &= ~ULITE_STATUS_RXVALID; stat &= port->read_status_mask; if (stat & ULITE_STATUS_PARITY) flag = TTY_PARITY; stat &= ~port->ignore_status_mask; if (stat & ULITE_STATUS_RXVALID) tty_insert_flip_char(tport, ch, flag); if (stat & ULITE_STATUS_FRAME) tty_insert_flip_char(tport, 0, TTY_FRAME); if (stat & ULITE_STATUS_OVERRUN) tty_insert_flip_char(tport, 0, TTY_OVERRUN); return 1;} static int ulite_transmit(struct uart_port *port, int stat){ struct tty_port *tport = &port->state->port; unsigned char ch; if (stat & ULITE_STATUS_TXFULL) return 0; if (port->x_char) { uart_out32(port->x_char, ULITE_TX, port); port->x_char = 0; port->icount.tx++; return 1; } if (uart_tx_stopped(port)) return 0; if (!uart_fifo_get(port, &ch)) return 0; uart_out32(ch, ULITE_TX, port); /* wake up */ if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) uart_write_wakeup(port); return 1;} static irqreturn_t ulite_isr(int irq, void *dev_id){ struct uart_port *port = dev_id; int stat, busy, n = 0; unsigned long flags; do { uart_port_lock_irqsave(port, &flags); stat = uart_in32(ULITE_STATUS, port); busy = ulite_receive(port, stat); busy |= ulite_transmit(port, stat); uart_port_unlock_irqrestore(port, flags); n++; } while (busy); /* work done? */ if (n > 1) { tty_flip_buffer_push(&port->state->port); return IRQ_HANDLED; } else { return IRQ_NONE; }} static unsigned int ulite_tx_empty(struct uart_port *port){ unsigned long flags; unsigned int ret; uart_port_lock_irqsave(port, &flags); ret = uart_in32(ULITE_STATUS, port); uart_port_unlock_irqrestore(port, flags); return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;} static unsigned int ulite_get_mctrl(struct uart_port *port){ return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;} static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl){ /* N/A */} static void ulite_stop_tx(struct uart_port *port){ /* N/A */} static void ulite_start_tx(struct uart_port *port){ ulite_transmit(port, uart_in32(ULITE_STATUS, port));} static void ulite_stop_rx(struct uart_port *port){ /* don't forward any more data (like !CREAD) */ port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;} static void ulite_break_ctl(struct uart_port *port, int ctl){ /* N/A */} static int ulite_startup(struct uart_port *port){ struct uartlite_data *pdata = port->private_data; int ret; ret = clk_enable(pdata->clk); if (ret) { dev_err(port->dev, "Failed to enable clock\n"); return ret; } ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, "uartlite", port); if (ret) return ret; uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); return 0;} static void ulite_shutdown(struct uart_port *port){ struct uartlite_data *pdata = port->private_data; uart_out32(0, ULITE_CONTROL, port); uart_in32(ULITE_CONTROL, port); /* dummy */ free_irq(port->irq, port); clk_disable(pdata->clk);} static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, const struct ktermios *old){ unsigned long flags; struct uartlite_data *pdata = port->private_data; /* Set termios to what the hardware supports */ termios->c_iflag &= ~BRKINT; termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE); termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE); tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud); uart_port_lock_irqsave(port, &flags); port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN | ULITE_STATUS_TXFULL; if (termios->c_iflag & INPCK) port->read_status_mask |= ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; port->ignore_status_mask = 0; if (termios->c_iflag & IGNPAR) port->ignore_status_mask |= ULITE_STATUS_PARITY | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; /* ignore all characters if CREAD is not set */ if ((termios->c_cflag & CREAD) == 0) port->ignore_status_mask |= ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; /* update timeout */ uart_update_timeout(port, termios->c_cflag, pdata->baud); uart_port_unlock_irqrestore(port, flags);} static const char *ulite_type(struct uart_port *port){ return port->type == PORT_UARTLITE ? "uartlite" : NULL;} static void ulite_release_port(struct uart_port *port){ release_mem_region(port->mapbase, ULITE_REGION); iounmap(port->membase); port->membase = NULL;} static int ulite_request_port(struct uart_port *port){ struct uartlite_data *pdata = port->private_data; int ret; pr_debug("ulite console: port=%p; port->mapbase=%llx\n", port, (unsigned long long) port->mapbase); if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { dev_err(port->dev, "Memory region busy\n"); return -EBUSY; } port->membase = ioremap(port->mapbase, ULITE_REGION); if (!port->membase) { dev_err(port->dev, "Unable to map registers\n"); release_mem_region(port->mapbase, ULITE_REGION); return -EBUSY; } pdata->reg_ops = &uartlite_be; ret = uart_in32(ULITE_CONTROL, port); uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); ret = uart_in32(ULITE_STATUS, port); /* Endianess detection */ if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) pdata->reg_ops = &uartlite_le; return 0;} static void ulite_config_port(struct uart_port *port, int flags){ if (!ulite_request_port(port)) port->type = PORT_UARTLITE;} static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser){ /* we don't want the core code to modify any port params */ return -EINVAL;} static void ulite_pm(struct uart_port *port, unsigned int state, unsigned int oldstate){ int ret; if (!state) { ret = pm_runtime_get_sync(port->dev); if (ret < 0) dev_err(port->dev, "Failed to enable clocks\n"); } else { pm_runtime_mark_last_busy(port->dev); pm_runtime_put_autosuspend(port->dev); }} #ifdef CONFIG_CONSOLE_POLLstatic int ulite_get_poll_char(struct uart_port *port){ if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) return NO_POLL_CHAR; return uart_in32(ULITE_RX, port);} static void ulite_put_poll_char(struct uart_port *port, unsigned char ch){ while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) cpu_relax(); /* write char to device */ uart_out32(ch, ULITE_TX, port);}#endif static const struct uart_ops ulite_ops = { .tx_empty = ulite_tx_empty, .set_mctrl = ulite_set_mctrl, .get_mctrl = ulite_get_mctrl, .stop_tx = ulite_stop_tx, .start_tx = ulite_start_tx, .stop_rx = ulite_stop_rx, .break_ctl = ulite_break_ctl, .startup = ulite_startup, .shutdown = ulite_shutdown, .set_termios = ulite_set_termios, .type = ulite_type, .release_port = ulite_release_port, .request_port = ulite_request_port, .config_port = ulite_config_port, .verify_port = ulite_verify_port, .pm = ulite_pm,#ifdef CONFIG_CONSOLE_POLL .poll_get_char = ulite_get_poll_char, .poll_put_char = ulite_put_poll_char,#endif}; /* --------------------------------------------------------------------- * Console driver operations */ #ifdef CONFIG_SERIAL_UARTLITE_CONSOLEstatic void ulite_console_wait_tx(struct uart_port *port){ u8 val; /* * Spin waiting for TX fifo to have space available. * When using the Microblaze Debug Module this can take up to 1s */ if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL), 0, 1000000, false, ULITE_STATUS, port)) dev_warn(port->dev, "timeout waiting for TX buffer empty\n");} static void ulite_console_putchar(struct uart_port *port, unsigned char ch){ ulite_console_wait_tx(port); uart_out32(ch, ULITE_TX, port);} static void ulite_console_write(struct console *co, const char *s, unsigned int count){ struct uart_port *port = console_port;Lines 1–500 of 949. Load more
// SPDX-License-Identifier: GPL-2.0 /* * uartlite.c: Serial driver for Xilinx uartlite serial controller * * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> * Copyright (C) 2007 Secret Lab Technologies Ltd. */ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/bitfield.h> #include <linux/console.h> #include <linux/serial.h> #include <linux/serial_core.h> #include <linux/tty.h> #include <linux/tty_flip.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/of.h> #include <linux/clk.h> #include <linux/pm_runtime.h> #define ULITE_NAME "ttyUL" #if CONFIG_SERIAL_UARTLITE_NR_UARTS > 4 #define ULITE_MAJOR 0 /* use dynamic node allocation */ #define ULITE_MINOR 0 #else #define ULITE_MAJOR 204 #define ULITE_MINOR 187 #endif #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS /* --------------------------------------------------------------------- * Register definitions * * For register details see datasheet: * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf */ #define ULITE_RX 0x00 #define ULITE_TX 0x04 #define ULITE_STATUS 0x08 #define ULITE_CONTROL 0x0c #define ULITE_REGION 16 #define ULITE_STATUS_RXVALID 0x01 #define ULITE_STATUS_RXFULL 0x02 #define ULITE_STATUS_TXEMPTY 0x04 #define ULITE_STATUS_TXFULL 0x08 #define ULITE_STATUS_IE 0x10 #define ULITE_STATUS_OVERRUN 0x20 #define ULITE_STATUS_FRAME 0x40 #define ULITE_STATUS_PARITY 0x80 #define ULITE_CONTROL_RST_TX 0x01 #define ULITE_CONTROL_RST_RX 0x02 #define ULITE_CONTROL_IE 0x10 #define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */ /* Static pointer to console port */ #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE static struct uart_port *console_port; #endif /** * struct uartlite_data - Driver private data * @reg_ops: Functions to read/write registers * @clk: Our parent clock, if present * @baud: The baud rate configured when this device was synthesized * @cflags: The cflags for parity and data bits */ struct uartlite_data { const struct uartlite_reg_ops *reg_ops; struct clk *clk; unsigned int baud; tcflag_t cflags; }; struct uartlite_reg_ops { u32 (*in)(void __iomem *addr); void (*out)(u32 val, void __iomem *addr); }; static u32 uartlite_inbe32(void __iomem *addr) { return ioread32be(addr); } static void uartlite_outbe32(u32 val, void __iomem *addr) { iowrite32be(val, addr); } static const struct uartlite_reg_ops uartlite_be = { .in = uartlite_inbe32, .out = uartlite_outbe32, }; static u32 uartlite_inle32(void __iomem *addr) { return ioread32(addr); } static void uartlite_outle32(u32 val, void __iomem *addr) { iowrite32(val, addr); } static const struct uartlite_reg_ops uartlite_le = { .in = uartlite_inle32, .out = uartlite_outle32, }; static inline u32 uart_in32(u32 offset, struct uart_port *port) { struct uartlite_data *pdata = port->private_data; return pdata->reg_ops->in(port->membase + offset); } static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) { struct uartlite_data *pdata = port->private_data; pdata->reg_ops->out(val, port->membase + offset); } static struct uart_port ulite_ports[ULITE_NR_UARTS]; static struct uart_driver ulite_uart_driver; /* --------------------------------------------------------------------- * Core UART driver operations */ static int ulite_receive(struct uart_port *port, int stat) { struct tty_port *tport = &port->state->port; unsigned char ch = 0; char flag = TTY_NORMAL; if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN | ULITE_STATUS_FRAME)) == 0) return 0; /* stats */ if (stat & ULITE_STATUS_RXVALID) { port->icount.rx++; ch = uart_in32(ULITE_RX, port); if (stat & ULITE_STATUS_PARITY) port->icount.parity++; } if (stat & ULITE_STATUS_OVERRUN) port->icount.overrun++; if (stat & ULITE_STATUS_FRAME) port->icount.frame++; /* drop byte with parity error if IGNPAR specificed */ if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) stat &= ~ULITE_STATUS_RXVALID; stat &= port->read_status_mask; if (stat & ULITE_STATUS_PARITY) flag = TTY_PARITY; stat &= ~port->ignore_status_mask; if (stat & ULITE_STATUS_RXVALID) tty_insert_flip_char(tport, ch, flag); if (stat & ULITE_STATUS_FRAME) tty_insert_flip_char(tport, 0, TTY_FRAME); if (stat & ULITE_STATUS_OVERRUN) tty_insert_flip_char(tport, 0, TTY_OVERRUN); return 1; } static int ulite_transmit(struct uart_port *port, int stat) { struct tty_port *tport = &port->state->port; unsigned char ch; if (stat & ULITE_STATUS_TXFULL) return 0; if (port->x_char) { uart_out32(port->x_char, ULITE_TX, port); port->x_char = 0; port->icount.tx++; return 1; } if (uart_tx_stopped(port)) return 0; if (!uart_fifo_get(port, &ch)) return 0; uart_out32(ch, ULITE_TX, port); /* wake up */ if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) uart_write_wakeup(port); return 1; } static irqreturn_t ulite_isr(int irq, void *dev_id) { struct uart_port *port = dev_id; int stat, busy, n = 0; unsigned long flags; do { uart_port_lock_irqsave(port, &flags); stat = uart_in32(ULITE_STATUS, port); busy = ulite_receive(port, stat); busy |= ulite_transmit(port, stat); uart_port_unlock_irqrestore(port, flags); n++; } while (busy); /* work done? */ if (n > 1) { tty_flip_buffer_push(&port->state->port); return IRQ_HANDLED; } else { return IRQ_NONE; } } static unsigned int ulite_tx_empty(struct uart_port *port) { unsigned long flags; unsigned int ret; uart_port_lock_irqsave(port, &flags); ret = uart_in32(ULITE_STATUS, port); uart_port_unlock_irqrestore(port, flags); return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; } static unsigned int ulite_get_mctrl(struct uart_port *port) { return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; } static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) { /* N/A */ } static void ulite_stop_tx(struct uart_port *port) { /* N/A */ } static void ulite_start_tx(struct uart_port *port) { ulite_transmit(port, uart_in32(ULITE_STATUS, port)); } static void ulite_stop_rx(struct uart_port *port) { /* don't forward any more data (like !CREAD) */ port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; } static void ulite_break_ctl(struct uart_port *port, int ctl) { /* N/A */ } static int ulite_startup(struct uart_port *port) { struct uartlite_data *pdata = port->private_data; int ret; ret = clk_enable(pdata->clk); if (ret) { dev_err(port->dev, "Failed to enable clock\n"); return ret; } ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, "uartlite", port); if (ret) return ret; uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); return 0; } static void ulite_shutdown(struct uart_port *port) { struct uartlite_data *pdata = port->private_data; uart_out32(0, ULITE_CONTROL, port); uart_in32(ULITE_CONTROL, port); /* dummy */ free_irq(port->irq, port); clk_disable(pdata->clk); } static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, const struct ktermios *old) { unsigned long flags; struct uartlite_data *pdata = port->private_data; /* Set termios to what the hardware supports */ termios->c_iflag &= ~BRKINT; termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE); termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE); tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud); uart_port_lock_irqsave(port, &flags); port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN | ULITE_STATUS_TXFULL; if (termios->c_iflag & INPCK) port->read_status_mask |= ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; port->ignore_status_mask = 0; if (termios->c_iflag & IGNPAR) port->ignore_status_mask |= ULITE_STATUS_PARITY | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; /* ignore all characters if CREAD is not set */ if ((termios->c_cflag & CREAD) == 0) port->ignore_status_mask |= ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; /* update timeout */ uart_update_timeout(port, termios->c_cflag, pdata->baud); uart_port_unlock_irqrestore(port, flags); } static const char *ulite_type(struct uart_port *port) { return port->type == PORT_UARTLITE ? "uartlite" : NULL; } static void ulite_release_port(struct uart_port *port) { release_mem_region(port->mapbase, ULITE_REGION); iounmap(port->membase); port->membase = NULL; } static int ulite_request_port(struct uart_port *port) { struct uartlite_data *pdata = port->private_data; int ret; pr_debug("ulite console: port=%p; port->mapbase=%llx\n", port, (unsigned long long) port->mapbase); if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { dev_err(port->dev, "Memory region busy\n"); return -EBUSY; } port->membase = ioremap(port->mapbase, ULITE_REGION); if (!port->membase) { dev_err(port->dev, "Unable to map registers\n"); release_mem_region(port->mapbase, ULITE_REGION); return -EBUSY; } pdata->reg_ops = &uartlite_be; ret = uart_in32(ULITE_CONTROL, port); uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); ret = uart_in32(ULITE_STATUS, port); /* Endianess detection */ if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) pdata->reg_ops = &uartlite_le; return 0; } static void ulite_config_port(struct uart_port *port, int flags) { if (!ulite_request_port(port)) port->type = PORT_UARTLITE; } static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) { /* we don't want the core code to modify any port params */ return -EINVAL; } static void ulite_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) { int ret; if (!state) { ret = pm_runtime_get_sync(port->dev); if (ret < 0) dev_err(port->dev, "Failed to enable clocks\n"); } else { pm_runtime_mark_last_busy(port->dev); pm_runtime_put_autosuspend(port->dev); } } #ifdef CONFIG_CONSOLE_POLL static int ulite_get_poll_char(struct uart_port *port) { if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) return NO_POLL_CHAR; return uart_in32(ULITE_RX, port); } static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) { while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) cpu_relax(); /* write char to device */ uart_out32(ch, ULITE_TX, port); } #endif static const struct uart_ops ulite_ops = { .tx_empty = ulite_tx_empty, .set_mctrl = ulite_set_mctrl, .get_mctrl = ulite_get_mctrl, .stop_tx = ulite_stop_tx, .start_tx = ulite_start_tx, .stop_rx = ulite_stop_rx, .break_ctl = ulite_break_ctl, .startup = ulite_startup, .shutdown = ulite_shutdown, .set_termios = ulite_set_termios, .type = ulite_type, .release_port = ulite_release_port, .request_port = ulite_request_port, .config_port = ulite_config_port, .verify_port = ulite_verify_port, .pm = ulite_pm, #ifdef CONFIG_CONSOLE_POLL .poll_get_char = ulite_get_poll_char, .poll_put_char = ulite_put_poll_char, #endif }; /* --------------------------------------------------------------------- * Console driver operations */ #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE static void ulite_console_wait_tx(struct uart_port *port) { u8 val; /* * Spin waiting for TX fifo to have space available. * When using the Microblaze Debug Module this can take up to 1s */ if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL), 0, 1000000, false, ULITE_STATUS, port)) dev_warn(port->dev, "timeout waiting for TX buffer empty\n"); } static void ulite_console_putchar(struct uart_port *port, unsigned char ch) { ulite_console_wait_tx(port); uart_out32(ch, ULITE_TX, port); } static void ulite_console_write(struct console *co, const char *s, unsigned int count) { struct uart_port *port = console_port;