// SPDX-License-Identifier: GPL-2.0/* * Freescale QUICC Engine UART device driver * * Author: Timur Tabi <timur@freescale.com> * * Copyright 2007 Freescale Semiconductor, Inc. * * This driver adds support for UART devices via Freescale's QUICC Engine * found on some Freescale SOCs. * * If Soft-UART support is needed but not already present, then this driver * will request and upload the "Soft-UART" microcode upon probe. The * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X" * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC, * (e.g. "11" for 1.1). */ #include <linux/module.h>#include <linux/platform_device.h>#include <linux/serial.h>#include <linux/serial_core.h>#include <linux/slab.h>#include <linux/tty.h>#include <linux/tty_flip.h>#include <linux/io.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/of_irq.h>#include <linux/dma-mapping.h> #include <soc/fsl/qe/ucc_slow.h> #include <linux/firmware.h>#include <soc/fsl/cpm.h> #ifdef CONFIG_PPC32#include <asm/reg.h> /* mfspr, SPRN_SVR */#endif /* * The GUMR flag for Soft UART. This would normally be defined in qe.h, * but Soft-UART is a hack and we want to keep everything related to it in * this file. */#define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ /* * soft_uart is 1 if we need to use Soft-UART mode */static int soft_uart;/* * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise. */static int firmware_loaded; /* Enable this macro to configure all serial ports in internal loopback mode *//* #define LOOPBACK */ /* The major and minor device numbers are defined in * Documentation/admin-guide/devices.txt. For the QE * UART, we have major number 204 and minor numbers 46 - 49, which are the * same as for the CPM2. This decision was made because no Freescale part * has both a CPM and a QE. */#define SERIAL_QE_MAJOR 204#define SERIAL_QE_MINOR 46 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */#define UCC_MAX_UART 4 /* The number of buffer descriptors for receiving characters. */#define RX_NUM_FIFO 4 /* The number of buffer descriptors for transmitting characters. */#define TX_NUM_FIFO 4 /* The maximum size of the character buffer for a single RX BD. */#define RX_BUF_SIZE 32 /* The maximum size of the character buffer for a single TX BD. */#define TX_BUF_SIZE 32 /* * The number of jiffies to wait after receiving a close command before the * device is actually closed. This allows the last few characters to be * sent over the wire. */#define UCC_WAIT_CLOSING 100 struct ucc_uart_pram { struct ucc_slow_pram common; u8 res1[8]; /* reserved */ __be16 maxidl; /* Maximum idle chars */ __be16 idlc; /* temp idle counter */ __be16 brkcr; /* Break count register */ __be16 parec; /* receive parity error counter */ __be16 frmec; /* receive framing error counter */ __be16 nosec; /* receive noise counter */ __be16 brkec; /* receive break condition counter */ __be16 brkln; /* last received break length */ __be16 uaddr[2]; /* UART address character 1 & 2 */ __be16 rtemp; /* Temp storage */ __be16 toseq; /* Transmit out of sequence char */ __be16 cchars[8]; /* control characters 1-8 */ __be16 rccm; /* receive control character mask */ __be16 rccr; /* receive control character register */ __be16 rlbc; /* receive last break character */ __be16 res2; /* reserved */ __be32 res3; /* reserved, should be cleared */ u8 res4; /* reserved, should be cleared */ u8 res5[3]; /* reserved, should be cleared */ __be32 res6; /* reserved, should be cleared */ __be32 res7; /* reserved, should be cleared */ __be32 res8; /* reserved, should be cleared */ __be32 res9; /* reserved, should be cleared */ __be32 res10; /* reserved, should be cleared */ __be32 res11; /* reserved, should be cleared */ __be32 res12; /* reserved, should be cleared */ __be32 res13; /* reserved, should be cleared *//* The rest is for Soft-UART only */ __be16 supsmr; /* 0x90, Shadow UPSMR */ __be16 res92; /* 0x92, reserved, initialize to 0 */ __be32 rx_state; /* 0x94, RX state, initialize to 0 */ __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */ u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */ u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */ u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */ u8 res14[0xBC - 0x9F]; /* reserved */ __be32 dump_ptr; /* 0xBC, Dump pointer */ __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */ u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */ u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ __be16 tx_state; /* 0xC6, TX state */ u8 res15[0xD0 - 0xC8]; /* reserved */ __be32 resD0; /* 0xD0, reserved, initialize to 0 */ u8 resD4; /* 0xD4, reserved, initialize to 0 */ __be16 resD5; /* 0xD5, reserved, initialize to 0 */} __attribute__ ((packed)); /* SUPSMR definitions, for Soft-UART only */#define UCC_UART_SUPSMR_SL 0x8000#define UCC_UART_SUPSMR_RPM_MASK 0x6000#define UCC_UART_SUPSMR_RPM_ODD 0x0000#define UCC_UART_SUPSMR_RPM_LOW 0x2000#define UCC_UART_SUPSMR_RPM_EVEN 0x4000#define UCC_UART_SUPSMR_RPM_HIGH 0x6000#define UCC_UART_SUPSMR_PEN 0x1000#define UCC_UART_SUPSMR_TPM_MASK 0x0C00#define UCC_UART_SUPSMR_TPM_ODD 0x0000#define UCC_UART_SUPSMR_TPM_LOW 0x0400#define UCC_UART_SUPSMR_TPM_EVEN 0x0800#define UCC_UART_SUPSMR_TPM_HIGH 0x0C00#define UCC_UART_SUPSMR_FRZ 0x0100#define UCC_UART_SUPSMR_UM_MASK 0x00c0#define UCC_UART_SUPSMR_UM_NORMAL 0x0000#define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040#define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0#define UCC_UART_SUPSMR_CL_MASK 0x0030#define UCC_UART_SUPSMR_CL_8 0x0030#define UCC_UART_SUPSMR_CL_7 0x0020#define UCC_UART_SUPSMR_CL_6 0x0010#define UCC_UART_SUPSMR_CL_5 0x0000 #define UCC_UART_TX_STATE_AHDLC 0x00#define UCC_UART_TX_STATE_UART 0x01#define UCC_UART_TX_STATE_X1 0x00#define UCC_UART_TX_STATE_X16 0x80 #define UCC_UART_PRAM_ALIGNMENT 0x100 #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD#define NUM_CONTROL_CHARS 8 /* Private per-port data structure */struct uart_qe_port { struct uart_port port; struct ucc_slow __iomem *uccp; struct ucc_uart_pram __iomem *uccup; struct ucc_slow_info us_info; struct ucc_slow_private *us_private; struct device_node *np; unsigned int ucc_num; /* First ucc is 0, not 1 */ u16 rx_nrfifos; u16 rx_fifosize; u16 tx_nrfifos; u16 tx_fifosize; int wait_closing; u32 flags; struct qe_bd __iomem *rx_bd_base; struct qe_bd __iomem *rx_cur; struct qe_bd __iomem *tx_bd_base; struct qe_bd __iomem *tx_cur; unsigned char *tx_buf; unsigned char *rx_buf; void *bd_virt; /* virtual address of the BD buffers */ dma_addr_t bd_dma_addr; /* bus address of the BD buffers */ unsigned int bd_size; /* size of BD buffer space */}; static struct uart_driver ucc_uart_driver = { .owner = THIS_MODULE, .driver_name = "ucc_uart", .dev_name = "ttyQE", .major = SERIAL_QE_MAJOR, .minor = SERIAL_QE_MINOR, .nr = UCC_MAX_UART,}; /* * Virtual to physical address translation. * * Given the virtual address for a character buffer, this function returns * the physical (DMA) equivalent. */static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port){ if (likely((addr >= qe_port->bd_virt)) && (addr < (qe_port->bd_virt + qe_port->bd_size))) return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); /* something nasty happened */ printk(KERN_ERR "%s: addr=%p\n", __func__, addr); BUG(); return 0;} /* * Physical to virtual address translation. * * Given the physical (DMA) address for a character buffer, this function * returns the virtual equivalent. */static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port){ /* sanity check */ if (likely((addr >= qe_port->bd_dma_addr) && (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); /* something nasty happened */ printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr); BUG(); return NULL;} /* * Return 1 if the QE is done transmitting all buffers for this port * * This function scans each BD in sequence. If we find a BD that is not * ready (READY=1), then we return 0 indicating that the QE is still sending * data. If we reach the last BD (WRAP=1), then we know we've scanned * the entire list, and all BDs are done. */static unsigned int qe_uart_tx_empty(struct uart_port *port){ struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); struct qe_bd __iomem *bdp = qe_port->tx_bd_base; while (1) { if (ioread16be(&bdp->status) & BD_SC_READY) /* This BD is not done, so return "not done" */ return 0; if (ioread16be(&bdp->status) & BD_SC_WRAP) /* * This BD is done and it's the last one, so return * "done" */ return 1; bdp++; }} /* * Set the modem control lines * * Although the QE can control the modem control lines (e.g. CTS), we * don't need that support. This function must exist, however, otherwise * the kernel will panic. */static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl){} /* * Get the current modem control line status * * Although the QE can control the modem control lines (e.g. CTS), this * driver currently doesn't support that, so we always return Carrier * Detect, Data Set Ready, and Clear To Send. */static unsigned int qe_uart_get_mctrl(struct uart_port *port){ return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;} /* * Disable the transmit interrupt. * * Although this function is called "stop_tx", it does not actually stop * transmission of data. Instead, it tells the QE to not generate an * interrupt when the UCC is finished sending characters. */static void qe_uart_stop_tx(struct uart_port *port){ struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);} /* * Transmit as many characters to the HW as possible. * * This function will attempt to stuff of all the characters from the * kernel's transmit buffer into TX BDs. * * A return value of non-zero indicates that it successfully stuffed all * characters from the kernel buffer. * * A return value of zero indicates that there are still characters in the * kernel's buffer that have not been transmitted, but there are no more BDs * available. This function should be called again after a BD has been made * available. */static int qe_uart_tx_pump(struct uart_qe_port *qe_port){ struct qe_bd __iomem *bdp; unsigned char *p; unsigned int count; struct uart_port *port = &qe_port->port; struct tty_port *tport = &port->state->port; /* Handle xon/xoff */ if (port->x_char) { /* Pick next descriptor and fill from buffer */ bdp = qe_port->tx_cur; p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); *p++ = port->x_char; iowrite16be(1, &bdp->length); qe_setbits_be16(&bdp->status, BD_SC_READY); /* Get next BD. */ if (ioread16be(&bdp->status) & BD_SC_WRAP) bdp = qe_port->tx_bd_base; else bdp++; qe_port->tx_cur = bdp; port->icount.tx++; port->x_char = 0; return 1; } if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { qe_uart_stop_tx(port); return 0; } /* Pick next descriptor and fill from buffer */ bdp = qe_port->tx_cur; while (!(ioread16be(&bdp->status) & BD_SC_READY) && !kfifo_is_empty(&tport->xmit_fifo)) { p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); count = uart_fifo_out(port, p, qe_port->tx_fifosize); iowrite16be(count, &bdp->length); qe_setbits_be16(&bdp->status, BD_SC_READY); /* Get next BD. */ if (ioread16be(&bdp->status) & BD_SC_WRAP) bdp = qe_port->tx_bd_base; else bdp++; } qe_port->tx_cur = bdp; if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) uart_write_wakeup(port); if (kfifo_is_empty(&tport->xmit_fifo)) { /* The kernel buffer is empty, so turn off TX interrupts. We don't need to be told when the QE is finished transmitting the data. */ qe_uart_stop_tx(port); return 0; } return 1;} /* * Start transmitting data * * This function will start transmitting any available data, if the port * isn't already transmitting data. */static void qe_uart_start_tx(struct uart_port *port){ struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); /* If we currently are transmitting, then just return */ if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) return; /* Otherwise, pump the port and start transmission */ if (qe_uart_tx_pump(qe_port)) qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);} /* * Stop transmitting data */static void qe_uart_stop_rx(struct uart_port *port){ struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);} /* Start or stop sending break signal * * This function controls the sending of a break signal. If break_state=1, * then we start sending a break signal. If break_state=0, then we stop * sending the break signal. */static void qe_uart_break_ctl(struct uart_port *port, int break_state){ struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); if (break_state) ucc_slow_stop_tx(qe_port->us_private); else ucc_slow_restart_tx(qe_port->us_private);} /* ISR helper function for receiving character. * * This function is called by the ISR to handling receiving characters */static void qe_uart_int_rx(struct uart_qe_port *qe_port){ int i; unsigned char ch, *cp; struct uart_port *port = &qe_port->port; struct tty_port *tport = &port->state->port; struct qe_bd __iomem *bdp; u16 status; unsigned int flg; /* Just loop through the closed BDs and copy the characters into * the buffer. */ bdp = qe_port->rx_cur; while (1) { status = ioread16be(&bdp->status); /* If this one is empty, then we assume we've read them all */ if (status & BD_SC_EMPTY) break; /* get number of characters, and check space in RX buffer */ i = ioread16be(&bdp->length); /* If we don't have enough room in RX buffer for the entire BD, * then we try later, which will be the next RX interrupt. */ if (tty_buffer_request_room(tport, i) < i) { dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); return; } /* get pointer */ cp = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); /* loop through the buffer */ while (i-- > 0) { ch = *cp++; port->icount.rx++; flg = TTY_NORMAL; if (!i && status & (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) goto handle_error; if (uart_handle_sysrq_char(port, ch)) continue; error_return: tty_insert_flip_char(tport, ch, flg); Lines 1–500 of 1531. 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// SPDX-License-Identifier: GPL-2.0 /* * Freescale QUICC Engine UART device driver * * Author: Timur Tabi <timur@freescale.com> * * Copyright 2007 Freescale Semiconductor, Inc. * * This driver adds support for UART devices via Freescale's QUICC Engine * found on some Freescale SOCs. * * If Soft-UART support is needed but not already present, then this driver * will request and upload the "Soft-UART" microcode upon probe. The * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X" * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC, * (e.g. "11" for 1.1). */ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/serial.h> #include <linux/serial_core.h> #include <linux/slab.h> #include <linux/tty.h> #include <linux/tty_flip.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/dma-mapping.h> #include <soc/fsl/qe/ucc_slow.h> #include <linux/firmware.h> #include <soc/fsl/cpm.h> #ifdef CONFIG_PPC32 #include <asm/reg.h> /* mfspr, SPRN_SVR */ #endif /* * The GUMR flag for Soft UART. This would normally be defined in qe.h, * but Soft-UART is a hack and we want to keep everything related to it in * this file. */ #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ /* * soft_uart is 1 if we need to use Soft-UART mode */ static int soft_uart; /* * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise. */ static int firmware_loaded; /* Enable this macro to configure all serial ports in internal loopback mode */ /* #define LOOPBACK */ /* The major and minor device numbers are defined in * Documentation/admin-guide/devices.txt. For the QE * UART, we have major number 204 and minor numbers 46 - 49, which are the * same as for the CPM2. This decision was made because no Freescale part * has both a CPM and a QE. */ #define SERIAL_QE_MAJOR 204 #define SERIAL_QE_MINOR 46 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */ #define UCC_MAX_UART 4 /* The number of buffer descriptors for receiving characters. */ #define RX_NUM_FIFO 4 /* The number of buffer descriptors for transmitting characters. */ #define TX_NUM_FIFO 4 /* The maximum size of the character buffer for a single RX BD. */ #define RX_BUF_SIZE 32 /* The maximum size of the character buffer for a single TX BD. */ #define TX_BUF_SIZE 32 /* * The number of jiffies to wait after receiving a close command before the * device is actually closed. This allows the last few characters to be * sent over the wire. */ #define UCC_WAIT_CLOSING 100 struct ucc_uart_pram { struct ucc_slow_pram common; u8 res1[8]; /* reserved */ __be16 maxidl; /* Maximum idle chars */ __be16 idlc; /* temp idle counter */ __be16 brkcr; /* Break count register */ __be16 parec; /* receive parity error counter */ __be16 frmec; /* receive framing error counter */ __be16 nosec; /* receive noise counter */ __be16 brkec; /* receive break condition counter */ __be16 brkln; /* last received break length */ __be16 uaddr[2]; /* UART address character 1 & 2 */ __be16 rtemp; /* Temp storage */ __be16 toseq; /* Transmit out of sequence char */ __be16 cchars[8]; /* control characters 1-8 */ __be16 rccm; /* receive control character mask */ __be16 rccr; /* receive control character register */ __be16 rlbc; /* receive last break character */ __be16 res2; /* reserved */ __be32 res3; /* reserved, should be cleared */ u8 res4; /* reserved, should be cleared */ u8 res5[3]; /* reserved, should be cleared */ __be32 res6; /* reserved, should be cleared */ __be32 res7; /* reserved, should be cleared */ __be32 res8; /* reserved, should be cleared */ __be32 res9; /* reserved, should be cleared */ __be32 res10; /* reserved, should be cleared */ __be32 res11; /* reserved, should be cleared */ __be32 res12; /* reserved, should be cleared */ __be32 res13; /* reserved, should be cleared */ /* The rest is for Soft-UART only */ __be16 supsmr; /* 0x90, Shadow UPSMR */ __be16 res92; /* 0x92, reserved, initialize to 0 */ __be32 rx_state; /* 0x94, RX state, initialize to 0 */ __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */ u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */ u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */ u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */ u8 res14[0xBC - 0x9F]; /* reserved */ __be32 dump_ptr; /* 0xBC, Dump pointer */ __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */ u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */ u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ __be16 tx_state; /* 0xC6, TX state */ u8 res15[0xD0 - 0xC8]; /* reserved */ __be32 resD0; /* 0xD0, reserved, initialize to 0 */ u8 resD4; /* 0xD4, reserved, initialize to 0 */ __be16 resD5; /* 0xD5, reserved, initialize to 0 */ } __attribute__ ((packed)); /* SUPSMR definitions, for Soft-UART only */ #define UCC_UART_SUPSMR_SL 0x8000 #define UCC_UART_SUPSMR_RPM_MASK 0x6000 #define UCC_UART_SUPSMR_RPM_ODD 0x0000 #define UCC_UART_SUPSMR_RPM_LOW 0x2000 #define UCC_UART_SUPSMR_RPM_EVEN 0x4000 #define UCC_UART_SUPSMR_RPM_HIGH 0x6000 #define UCC_UART_SUPSMR_PEN 0x1000 #define UCC_UART_SUPSMR_TPM_MASK 0x0C00 #define UCC_UART_SUPSMR_TPM_ODD 0x0000 #define UCC_UART_SUPSMR_TPM_LOW 0x0400 #define UCC_UART_SUPSMR_TPM_EVEN 0x0800 #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00 #define UCC_UART_SUPSMR_FRZ 0x0100 #define UCC_UART_SUPSMR_UM_MASK 0x00c0 #define UCC_UART_SUPSMR_UM_NORMAL 0x0000 #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040 #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0 #define UCC_UART_SUPSMR_CL_MASK 0x0030 #define UCC_UART_SUPSMR_CL_8 0x0030 #define UCC_UART_SUPSMR_CL_7 0x0020 #define UCC_UART_SUPSMR_CL_6 0x0010 #define UCC_UART_SUPSMR_CL_5 0x0000 #define UCC_UART_TX_STATE_AHDLC 0x00 #define UCC_UART_TX_STATE_UART 0x01 #define UCC_UART_TX_STATE_X1 0x00 #define UCC_UART_TX_STATE_X16 0x80 #define UCC_UART_PRAM_ALIGNMENT 0x100 #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD #define NUM_CONTROL_CHARS 8 /* Private per-port data structure */ struct uart_qe_port { struct uart_port port; struct ucc_slow __iomem *uccp; struct ucc_uart_pram __iomem *uccup; struct ucc_slow_info us_info; struct ucc_slow_private *us_private; struct device_node *np; unsigned int ucc_num; /* First ucc is 0, not 1 */ u16 rx_nrfifos; u16 rx_fifosize; u16 tx_nrfifos; u16 tx_fifosize; int wait_closing; u32 flags; struct qe_bd __iomem *rx_bd_base; struct qe_bd __iomem *rx_cur; struct qe_bd __iomem *tx_bd_base; struct qe_bd __iomem *tx_cur; unsigned char *tx_buf; unsigned char *rx_buf; void *bd_virt; /* virtual address of the BD buffers */ dma_addr_t bd_dma_addr; /* bus address of the BD buffers */ unsigned int bd_size; /* size of BD buffer space */ }; static struct uart_driver ucc_uart_driver = { .owner = THIS_MODULE, .driver_name = "ucc_uart", .dev_name = "ttyQE", .major = SERIAL_QE_MAJOR, .minor = SERIAL_QE_MINOR, .nr = UCC_MAX_UART, }; /* * Virtual to physical address translation. * * Given the virtual address for a character buffer, this function returns * the physical (DMA) equivalent. */ static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port) { if (likely((addr >= qe_port->bd_virt)) && (addr < (qe_port->bd_virt + qe_port->bd_size))) return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); /* something nasty happened */ printk(KERN_ERR "%s: addr=%p\n", __func__, addr); BUG(); return 0; } /* * Physical to virtual address translation. * * Given the physical (DMA) address for a character buffer, this function * returns the virtual equivalent. */ static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port) { /* sanity check */ if (likely((addr >= qe_port->bd_dma_addr) && (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); /* something nasty happened */ printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr); BUG(); return NULL; } /* * Return 1 if the QE is done transmitting all buffers for this port * * This function scans each BD in sequence. If we find a BD that is not * ready (READY=1), then we return 0 indicating that the QE is still sending * data. If we reach the last BD (WRAP=1), then we know we've scanned * the entire list, and all BDs are done. */ static unsigned int qe_uart_tx_empty(struct uart_port *port) { struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); struct qe_bd __iomem *bdp = qe_port->tx_bd_base; while (1) { if (ioread16be(&bdp->status) & BD_SC_READY) /* This BD is not done, so return "not done" */ return 0; if (ioread16be(&bdp->status) & BD_SC_WRAP) /* * This BD is done and it's the last one, so return * "done" */ return 1; bdp++; } } /* * Set the modem control lines * * Although the QE can control the modem control lines (e.g. CTS), we * don't need that support. This function must exist, however, otherwise * the kernel will panic. */ static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) { } /* * Get the current modem control line status * * Although the QE can control the modem control lines (e.g. CTS), this * driver currently doesn't support that, so we always return Carrier * Detect, Data Set Ready, and Clear To Send. */ static unsigned int qe_uart_get_mctrl(struct uart_port *port) { return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; } /* * Disable the transmit interrupt. * * Although this function is called "stop_tx", it does not actually stop * transmission of data. Instead, it tells the QE to not generate an * interrupt when the UCC is finished sending characters. */ static void qe_uart_stop_tx(struct uart_port *port) { struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); } /* * Transmit as many characters to the HW as possible. * * This function will attempt to stuff of all the characters from the * kernel's transmit buffer into TX BDs. * * A return value of non-zero indicates that it successfully stuffed all * characters from the kernel buffer. * * A return value of zero indicates that there are still characters in the * kernel's buffer that have not been transmitted, but there are no more BDs * available. This function should be called again after a BD has been made * available. */ static int qe_uart_tx_pump(struct uart_qe_port *qe_port) { struct qe_bd __iomem *bdp; unsigned char *p; unsigned int count; struct uart_port *port = &qe_port->port; struct tty_port *tport = &port->state->port; /* Handle xon/xoff */ if (port->x_char) { /* Pick next descriptor and fill from buffer */ bdp = qe_port->tx_cur; p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); *p++ = port->x_char; iowrite16be(1, &bdp->length); qe_setbits_be16(&bdp->status, BD_SC_READY); /* Get next BD. */ if (ioread16be(&bdp->status) & BD_SC_WRAP) bdp = qe_port->tx_bd_base; else bdp++; qe_port->tx_cur = bdp; port->icount.tx++; port->x_char = 0; return 1; } if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { qe_uart_stop_tx(port); return 0; } /* Pick next descriptor and fill from buffer */ bdp = qe_port->tx_cur; while (!(ioread16be(&bdp->status) & BD_SC_READY) && !kfifo_is_empty(&tport->xmit_fifo)) { p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); count = uart_fifo_out(port, p, qe_port->tx_fifosize); iowrite16be(count, &bdp->length); qe_setbits_be16(&bdp->status, BD_SC_READY); /* Get next BD. */ if (ioread16be(&bdp->status) & BD_SC_WRAP) bdp = qe_port->tx_bd_base; else bdp++; } qe_port->tx_cur = bdp; if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) uart_write_wakeup(port); if (kfifo_is_empty(&tport->xmit_fifo)) { /* The kernel buffer is empty, so turn off TX interrupts. We don't need to be told when the QE is finished transmitting the data. */ qe_uart_stop_tx(port); return 0; } return 1; } /* * Start transmitting data * * This function will start transmitting any available data, if the port * isn't already transmitting data. */ static void qe_uart_start_tx(struct uart_port *port) { struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); /* If we currently are transmitting, then just return */ if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) return; /* Otherwise, pump the port and start transmission */ if (qe_uart_tx_pump(qe_port)) qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); } /* * Stop transmitting data */ static void qe_uart_stop_rx(struct uart_port *port) { struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); } /* Start or stop sending break signal * * This function controls the sending of a break signal. If break_state=1, * then we start sending a break signal. If break_state=0, then we stop * sending the break signal. */ static void qe_uart_break_ctl(struct uart_port *port, int break_state) { struct uart_qe_port *qe_port = container_of(port, struct uart_qe_port, port); if (break_state) ucc_slow_stop_tx(qe_port->us_private); else ucc_slow_restart_tx(qe_port->us_private); } /* ISR helper function for receiving character. * * This function is called by the ISR to handling receiving characters */ static void qe_uart_int_rx(struct uart_qe_port *qe_port) { int i; unsigned char ch, *cp; struct uart_port *port = &qe_port->port; struct tty_port *tport = &port->state->port; struct qe_bd __iomem *bdp; u16 status; unsigned int flg; /* Just loop through the closed BDs and copy the characters into * the buffer. */ bdp = qe_port->rx_cur; while (1) { status = ioread16be(&bdp->status); /* If this one is empty, then we assume we've read them all */ if (status & BD_SC_EMPTY) break; /* get number of characters, and check space in RX buffer */ i = ioread16be(&bdp->length); /* If we don't have enough room in RX buffer for the entire BD, * then we try later, which will be the next RX interrupt. */ if (tty_buffer_request_room(tport, i) < i) { dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); return; } /* get pointer */ cp = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); /* loop through the buffer */ while (i-- > 0) { ch = *cp++; port->icount.rx++; flg = TTY_NORMAL; if (!i && status & (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) goto handle_error; if (uart_handle_sysrq_char(port, ch)) continue; error_return: tty_insert_flip_char(tport, ch, flg);