/* * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge * * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive for * more details. * * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) * which is based on the code of neofb. */ #include <linux/aperture.h>#include <linux/module.h>#include <linux/kernel.h>#include <linux/errno.h>#include <linux/string.h>#include <linux/mm.h>#include <linux/tty.h>#include <linux/delay.h>#include <linux/fb.h>#include <linux/svga.h>#include <linux/init.h>#include <linux/pci.h>#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */#include <video/vga.h> #include <linux/i2c.h>#include <linux/i2c-algo-bit.h> struct s3fb_info { int chip, rev, mclk_freq; int wc_cookie; struct vgastate state; struct mutex open_lock; unsigned int ref_count; u32 pseudo_palette[16];#ifdef CONFIG_FB_S3_DDC u8 __iomem *mmio; bool ddc_registered; struct i2c_adapter ddc_adapter; struct i2c_algo_bit_data ddc_algo;#endif}; /* ------------------------------------------------------------------------- */ static const struct svga_fb_format s3fb_formats[] = { { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, { 1, {0, 1, 0}, {0, 1, 0}, {0, 1, 0}, {0, 0, 0}, 2, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 32, 64}, { 2, {0, 2, 0}, {0, 2, 0}, {0, 2, 0}, {0, 0, 0}, 2, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 16, 32}, { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 2, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, SVGA_FORMAT_END}; static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, 35000, 240000, 14318};static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4, 230000, 460000, 14318}; static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge", "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", "S3 Virge/GX2", "S3 Virge/GX2+", "", "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", "S3 Trio3D", "S3 Virge/MX"}; #define CHIP_UNKNOWN 0x00#define CHIP_732_TRIO32 0x01#define CHIP_764_TRIO64 0x02#define CHIP_765_TRIO64VP 0x03#define CHIP_767_TRIO64UVP 0x04#define CHIP_775_TRIO64V2_DX 0x05#define CHIP_785_TRIO64V2_GX 0x06#define CHIP_551_PLATO_PX 0x07#define CHIP_M65_AURORA64VP 0x08#define CHIP_325_VIRGE 0x09#define CHIP_988_VIRGE_VX 0x0A#define CHIP_375_VIRGE_DX 0x0B#define CHIP_385_VIRGE_GX 0x0C#define CHIP_357_VIRGE_GX2 0x0D#define CHIP_359_VIRGE_GX2P 0x0E#define CHIP_360_TRIO3D_1X 0x10#define CHIP_362_TRIO3D_2X 0x11#define CHIP_368_TRIO3D_2X 0x12#define CHIP_365_TRIO3D 0x13#define CHIP_260_VIRGE_MX 0x14 #define CHIP_XXX_TRIO 0x80#define CHIP_XXX_TRIO64V2_DXGX 0x81#define CHIP_XXX_VIRGE_DXGX 0x82#define CHIP_36X_TRIO3D_1X_2X 0x83 #define CHIP_UNDECIDED_FLAG 0x80#define CHIP_MASK 0xFF #define MMIO_OFFSET 0x1000000#define MMIO_SIZE 0x10000 /* CRT timing register sets */ static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END}; static const struct svga_timing_regs s3_timing_regs = { s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,}; /* ------------------------------------------------------------------------- */ /* Module parameters */ static char *mode_option;static int mtrr = 1;static int fasttext = 1; MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");MODULE_LICENSE("GPL");MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); module_param(mode_option, charp, 0444);MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");module_param_named(mode, mode_option, charp, 0444);MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");module_param(mtrr, int, 0444);MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); module_param(fasttext, int, 0644);MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); /* ------------------------------------------------------------------------- */ #ifdef CONFIG_FB_S3_DDC #define DDC_REG 0xaa /* Trio 3D/1X/2X */#define DDC_MMIO_REG 0xff20 /* all other chips */#define DDC_SCL_OUT (1 << 0)#define DDC_SDA_OUT (1 << 1)#define DDC_SCL_IN (1 << 2)#define DDC_SDA_IN (1 << 3)#define DDC_DRIVE_EN (1 << 4) static bool s3fb_ddc_needs_mmio(int chip){ return !(chip == CHIP_360_TRIO3D_1X || chip == CHIP_362_TRIO3D_2X || chip == CHIP_368_TRIO3D_2X);} static u8 s3fb_ddc_read(struct s3fb_info *par){ if (s3fb_ddc_needs_mmio(par->chip)) return readb(par->mmio + DDC_MMIO_REG); else return vga_rcrt(par->state.vgabase, DDC_REG);} static void s3fb_ddc_write(struct s3fb_info *par, u8 val){ if (s3fb_ddc_needs_mmio(par->chip)) writeb(val, par->mmio + DDC_MMIO_REG); else vga_wcrt(par->state.vgabase, DDC_REG, val);} static void s3fb_ddc_setscl(void *data, int val){ struct s3fb_info *par = data; unsigned char reg; reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; if (val) reg |= DDC_SCL_OUT; else reg &= ~DDC_SCL_OUT; s3fb_ddc_write(par, reg);} static void s3fb_ddc_setsda(void *data, int val){ struct s3fb_info *par = data; unsigned char reg; reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; if (val) reg |= DDC_SDA_OUT; else reg &= ~DDC_SDA_OUT; s3fb_ddc_write(par, reg);} static int s3fb_ddc_getscl(void *data){ struct s3fb_info *par = data; return !!(s3fb_ddc_read(par) & DDC_SCL_IN);} static int s3fb_ddc_getsda(void *data){ struct s3fb_info *par = data; return !!(s3fb_ddc_read(par) & DDC_SDA_IN);} static int s3fb_setup_ddc_bus(struct fb_info *info){ struct s3fb_info *par = info->par; strscpy(par->ddc_adapter.name, info->fix.id, sizeof(par->ddc_adapter.name)); par->ddc_adapter.owner = THIS_MODULE; par->ddc_adapter.algo_data = &par->ddc_algo; par->ddc_adapter.dev.parent = info->device; par->ddc_algo.setsda = s3fb_ddc_setsda; par->ddc_algo.setscl = s3fb_ddc_setscl; par->ddc_algo.getsda = s3fb_ddc_getsda; par->ddc_algo.getscl = s3fb_ddc_getscl; par->ddc_algo.udelay = 10; par->ddc_algo.timeout = 20; par->ddc_algo.data = par; i2c_set_adapdata(&par->ddc_adapter, par); /* * some Virge cards have external MUX to switch chip I2C bus between * DDC and extension pins - switch it do DDC *//* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ if (par->chip == CHIP_357_VIRGE_GX2 || par->chip == CHIP_359_VIRGE_GX2P || par->chip == CHIP_260_VIRGE_MX) svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); else svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); /* some Virge need this or the DDC is ignored */ svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); return i2c_bit_add_bus(&par->ddc_adapter);}#endif /* CONFIG_FB_S3_DDC */ /* ------------------------------------------------------------------------- */ /* Set font in S3 fast text mode */ static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map){ const u8 *font = map->data; u8 __iomem *fb = (u8 __iomem *) info->screen_base; int i, c; if ((map->width != 8) || (map->height != 16) || (map->depth != 1) || (map->length != 256)) { fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", map->width, map->height, map->depth, map->length); return; } fb += 2; for (i = 0; i < map->height; i++) { for (c = 0; c < map->length; c++) { fb_writeb(font[c * map->height + i], fb + c * 4); } fb += 1024; }} static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor){ struct s3fb_info *par = info->par; svga_tilecursor(par->state.vgabase, info, cursor);} static struct fb_tile_ops s3fb_tile_ops = { .fb_settile = svga_settile, .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, .fb_tilecursor = s3fb_tilecursor, .fb_get_tilemax = svga_get_tilemax,}; static struct fb_tile_ops s3fb_fast_tile_ops = { .fb_settile = s3fb_settile_fast, .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, .fb_tilecursor = s3fb_tilecursor, .fb_get_tilemax = svga_get_tilemax,}; /* ------------------------------------------------------------------------- */ /* image data is MSB-first, fb structure is MSB-first too */static inline u32 expand_color(u32 c){ return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;} /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image){ u32 fg = expand_color(image->fg_color); u32 bg = expand_color(image->bg_color); const u8 *src1, *src; u8 __iomem *dst1; u32 __iomem *dst; u32 val; int x, y; src1 = image->data; dst1 = info->screen_base + (image->dy * info->fix.line_length) + ((image->dx / 8) * 4); for (y = 0; y < image->height; y++) { src = src1; dst = (u32 __iomem *) dst1; for (x = 0; x < image->width; x += 8) { val = *(src++) * 0x01010101; val = (val & fg) | (~val & bg); fb_writel(val, dst++); } src1 += image->width / 8; dst1 += info->fix.line_length; } } /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect){ u32 fg = expand_color(rect->color); u8 __iomem *dst1; u32 __iomem *dst; int x, y; dst1 = info->screen_base + (rect->dy * info->fix.line_length) + ((rect->dx / 8) * 4); for (y = 0; y < rect->height; y++) { dst = (u32 __iomem *) dst1; for (x = 0; x < rect->width; x += 8) { fb_writel(fg, dst++); } dst1 += info->fix.line_length; }} /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */static inline u32 expand_pixel(u32 c){ return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;} /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image){ u32 fg = image->fg_color * 0x11111111; u32 bg = image->bg_color * 0x11111111; const u8 *src1, *src; u8 __iomem *dst1; u32 __iomem *dst; u32 val; int x, y; src1 = image->data; dst1 = info->screen_base + (image->dy * info->fix.line_length) + ((image->dx / 8) * 4); for (y = 0; y < image->height; y++) { src = src1; dst = (u32 __iomem *) dst1; for (x = 0; x < image->width; x += 8) { val = expand_pixel(*(src++)); val = (val & fg) | (~val & bg); fb_writel(val, dst++); } src1 += image->width / 8; dst1 += info->fix.line_length; }} static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image){ if ((info->var.bits_per_pixel == 4) && (image->depth == 1) && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) s3fb_iplan_imageblit(info, image); else s3fb_cfb4_imageblit(info, image); } else cfb_imageblit(info, image);} static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect){ if ((info->var.bits_per_pixel == 4) && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) s3fb_iplan_fillrect(info, rect); else cfb_fillrect(info, rect);} /* ------------------------------------------------------------------------- */ static void s3_set_pixclock(struct fb_info *info, u32 pixclock){ struct s3fb_info *par = info->par; u16 m, n, r; u8 regval; int rv; rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); if (rv < 0) { fb_err(info, "cannot set requested pixclock, keeping old value\n"); return; } /* Set VGA misc register */ regval = vga_r(par->state.vgabase, VGA_MIS_R); vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); /* Set S3 clock registers */ if (par->chip == CHIP_357_VIRGE_GX2 || par->chip == CHIP_359_VIRGE_GX2P || par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || par->chip == CHIP_368_TRIO3D_2X || par->chip == CHIP_260_VIRGE_MX) { vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ } else vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); vga_wseq(par->state.vgabase, 0x13, m - 2); udelay(1000); /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));}Lines 1–500 of 1659. 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/* * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge * * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive for * more details. * * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) * which is based on the code of neofb. */ #include <linux/aperture.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/svga.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ #include <video/vga.h> #include <linux/i2c.h> #include <linux/i2c-algo-bit.h> struct s3fb_info { int chip, rev, mclk_freq; int wc_cookie; struct vgastate state; struct mutex open_lock; unsigned int ref_count; u32 pseudo_palette[16]; #ifdef CONFIG_FB_S3_DDC u8 __iomem *mmio; bool ddc_registered; struct i2c_adapter ddc_adapter; struct i2c_algo_bit_data ddc_algo; #endif }; /* ------------------------------------------------------------------------- */ static const struct svga_fb_format s3fb_formats[] = { { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, { 1, {0, 1, 0}, {0, 1, 0}, {0, 1, 0}, {0, 0, 0}, 2, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 32, 64}, { 2, {0, 2, 0}, {0, 2, 0}, {0, 2, 0}, {0, 0, 0}, 2, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 16, 32}, { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 2, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, SVGA_FORMAT_END }; static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, 35000, 240000, 14318}; static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4, 230000, 460000, 14318}; static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge", "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", "S3 Virge/GX2", "S3 Virge/GX2+", "", "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", "S3 Trio3D", "S3 Virge/MX"}; #define CHIP_UNKNOWN 0x00 #define CHIP_732_TRIO32 0x01 #define CHIP_764_TRIO64 0x02 #define CHIP_765_TRIO64VP 0x03 #define CHIP_767_TRIO64UVP 0x04 #define CHIP_775_TRIO64V2_DX 0x05 #define CHIP_785_TRIO64V2_GX 0x06 #define CHIP_551_PLATO_PX 0x07 #define CHIP_M65_AURORA64VP 0x08 #define CHIP_325_VIRGE 0x09 #define CHIP_988_VIRGE_VX 0x0A #define CHIP_375_VIRGE_DX 0x0B #define CHIP_385_VIRGE_GX 0x0C #define CHIP_357_VIRGE_GX2 0x0D #define CHIP_359_VIRGE_GX2P 0x0E #define CHIP_360_TRIO3D_1X 0x10 #define CHIP_362_TRIO3D_2X 0x11 #define CHIP_368_TRIO3D_2X 0x12 #define CHIP_365_TRIO3D 0x13 #define CHIP_260_VIRGE_MX 0x14 #define CHIP_XXX_TRIO 0x80 #define CHIP_XXX_TRIO64V2_DXGX 0x81 #define CHIP_XXX_VIRGE_DXGX 0x82 #define CHIP_36X_TRIO3D_1X_2X 0x83 #define CHIP_UNDECIDED_FLAG 0x80 #define CHIP_MASK 0xFF #define MMIO_OFFSET 0x1000000 #define MMIO_SIZE 0x10000 /* CRT timing register sets */ static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END}; static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END}; static const struct svga_timing_regs s3_timing_regs = { s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, }; /* ------------------------------------------------------------------------- */ /* Module parameters */ static char *mode_option; static int mtrr = 1; static int fasttext = 1; MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); module_param(mode_option, charp, 0444); MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); module_param_named(mode, mode_option, charp, 0444); MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); module_param(mtrr, int, 0444); MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); module_param(fasttext, int, 0644); MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); /* ------------------------------------------------------------------------- */ #ifdef CONFIG_FB_S3_DDC #define DDC_REG 0xaa /* Trio 3D/1X/2X */ #define DDC_MMIO_REG 0xff20 /* all other chips */ #define DDC_SCL_OUT (1 << 0) #define DDC_SDA_OUT (1 << 1) #define DDC_SCL_IN (1 << 2) #define DDC_SDA_IN (1 << 3) #define DDC_DRIVE_EN (1 << 4) static bool s3fb_ddc_needs_mmio(int chip) { return !(chip == CHIP_360_TRIO3D_1X || chip == CHIP_362_TRIO3D_2X || chip == CHIP_368_TRIO3D_2X); } static u8 s3fb_ddc_read(struct s3fb_info *par) { if (s3fb_ddc_needs_mmio(par->chip)) return readb(par->mmio + DDC_MMIO_REG); else return vga_rcrt(par->state.vgabase, DDC_REG); } static void s3fb_ddc_write(struct s3fb_info *par, u8 val) { if (s3fb_ddc_needs_mmio(par->chip)) writeb(val, par->mmio + DDC_MMIO_REG); else vga_wcrt(par->state.vgabase, DDC_REG, val); } static void s3fb_ddc_setscl(void *data, int val) { struct s3fb_info *par = data; unsigned char reg; reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; if (val) reg |= DDC_SCL_OUT; else reg &= ~DDC_SCL_OUT; s3fb_ddc_write(par, reg); } static void s3fb_ddc_setsda(void *data, int val) { struct s3fb_info *par = data; unsigned char reg; reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; if (val) reg |= DDC_SDA_OUT; else reg &= ~DDC_SDA_OUT; s3fb_ddc_write(par, reg); } static int s3fb_ddc_getscl(void *data) { struct s3fb_info *par = data; return !!(s3fb_ddc_read(par) & DDC_SCL_IN); } static int s3fb_ddc_getsda(void *data) { struct s3fb_info *par = data; return !!(s3fb_ddc_read(par) & DDC_SDA_IN); } static int s3fb_setup_ddc_bus(struct fb_info *info) { struct s3fb_info *par = info->par; strscpy(par->ddc_adapter.name, info->fix.id, sizeof(par->ddc_adapter.name)); par->ddc_adapter.owner = THIS_MODULE; par->ddc_adapter.algo_data = &par->ddc_algo; par->ddc_adapter.dev.parent = info->device; par->ddc_algo.setsda = s3fb_ddc_setsda; par->ddc_algo.setscl = s3fb_ddc_setscl; par->ddc_algo.getsda = s3fb_ddc_getsda; par->ddc_algo.getscl = s3fb_ddc_getscl; par->ddc_algo.udelay = 10; par->ddc_algo.timeout = 20; par->ddc_algo.data = par; i2c_set_adapdata(&par->ddc_adapter, par); /* * some Virge cards have external MUX to switch chip I2C bus between * DDC and extension pins - switch it do DDC */ /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ if (par->chip == CHIP_357_VIRGE_GX2 || par->chip == CHIP_359_VIRGE_GX2P || par->chip == CHIP_260_VIRGE_MX) svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); else svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); /* some Virge need this or the DDC is ignored */ svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); return i2c_bit_add_bus(&par->ddc_adapter); } #endif /* CONFIG_FB_S3_DDC */ /* ------------------------------------------------------------------------- */ /* Set font in S3 fast text mode */ static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) { const u8 *font = map->data; u8 __iomem *fb = (u8 __iomem *) info->screen_base; int i, c; if ((map->width != 8) || (map->height != 16) || (map->depth != 1) || (map->length != 256)) { fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", map->width, map->height, map->depth, map->length); return; } fb += 2; for (i = 0; i < map->height; i++) { for (c = 0; c < map->length; c++) { fb_writeb(font[c * map->height + i], fb + c * 4); } fb += 1024; } } static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) { struct s3fb_info *par = info->par; svga_tilecursor(par->state.vgabase, info, cursor); } static struct fb_tile_ops s3fb_tile_ops = { .fb_settile = svga_settile, .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, .fb_tilecursor = s3fb_tilecursor, .fb_get_tilemax = svga_get_tilemax, }; static struct fb_tile_ops s3fb_fast_tile_ops = { .fb_settile = s3fb_settile_fast, .fb_tilecopy = svga_tilecopy, .fb_tilefill = svga_tilefill, .fb_tileblit = svga_tileblit, .fb_tilecursor = s3fb_tilecursor, .fb_get_tilemax = svga_get_tilemax, }; /* ------------------------------------------------------------------------- */ /* image data is MSB-first, fb structure is MSB-first too */ static inline u32 expand_color(u32 c) { return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; } /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) { u32 fg = expand_color(image->fg_color); u32 bg = expand_color(image->bg_color); const u8 *src1, *src; u8 __iomem *dst1; u32 __iomem *dst; u32 val; int x, y; src1 = image->data; dst1 = info->screen_base + (image->dy * info->fix.line_length) + ((image->dx / 8) * 4); for (y = 0; y < image->height; y++) { src = src1; dst = (u32 __iomem *) dst1; for (x = 0; x < image->width; x += 8) { val = *(src++) * 0x01010101; val = (val & fg) | (~val & bg); fb_writel(val, dst++); } src1 += image->width / 8; dst1 += info->fix.line_length; } } /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { u32 fg = expand_color(rect->color); u8 __iomem *dst1; u32 __iomem *dst; int x, y; dst1 = info->screen_base + (rect->dy * info->fix.line_length) + ((rect->dx / 8) * 4); for (y = 0; y < rect->height; y++) { dst = (u32 __iomem *) dst1; for (x = 0; x < rect->width; x += 8) { fb_writel(fg, dst++); } dst1 += info->fix.line_length; } } /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ static inline u32 expand_pixel(u32 c) { return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; } /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) { u32 fg = image->fg_color * 0x11111111; u32 bg = image->bg_color * 0x11111111; const u8 *src1, *src; u8 __iomem *dst1; u32 __iomem *dst; u32 val; int x, y; src1 = image->data; dst1 = info->screen_base + (image->dy * info->fix.line_length) + ((image->dx / 8) * 4); for (y = 0; y < image->height; y++) { src = src1; dst = (u32 __iomem *) dst1; for (x = 0; x < image->width; x += 8) { val = expand_pixel(*(src++)); val = (val & fg) | (~val & bg); fb_writel(val, dst++); } src1 += image->width / 8; dst1 += info->fix.line_length; } } static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) { if ((info->var.bits_per_pixel == 4) && (image->depth == 1) && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) s3fb_iplan_imageblit(info, image); else s3fb_cfb4_imageblit(info, image); } else cfb_imageblit(info, image); } static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { if ((info->var.bits_per_pixel == 4) && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) s3fb_iplan_fillrect(info, rect); else cfb_fillrect(info, rect); } /* ------------------------------------------------------------------------- */ static void s3_set_pixclock(struct fb_info *info, u32 pixclock) { struct s3fb_info *par = info->par; u16 m, n, r; u8 regval; int rv; rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); if (rv < 0) { fb_err(info, "cannot set requested pixclock, keeping old value\n"); return; } /* Set VGA misc register */ regval = vga_r(par->state.vgabase, VGA_MIS_R); vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); /* Set S3 clock registers */ if (par->chip == CHIP_357_VIRGE_GX2 || par->chip == CHIP_359_VIRGE_GX2P || par->chip == CHIP_360_TRIO3D_1X || par->chip == CHIP_362_TRIO3D_2X || par->chip == CHIP_368_TRIO3D_2X || par->chip == CHIP_260_VIRGE_MX) { vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ } else vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); vga_wseq(par->state.vgabase, 0x13, m - 2); udelay(1000); /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); }