/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- * * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Fremont, California. * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: *    Kevin E. Martin <martin@valinux.com> *    Gareth Hughes <gareth@valinux.com> *    Keith Whitwell <keith@tungstengraphics.com> */ #ifndef __AMDGPU_DRM_H__#define __AMDGPU_DRM_H__ #include "drm.h" #if defined(__cplusplus)extern "C" {#endif #define DRM_AMDGPU_GEM_CREATE		0x00#define DRM_AMDGPU_GEM_MMAP		0x01#define DRM_AMDGPU_CTX			0x02#define DRM_AMDGPU_BO_LIST		0x03#define DRM_AMDGPU_CS			0x04#define DRM_AMDGPU_INFO			0x05#define DRM_AMDGPU_GEM_METADATA		0x06#define DRM_AMDGPU_GEM_WAIT_IDLE	0x07#define DRM_AMDGPU_GEM_VA		0x08#define DRM_AMDGPU_WAIT_CS		0x09#define DRM_AMDGPU_GEM_OP		0x10#define DRM_AMDGPU_GEM_USERPTR		0x11#define DRM_AMDGPU_WAIT_FENCES		0x12#define DRM_AMDGPU_VM			0x13#define DRM_AMDGPU_FENCE_TO_HANDLE	0x14#define DRM_AMDGPU_SCHED		0x15#define DRM_AMDGPU_USERQ		0x16#define DRM_AMDGPU_USERQ_SIGNAL		0x17#define DRM_AMDGPU_USERQ_WAIT		0x18#define DRM_AMDGPU_GEM_LIST_HANDLES	0x19#define DRM_AMDGPU_PROC_OPTIONS		0x1A #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)#define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)#define DRM_IOCTL_AMDGPU_CTX		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)#define DRM_IOCTL_AMDGPU_BO_LIST	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)#define DRM_IOCTL_AMDGPU_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)#define DRM_IOCTL_AMDGPU_INFO		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)#define DRM_IOCTL_AMDGPU_GEM_METADATA	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)#define DRM_IOCTL_AMDGPU_GEM_VA		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)#define DRM_IOCTL_AMDGPU_WAIT_CS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)#define DRM_IOCTL_AMDGPU_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)#define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)#define DRM_IOCTL_AMDGPU_WAIT_FENCES	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)#define DRM_IOCTL_AMDGPU_VM		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)#define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)#define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)#define DRM_IOCTL_AMDGPU_USERQ_WAIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)#define DRM_IOCTL_AMDGPU_PROC_OPTIONS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options) /** * DOC: memory domains * * %AMDGPU_GEM_DOMAIN_CPU	System memory that is not GPU accessible. * Memory in this pool could be swapped out to disk if there is pressure. * * %AMDGPU_GEM_DOMAIN_GTT	GPU accessible system memory, mapped into the * GPU's virtual address space via gart. Gart memory linearizes non-contiguous * pages of system memory, allows GPU access system memory in a linearized * fashion. * * %AMDGPU_GEM_DOMAIN_VRAM	Local video memory. For APUs, it is memory * carved out by the BIOS. * * %AMDGPU_GEM_DOMAIN_GDS	Global on-chip data storage used to share data * across shader threads. * * %AMDGPU_GEM_DOMAIN_GWS	Global wave sync, used to synchronize the * execution of all the waves on a device. * * %AMDGPU_GEM_DOMAIN_OA	Ordered append, used by 3D or Compute engines * for appending data. * * %AMDGPU_GEM_DOMAIN_DOORBELL	Doorbell. It is an MMIO region for * signalling user mode queues. */#define AMDGPU_GEM_DOMAIN_CPU		0x1#define AMDGPU_GEM_DOMAIN_GTT		0x2#define AMDGPU_GEM_DOMAIN_VRAM		0x4#define AMDGPU_GEM_DOMAIN_GDS		0x8#define AMDGPU_GEM_DOMAIN_GWS		0x10#define AMDGPU_GEM_DOMAIN_OA		0x20#define AMDGPU_GEM_DOMAIN_DOORBELL	0x40#define AMDGPU_GEM_DOMAIN_MASK		(AMDGPU_GEM_DOMAIN_CPU | \					 AMDGPU_GEM_DOMAIN_GTT | \					 AMDGPU_GEM_DOMAIN_VRAM | \					 AMDGPU_GEM_DOMAIN_GDS | \					 AMDGPU_GEM_DOMAIN_GWS | \					 AMDGPU_GEM_DOMAIN_OA |	\					 AMDGPU_GEM_DOMAIN_DOORBELL) /* Flag that CPU access will be required for the case of VRAM domain */#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)/* Flag that CPU access will not work, this VRAM domain is invisible */#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS		(1 << 1)/* Flag that USWC attributes should be used for GTT */#define AMDGPU_GEM_CREATE_CPU_GTT_USWC		(1 << 2)/* Flag that the memory should be in VRAM and cleared */#define AMDGPU_GEM_CREATE_VRAM_CLEARED		(1 << 3)/* Flag that allocating the BO should use linear VRAM */#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS	(1 << 5)/* Flag that BO is always valid in this VM */#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID	(1 << 6)/* Flag that BO sharing will be explicitly synchronized */#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC		(1 << 7)/* Flag that indicates allocating MQD gart on GFX9, where the mtype * for the second page onward should be set to NC. It should never * be used by user space applications. */#define AMDGPU_GEM_CREATE_CP_MQD_GFX9		(1 << 8)/* Flag that BO may contain sensitive data that must be wiped before * releasing the memory */#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE	(1 << 9)/* Flag that BO will be encrypted and that the TMZ bit should be * set in the PTEs when mapping this buffer via GPUVM or * accessing it with various hw blocks */#define AMDGPU_GEM_CREATE_ENCRYPTED		(1 << 10)/* Flag that BO will be used only in preemptible context, which does * not require GTT memory accounting */#define AMDGPU_GEM_CREATE_PREEMPTIBLE		(1 << 11)/* Flag that BO can be discarded under memory pressure without keeping the * content. */#define AMDGPU_GEM_CREATE_DISCARDABLE		(1 << 12)/* Flag that BO is shared coherently between multiple devices or CPU threads. * May depend on GPU instructions to flush caches to system scope explicitly. * * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and * may override the MTYPE selected in AMDGPU_VA_OP_MAP. */#define AMDGPU_GEM_CREATE_COHERENT		(1 << 13)/* Flag that BO should not be cached by GPU. Coherent without having to flush * GPU caches explicitly * * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and * may override the MTYPE selected in AMDGPU_VA_OP_MAP. */#define AMDGPU_GEM_CREATE_UNCACHED		(1 << 14)/* Flag that BO should be coherent across devices when using device-level * atomics. May depend on GPU instructions to flush caches to device scope * explicitly, promoting them to system scope automatically. * * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and * may override the MTYPE selected in AMDGPU_VA_OP_MAP. */#define AMDGPU_GEM_CREATE_EXT_COHERENT		(1 << 15)/* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */#define AMDGPU_GEM_CREATE_GFX12_DCC		(1 << 16) struct drm_amdgpu_gem_create_in  {	/** the requested memory size */	__u64 bo_size;	/** physical start_addr alignment in bytes for some HW requirements */	__u64 alignment;	/** the requested memory domains */	__u64 domains;	/** allocation flags */	__u64 domain_flags;}; struct drm_amdgpu_gem_create_out  {	/** returned GEM object handle */	__u32 handle;	__u32 _pad;}; union drm_amdgpu_gem_create {	struct drm_amdgpu_gem_create_in		in;	struct drm_amdgpu_gem_create_out	out;}; /** Opcode to create new residency list.  */#define AMDGPU_BO_LIST_OP_CREATE	0/** Opcode to destroy previously created residency list */#define AMDGPU_BO_LIST_OP_DESTROY	1/** Opcode to update resource information in the list */#define AMDGPU_BO_LIST_OP_UPDATE	2 struct drm_amdgpu_bo_list_in {	/** Type of operation */	__u32 operation;	/** Handle of list or 0 if we want to create one */	__u32 list_handle;	/** Number of BOs in list  */	__u32 bo_number;	/** Size of each element describing BO */	__u32 bo_info_size;	/** Pointer to array describing BOs */	__u64 bo_info_ptr;}; struct drm_amdgpu_bo_list_entry {	/** Handle of BO */	__u32 bo_handle;	/** New (if specified) BO priority to be used during migration */	__u32 bo_priority;}; struct drm_amdgpu_bo_list_out {	/** Handle of resource list  */	__u32 list_handle;	__u32 _pad;}; union drm_amdgpu_bo_list {	struct drm_amdgpu_bo_list_in in;	struct drm_amdgpu_bo_list_out out;}; /* context related */#define AMDGPU_CTX_OP_ALLOC_CTX	1#define AMDGPU_CTX_OP_FREE_CTX	2#define AMDGPU_CTX_OP_QUERY_STATE	3#define AMDGPU_CTX_OP_QUERY_STATE2	4#define AMDGPU_CTX_OP_GET_STABLE_PSTATE	5#define AMDGPU_CTX_OP_SET_STABLE_PSTATE	6 /* GPU reset status */#define AMDGPU_CTX_NO_RESET		0/* this the context caused it */#define AMDGPU_CTX_GUILTY_RESET		1/* some other context caused it */#define AMDGPU_CTX_INNOCENT_RESET	2/* unknown cause */#define AMDGPU_CTX_UNKNOWN_RESET	3 /* indicate gpu reset occurred after ctx created */#define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)/* indicate vram lost occurred after ctx created */#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)/* indicate some job from this context once cause gpu hang */#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)/* indicate some errors are detected by RAS */#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE   (1<<3)#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE   (1<<4)/* indicate that the reset hasn't completed yet */#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) /* Context priority level */#define AMDGPU_CTX_PRIORITY_UNSET       -2048#define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023#define AMDGPU_CTX_PRIORITY_LOW         -512#define AMDGPU_CTX_PRIORITY_NORMAL      0/* * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires * CAP_SYS_NICE or DRM_MASTER*/#define AMDGPU_CTX_PRIORITY_HIGH        512#define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023 /* select a stable profiling pstate for perfmon tools */#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK  0xf#define AMDGPU_CTX_STABLE_PSTATE_NONE  0#define AMDGPU_CTX_STABLE_PSTATE_STANDARD  1#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK  2#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK  3#define AMDGPU_CTX_STABLE_PSTATE_PEAK  4 struct drm_amdgpu_ctx_in {	/** AMDGPU_CTX_OP_* */	__u32	op;	/** Flags */	__u32	flags;	__u32	ctx_id;	/** AMDGPU_CTX_PRIORITY_* */	__s32	priority;}; union drm_amdgpu_ctx_out {		struct {			__u32	ctx_id;			__u32	_pad;		} alloc; 		struct {			/** For future use, no flags defined so far */			__u64	flags;			/** Number of resets caused by this context so far. */			__u32	hangs;			/** Reset status since the last call of the ioctl. */			__u32	reset_status;		} state; 		struct {			__u32	flags;			__u32	_pad;		} pstate;}; union drm_amdgpu_ctx {	struct drm_amdgpu_ctx_in in;	union drm_amdgpu_ctx_out out;}; /* user queue IOCTL operations */#define AMDGPU_USERQ_OP_CREATE	1#define AMDGPU_USERQ_OP_FREE	2 /* queue priority levels *//* low < normal low < normal high < high */#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK  0x3#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only *//* for queues that need access to protected content */#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE  (1 << 2) /* * This structure is a container to pass input configuration * info for all supported userqueue related operations. * For operation AMDGPU_USERQ_OP_CREATE: user is expected *  to set all fields, excep the parameter 'queue_id'. * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected *  to be set is 'queue_id', eveything else is ignored. */struct drm_amdgpu_userq_in {	/** AMDGPU_USERQ_OP_* */	__u32	op;	/** Queue id passed for operation USERQ_OP_FREE */	__u32	queue_id;	/** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */	__u32   ip_type;	/**	 * @doorbell_handle: the handle of doorbell GEM object	 * associated with this userqueue client.	 */	__u32   doorbell_handle;	/**	 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.	 * Kernel will generate absolute doorbell offset using doorbell_handle	 * and doorbell_offset in the doorbell bo.	 */	__u32   doorbell_offset;	/**	 * @flags: flags used for queue parameters	 */	__u32 flags;	/**	 * @queue_va: Virtual address of the GPU memory which holds the queue	 * object. The queue holds the workload packets.	 */	__u64   queue_va;	/**	 * @queue_size: Size of the queue in bytes, this needs to be 256-byte	 * aligned.	 */	__u64   queue_size;	/**	 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.	 * This object must be at least 8 byte in size and aligned to 8-byte offset.	 */	__u64   rptr_va;	/**	 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.	 * This object must be at least 8 byte in size and aligned to 8-byte offset.	 *	 * Queue, RPTR and WPTR can come from the same object, as long as the size	 * and alignment related requirements are met.	 */	__u64   wptr_va;	/**	 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow	 * the GPU to uniquely define and identify a usermode queue.	 *	 * MQD data can be of different size for different GPU IP/engine and	 * their respective versions/revisions, so this points to a __u64 *	 * which holds IP specific MQD of this usermode queue.	 */	__u64 mqd;	/**	 * @size: size of MQD data in bytes, it must match the MQD structure	 * size of the respective engine/revision defined in UAPI for ex, for	 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).	 */	__u64 mqd_size;}; /* The structure to carry output of userqueue ops */struct drm_amdgpu_userq_out {	/**	 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique	 * queue ID to represent the newly created userqueue in the system, otherwise	 * it should be ignored.	 */	__u32	queue_id;	__u32 _pad;}; union drm_amdgpu_userq {	struct drm_amdgpu_userq_in in;	struct drm_amdgpu_userq_out out;}; /* GFX V11 IP specific MQD parameters */struct drm_amdgpu_userq_mqd_gfx11 {	/**	 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.	 */	__u64   shadow_va;	/**	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.	 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.	 */	__u64   csa_va;}; /* GFX V11 SDMA IP specific MQD parameters */struct drm_amdgpu_userq_mqd_sdma_gfx11 {	/**	 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL	 * to get the size.	 */	__u64   csa_va;}; /* GFX V11 Compute IP specific MQD parameters */struct drm_amdgpu_userq_mqd_compute_gfx11 {	/**	 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.	 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL	 * to get the size.	 */	__u64   eop_va;}; /* userq signal/wait ioctl */struct drm_amdgpu_userq_signal {	/**	 * @queue_id: Queue handle used by the userq fence creation function	 * to retrieve the WPTR.	 */	__u32	queue_id;	__u32	pad;	/**	 * @syncobj_handles: The list of syncobj handles submitted by the user queue	 * job to be signaled.	 */	__u64	syncobj_handles;	/**	 * @num_syncobj_handles: A count that represents the number of syncobj handles in	 * @syncobj_handles.	 */	__u16	num_syncobj_handles;	__u16	pad0;	__u32	pad1;	/**	 * @bo_read_handles: The list of BO handles that the submitted user queue job	 * is using for read only. This will update BO fences in the kernel.	 */	__u64	bo_read_handles;	/**	 * @bo_write_handles: The list of BO handles that the submitted user queue job	 * is using for write only. This will update BO fences in the kernel.	 */	__u64	bo_write_handles;	/**	 * @num_bo_read_handles: A count that represents the number of read BO handles in	 * @bo_read_handles.	 */

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