/* SPDX-License-Identifier: MIT *//* * Copyright © 2023 Intel Corporation */ #ifndef _UAPI_XE_DRM_H_#define _UAPI_XE_DRM_H_ #include "drm.h" #if defined(__cplusplus)extern "C" {#endif /* * Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. * Sections in this file are organized as follows: * 1. IOCTL definition * 2. Extension definition and helper structs * 3. IOCTL's Query structs in the order of the Query's entries. * 4. The rest of IOCTL structs in the order of IOCTL declaration. */ /** * DOC: Xe Device Block Diagram * * The diagram below represents a high-level simplification of a discrete * GPU supported by the Xe driver. It shows some device components which * are necessary to understand this API, as well as how their relations * to each other. This diagram does not represent real hardware:: * * ┌──────────────────────────────────────────────────────────────────┐ * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ * └─────────────────────────────Device0───────┬──────────────────────┘ * │ * ───────────────────────┴────────── PCI bus */ /** * DOC: Xe uAPI Overview * * This section aims to describe the Xe's IOCTL entries, its structs, and other * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related * entries and usage. * * List of supported IOCTLs: * - &DRM_IOCTL_XE_DEVICE_QUERY * - &DRM_IOCTL_XE_GEM_CREATE * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET * - &DRM_IOCTL_XE_VM_CREATE * - &DRM_IOCTL_XE_VM_DESTROY * - &DRM_IOCTL_XE_VM_BIND * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY * - &DRM_IOCTL_XE_EXEC * - &DRM_IOCTL_XE_WAIT_USER_FENCE * - &DRM_IOCTL_XE_OBSERVATION * - &DRM_IOCTL_XE_MADVISE * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS * - &DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY * - &DRM_IOCTL_XE_VM_GET_PROPERTY */ /* * xe specific ioctls. * * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset * against DRM_COMMAND_BASE and should be between [0x0, 0x60). */#define DRM_XE_DEVICE_QUERY 0x00#define DRM_XE_GEM_CREATE 0x01#define DRM_XE_GEM_MMAP_OFFSET 0x02#define DRM_XE_VM_CREATE 0x03#define DRM_XE_VM_DESTROY 0x04#define DRM_XE_VM_BIND 0x05#define DRM_XE_EXEC_QUEUE_CREATE 0x06#define DRM_XE_EXEC_QUEUE_DESTROY 0x07#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08#define DRM_XE_EXEC 0x09#define DRM_XE_WAIT_USER_FENCE 0x0a#define DRM_XE_OBSERVATION 0x0b#define DRM_XE_MADVISE 0x0c#define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e#define DRM_XE_VM_GET_PROPERTY 0x0f /* Must be kept compact -- no holes */ #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)#define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)#define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)#define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)#define DRM_IOCTL_XE_VM_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_GET_PROPERTY, struct drm_xe_vm_get_property) /** * DOC: Xe IOCTL Extensions * * Before detailing the IOCTLs and its structs, it is important to highlight * that every IOCTL in Xe is extensible. * * Many interfaces need to grow over time. In most cases we can simply * extend the struct and have userspace pass in more data. Another option, * as demonstrated by Vulkan's approach to providing extensions for forward * and backward compatibility, is to use a list of optional structs to * provide those extra details. * * The key advantage to using an extension chain is that it allows us to * redefine the interface more easily than an ever growing struct of * increasing complexity, and for large parts of that interface to be * entirely optional. The downside is more pointer chasing; chasing across * the __user boundary with pointers encapsulated inside u64. * * Example chaining: * * .. code-block:: C * * struct drm_xe_user_extension ext3 { * .next_extension = 0, // end * .name = ..., * }; * struct drm_xe_user_extension ext2 { * .next_extension = (uintptr_t)&ext3, * .name = ..., * }; * struct drm_xe_user_extension ext1 { * .next_extension = (uintptr_t)&ext2, * .name = ..., * }; * * Typically the struct drm_xe_user_extension would be embedded in some uAPI * struct, and in this case we would feed it the head of the chain(i.e ext1), * which would then apply all of the above extensions. */ /** * struct drm_xe_user_extension - Base class for defining a chain of extensions */struct drm_xe_user_extension { /** * @next_extension: * * Pointer to the next struct drm_xe_user_extension, or zero if the end. */ __u64 next_extension; /** * @name: Name of the extension. * * Note that the name here is just some integer. * * Also note that the name space for this is not global for the whole * driver, but rather its scope/meaning is limited to the specific piece * of uAPI which has embedded the struct drm_xe_user_extension. */ __u32 name; /** * @pad: MBZ * * All undefined bits must be zero. */ __u32 pad;}; /** * struct drm_xe_ext_set_property - Generic set property extension * * A generic struct that allows any of the Xe's IOCTL to be extended * with a set_property operation. */struct drm_xe_ext_set_property { /** @base: base user extension */ struct drm_xe_user_extension base; /** @property: property to set */ __u32 property; /** @pad: MBZ */ __u32 pad; union { /** @value: property value */ __u64 value; /** @ptr: pointer to user value */ __u64 ptr; }; /** @reserved: Reserved */ __u64 reserved[2];}; /** * struct drm_xe_engine_class_instance - instance of an engine class * * It is returned as part of the &struct drm_xe_engine, but it also is used as * the input of engine selection for both &struct drm_xe_exec_queue_create and * &struct drm_xe_query_engine_cycles * * The @engine_class can be: * - %DRM_XE_ENGINE_CLASS_RENDER * - %DRM_XE_ENGINE_CLASS_COPY * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE * - %DRM_XE_ENGINE_CLASS_COMPUTE * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual * hardware engine class). Used for creating ordered queues of VM * bind operations. */struct drm_xe_engine_class_instance {#define DRM_XE_ENGINE_CLASS_RENDER 0#define DRM_XE_ENGINE_CLASS_COPY 1#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3#define DRM_XE_ENGINE_CLASS_COMPUTE 4#define DRM_XE_ENGINE_CLASS_VM_BIND 5 /** @engine_class: engine class id */ __u16 engine_class; /** @engine_instance: engine instance id */ __u16 engine_instance; /** @gt_id: Unique ID of this GT within the PCI Device */ __u16 gt_id; /** @pad: MBZ */ __u16 pad;}; /** * struct drm_xe_engine - describe hardware engine */struct drm_xe_engine { /** @instance: The &struct drm_xe_engine_class_instance */ struct drm_xe_engine_class_instance instance; /** @reserved: Reserved */ __u64 reserved[3];}; /** * struct drm_xe_query_engines - describe engines * * If a query is made with a &struct drm_xe_device_query where .query * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of * &struct drm_xe_query_engines in .data. */struct drm_xe_query_engines { /** @num_engines: number of engines returned in @engines */ __u32 num_engines; /** @pad: MBZ */ __u32 pad; /** @engines: The returned engines for this device */ struct drm_xe_engine engines[];}; /** * enum drm_xe_memory_class - Supported memory classes. */enum drm_xe_memory_class { /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, /** * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this * represents the memory that is local to the device, which we * call VRAM. Not valid on integrated platforms. */ DRM_XE_MEM_REGION_CLASS_VRAM}; /** * struct drm_xe_mem_region - Describes some region as known to * the driver. */struct drm_xe_mem_region { /** * @mem_class: The memory class describing this region. * * See enum drm_xe_memory_class for supported values. */ __u16 mem_class; /** * @instance: The unique ID for this region, which serves as the * index in the placement bitmask used as argument for * &DRM_IOCTL_XE_GEM_CREATE */ __u16 instance; /** * @min_page_size: Min page-size in bytes for this region. * * When the kernel allocates memory for this region, the * underlying pages will be at least @min_page_size in size. * Buffer objects with an allowable placement in this region must be * created with a size aligned to this value. * GPU virtual address mappings of (parts of) buffer objects that * may be placed in this region must also have their GPU virtual * address and range aligned to this value. * Affected IOCTLS will return %-EINVAL if alignment restrictions are * not met. */ __u32 min_page_size; /** * @total_size: The usable size in bytes for this region. */ __u64 total_size; /** * @used: Estimate of the memory used in bytes for this region. */ __u64 used; /** * @cpu_visible_size: How much of this region can be CPU * accessed, in bytes. * * This will always be <= @total_size, and the remainder (if * any) will not be CPU accessible. If the CPU accessible part * is smaller than @total_size then this is referred to as a * small BAR system. * * On systems without small BAR (full BAR), the @cpu_visible_size will * always equal the @total_size, since all of it will be CPU * accessible. * * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM * regions (for other types the value here will always equal * zero). */ __u64 cpu_visible_size; /** * @cpu_visible_used: Estimate of CPU visible memory used, in * bytes. * * Note this is only currently tracked for * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value * here will always be zero). */ __u64 cpu_visible_used; /** @reserved: Reserved */ __u64 reserved[6];}; /** * struct drm_xe_query_mem_regions - describe memory regions * * If a query is made with a struct drm_xe_device_query where .query * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses * struct drm_xe_query_mem_regions in .data. */struct drm_xe_query_mem_regions { /** @num_mem_regions: number of memory regions returned in @mem_regions */ __u32 num_mem_regions; /** @pad: MBZ */ __u32 pad; /** @mem_regions: The returned memory regions for this device */ struct drm_xe_mem_region mem_regions[];}; /** * struct drm_xe_query_config - describe the device configuration * * If a query is made with a struct drm_xe_device_query where .query * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses * struct drm_xe_query_config in .data. * * The index in @info can be: * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) * and the device revision (next 8 bits) * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device * configuration, see list below * * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device * has usable VRAM * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device * has low latency hint support * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the * device has CPU address mirroring support * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the * device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION. * This is exposed only on Xe2+. * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX - Flag is set * if a queue can be created with * %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment * required by this device, typically SZ_4K or SZ_64K * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest * available exec queue priority */struct drm_xe_query_config { /** @num_params: number of parameters returned in info */ __u32 num_params; /** @pad: MBZ */ __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0#define DRM_XE_QUERY_CONFIG_FLAGS 1 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5)#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2#define DRM_XE_QUERY_CONFIG_VA_BITS 3#define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 /** @info: array of elements containing the config info */ __u64 info[];}; /** * struct drm_xe_gt - describe an individual GT. * * To be used with drm_xe_query_gt_list, which will return a list with all the * existing GT individual descriptions. * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for * implementing graphics and/or media operations. * * The index in @type can be: * - %DRM_XE_QUERY_GT_TYPE_MAIN * - %DRM_XE_QUERY_GT_TYPE_MEDIA */struct drm_xe_gt {#define DRM_XE_QUERY_GT_TYPE_MAIN 0#define DRM_XE_QUERY_GT_TYPE_MEDIA 1 /** @type: GT type: Main or Media */ __u16 type; /** @tile_id: Tile ID where this GT lives (Information only) */ __u16 tile_id; /** @gt_id: Unique ID of this GT within the PCI Device */ __u16 gt_id; /** @pad: MBZ */ __u16 pad[3]; /** @reference_clock: A clock frequency for timestamp */ __u32 reference_clock; /** * @near_mem_regions: Bit mask of instances from * drm_xe_query_mem_regions that are nearest to the current engines * of this GT. * Each index in this mask refers directly to the struct * drm_xe_query_mem_regions' instance, no assumptions should * be made about order. The type of each region is described * by struct drm_xe_query_mem_regions' mem_class. */ __u64 near_mem_regions; /** * @far_mem_regions: Bit mask of instances from * drm_xe_query_mem_regions that are far from the engines of this GT. * In general, they have extra indirections when compared to the * @near_mem_regions. For a discrete device this could mean system * memory and memory living in a different tile. * Each index in this mask refers directly to the struct * drm_xe_query_mem_regions' instance, no assumptions should * be made about order. The type of each region is described * by struct drm_xe_query_mem_regions' mem_class. */ __u64 far_mem_regions; /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */ __u16 ip_ver_major; /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */ __u16 ip_ver_minor; /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */ __u16 ip_ver_rev; /** @pad2: MBZ */ __u16 pad2; /** @reserved: Reserved */ __u64 reserved[7];Lines 1–500 of 2625. Load more
/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef _UAPI_XE_DRM_H_ #define _UAPI_XE_DRM_H_ #include "drm.h" #if defined(__cplusplus) extern "C" { #endif /* * Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. * Sections in this file are organized as follows: * 1. IOCTL definition * 2. Extension definition and helper structs * 3. IOCTL's Query structs in the order of the Query's entries. * 4. The rest of IOCTL structs in the order of IOCTL declaration. */ /** * DOC: Xe Device Block Diagram * * The diagram below represents a high-level simplification of a discrete * GPU supported by the Xe driver. It shows some device components which * are necessary to understand this API, as well as how their relations * to each other. This diagram does not represent real hardware:: * * ┌──────────────────────────────────────────────────────────────────┐ * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ * └─────────────────────────────Device0───────┬──────────────────────┘ * │ * ───────────────────────┴────────── PCI bus */ /** * DOC: Xe uAPI Overview * * This section aims to describe the Xe's IOCTL entries, its structs, and other * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related * entries and usage. * * List of supported IOCTLs: * - &DRM_IOCTL_XE_DEVICE_QUERY * - &DRM_IOCTL_XE_GEM_CREATE * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET * - &DRM_IOCTL_XE_VM_CREATE * - &DRM_IOCTL_XE_VM_DESTROY * - &DRM_IOCTL_XE_VM_BIND * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY * - &DRM_IOCTL_XE_EXEC * - &DRM_IOCTL_XE_WAIT_USER_FENCE * - &DRM_IOCTL_XE_OBSERVATION * - &DRM_IOCTL_XE_MADVISE * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS * - &DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY * - &DRM_IOCTL_XE_VM_GET_PROPERTY */ /* * xe specific ioctls. * * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset * against DRM_COMMAND_BASE and should be between [0x0, 0x60). */ #define DRM_XE_DEVICE_QUERY 0x00 #define DRM_XE_GEM_CREATE 0x01 #define DRM_XE_GEM_MMAP_OFFSET 0x02 #define DRM_XE_VM_CREATE 0x03 #define DRM_XE_VM_DESTROY 0x04 #define DRM_XE_VM_BIND 0x05 #define DRM_XE_EXEC_QUEUE_CREATE 0x06 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 #define DRM_XE_EXEC 0x09 #define DRM_XE_WAIT_USER_FENCE 0x0a #define DRM_XE_OBSERVATION 0x0b #define DRM_XE_MADVISE 0x0c #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d #define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e #define DRM_XE_VM_GET_PROPERTY 0x0f /* Must be kept compact -- no holes */ #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) #define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise) #define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr) #define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) #define DRM_IOCTL_XE_VM_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_GET_PROPERTY, struct drm_xe_vm_get_property) /** * DOC: Xe IOCTL Extensions * * Before detailing the IOCTLs and its structs, it is important to highlight * that every IOCTL in Xe is extensible. * * Many interfaces need to grow over time. In most cases we can simply * extend the struct and have userspace pass in more data. Another option, * as demonstrated by Vulkan's approach to providing extensions for forward * and backward compatibility, is to use a list of optional structs to * provide those extra details. * * The key advantage to using an extension chain is that it allows us to * redefine the interface more easily than an ever growing struct of * increasing complexity, and for large parts of that interface to be * entirely optional. The downside is more pointer chasing; chasing across * the __user boundary with pointers encapsulated inside u64. * * Example chaining: * * .. code-block:: C * * struct drm_xe_user_extension ext3 { * .next_extension = 0, // end * .name = ..., * }; * struct drm_xe_user_extension ext2 { * .next_extension = (uintptr_t)&ext3, * .name = ..., * }; * struct drm_xe_user_extension ext1 { * .next_extension = (uintptr_t)&ext2, * .name = ..., * }; * * Typically the struct drm_xe_user_extension would be embedded in some uAPI * struct, and in this case we would feed it the head of the chain(i.e ext1), * which would then apply all of the above extensions. */ /** * struct drm_xe_user_extension - Base class for defining a chain of extensions */ struct drm_xe_user_extension { /** * @next_extension: * * Pointer to the next struct drm_xe_user_extension, or zero if the end. */ __u64 next_extension; /** * @name: Name of the extension. * * Note that the name here is just some integer. * * Also note that the name space for this is not global for the whole * driver, but rather its scope/meaning is limited to the specific piece * of uAPI which has embedded the struct drm_xe_user_extension. */ __u32 name; /** * @pad: MBZ * * All undefined bits must be zero. */ __u32 pad; }; /** * struct drm_xe_ext_set_property - Generic set property extension * * A generic struct that allows any of the Xe's IOCTL to be extended * with a set_property operation. */ struct drm_xe_ext_set_property { /** @base: base user extension */ struct drm_xe_user_extension base; /** @property: property to set */ __u32 property; /** @pad: MBZ */ __u32 pad; union { /** @value: property value */ __u64 value; /** @ptr: pointer to user value */ __u64 ptr; }; /** @reserved: Reserved */ __u64 reserved[2]; }; /** * struct drm_xe_engine_class_instance - instance of an engine class * * It is returned as part of the &struct drm_xe_engine, but it also is used as * the input of engine selection for both &struct drm_xe_exec_queue_create and * &struct drm_xe_query_engine_cycles * * The @engine_class can be: * - %DRM_XE_ENGINE_CLASS_RENDER * - %DRM_XE_ENGINE_CLASS_COPY * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE * - %DRM_XE_ENGINE_CLASS_COMPUTE * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual * hardware engine class). Used for creating ordered queues of VM * bind operations. */ struct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0 #define DRM_XE_ENGINE_CLASS_COPY 1 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 /** @engine_class: engine class id */ __u16 engine_class; /** @engine_instance: engine instance id */ __u16 engine_instance; /** @gt_id: Unique ID of this GT within the PCI Device */ __u16 gt_id; /** @pad: MBZ */ __u16 pad; }; /** * struct drm_xe_engine - describe hardware engine */ struct drm_xe_engine { /** @instance: The &struct drm_xe_engine_class_instance */ struct drm_xe_engine_class_instance instance; /** @reserved: Reserved */ __u64 reserved[3]; }; /** * struct drm_xe_query_engines - describe engines * * If a query is made with a &struct drm_xe_device_query where .query * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of * &struct drm_xe_query_engines in .data. */ struct drm_xe_query_engines { /** @num_engines: number of engines returned in @engines */ __u32 num_engines; /** @pad: MBZ */ __u32 pad; /** @engines: The returned engines for this device */ struct drm_xe_engine engines[]; }; /** * enum drm_xe_memory_class - Supported memory classes. */ enum drm_xe_memory_class { /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, /** * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this * represents the memory that is local to the device, which we * call VRAM. Not valid on integrated platforms. */ DRM_XE_MEM_REGION_CLASS_VRAM }; /** * struct drm_xe_mem_region - Describes some region as known to * the driver. */ struct drm_xe_mem_region { /** * @mem_class: The memory class describing this region. * * See enum drm_xe_memory_class for supported values. */ __u16 mem_class; /** * @instance: The unique ID for this region, which serves as the * index in the placement bitmask used as argument for * &DRM_IOCTL_XE_GEM_CREATE */ __u16 instance; /** * @min_page_size: Min page-size in bytes for this region. * * When the kernel allocates memory for this region, the * underlying pages will be at least @min_page_size in size. * Buffer objects with an allowable placement in this region must be * created with a size aligned to this value. * GPU virtual address mappings of (parts of) buffer objects that * may be placed in this region must also have their GPU virtual * address and range aligned to this value. * Affected IOCTLS will return %-EINVAL if alignment restrictions are * not met. */ __u32 min_page_size; /** * @total_size: The usable size in bytes for this region. */ __u64 total_size; /** * @used: Estimate of the memory used in bytes for this region. */ __u64 used; /** * @cpu_visible_size: How much of this region can be CPU * accessed, in bytes. * * This will always be <= @total_size, and the remainder (if * any) will not be CPU accessible. If the CPU accessible part * is smaller than @total_size then this is referred to as a * small BAR system. * * On systems without small BAR (full BAR), the @cpu_visible_size will * always equal the @total_size, since all of it will be CPU * accessible. * * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM * regions (for other types the value here will always equal * zero). */ __u64 cpu_visible_size; /** * @cpu_visible_used: Estimate of CPU visible memory used, in * bytes. * * Note this is only currently tracked for * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value * here will always be zero). */ __u64 cpu_visible_used; /** @reserved: Reserved */ __u64 reserved[6]; }; /** * struct drm_xe_query_mem_regions - describe memory regions * * If a query is made with a struct drm_xe_device_query where .query * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses * struct drm_xe_query_mem_regions in .data. */ struct drm_xe_query_mem_regions { /** @num_mem_regions: number of memory regions returned in @mem_regions */ __u32 num_mem_regions; /** @pad: MBZ */ __u32 pad; /** @mem_regions: The returned memory regions for this device */ struct drm_xe_mem_region mem_regions[]; }; /** * struct drm_xe_query_config - describe the device configuration * * If a query is made with a struct drm_xe_device_query where .query * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses * struct drm_xe_query_config in .data. * * The index in @info can be: * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) * and the device revision (next 8 bits) * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device * configuration, see list below * * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device * has usable VRAM * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device * has low latency hint support * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the * device has CPU address mirroring support * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the * device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION. * This is exposed only on Xe2+. * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX - Flag is set * if a queue can be created with * %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment * required by this device, typically SZ_4K or SZ_64K * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest * available exec queue priority */ struct drm_xe_query_config { /** @num_params: number of parameters returned in info */ __u32 num_params; /** @pad: MBZ */ __u32 pad; #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 #define DRM_XE_QUERY_CONFIG_FLAGS 1 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4) #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5) #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 /** @info: array of elements containing the config info */ __u64 info[]; }; /** * struct drm_xe_gt - describe an individual GT. * * To be used with drm_xe_query_gt_list, which will return a list with all the * existing GT individual descriptions. * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for * implementing graphics and/or media operations. * * The index in @type can be: * - %DRM_XE_QUERY_GT_TYPE_MAIN * - %DRM_XE_QUERY_GT_TYPE_MEDIA */ struct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 /** @type: GT type: Main or Media */ __u16 type; /** @tile_id: Tile ID where this GT lives (Information only) */ __u16 tile_id; /** @gt_id: Unique ID of this GT within the PCI Device */ __u16 gt_id; /** @pad: MBZ */ __u16 pad[3]; /** @reference_clock: A clock frequency for timestamp */ __u32 reference_clock; /** * @near_mem_regions: Bit mask of instances from * drm_xe_query_mem_regions that are nearest to the current engines * of this GT. * Each index in this mask refers directly to the struct * drm_xe_query_mem_regions' instance, no assumptions should * be made about order. The type of each region is described * by struct drm_xe_query_mem_regions' mem_class. */ __u64 near_mem_regions; /** * @far_mem_regions: Bit mask of instances from * drm_xe_query_mem_regions that are far from the engines of this GT. * In general, they have extra indirections when compared to the * @near_mem_regions. For a discrete device this could mean system * memory and memory living in a different tile. * Each index in this mask refers directly to the struct * drm_xe_query_mem_regions' instance, no assumptions should * be made about order. The type of each region is described * by struct drm_xe_query_mem_regions' mem_class. */ __u64 far_mem_regions; /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */ __u16 ip_ver_major; /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */ __u16 ip_ver_minor; /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */ __u16 ip_ver_rev; /** @pad2: MBZ */ __u16 pad2; /** @reserved: Reserved */ __u64 reserved[7];