/* AArch64 assembler/disassembler support.    Copyright 2009, 2010, 2011, 2012, 2013  Free Software Foundation, Inc.   Contributed by ARM Ltd.    This file is part of GNU Binutils.    This program is free software; you can redistribute it and/or modify   it under the terms of the GNU General Public License as published by   the Free Software Foundation; either version 3 of the license, or   (at your option) any later version.    This program is distributed in the hope that it will be useful,   but WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the   GNU General Public License for more details.    You should have received a copy of the GNU General Public License   along with this program; see the file COPYING3. If not,   see <http://www.gnu.org/licenses/>.  */ #ifndef OPCODE_AARCH64_H#define OPCODE_AARCH64_H #include "bfd.h"#include "bfd_stdint.h"#include <assert.h>#include <stdlib.h> /* The offset for pc-relative addressing is currently defined to be 0.  */#define AARCH64_PCREL_OFFSET		0 typedef uint32_t aarch64_insn; /* The following bitmasks control CPU features.  */#define AARCH64_FEATURE_V8	0x00000001	/* All processors.  */#define AARCH64_FEATURE_CRYPTO	0x00010000	/* Crypto instructions.  */#define AARCH64_FEATURE_FP	0x00020000	/* FP instructions.  */#define AARCH64_FEATURE_SIMD	0x00040000	/* SIMD instructions.  */#define AARCH64_FEATURE_CRC	0x00080000	/* CRC instructions.  */ /* Architectures are the sum of the base and extensions.  */#define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \						 AARCH64_FEATURE_FP  \						 | AARCH64_FEATURE_SIMD)#define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)#define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */ /* CPU-specific features.  */typedef unsigned long aarch64_feature_set; #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)	\  (((CPU) & (FEAT)) != 0) #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)	\  do						\    {						\      (TARG) = (F1) | (F2);			\    }						\  while (0) #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)	\  do						\    { 						\      (TARG) = (F1) &~ (F2);			\    }						\  while (0) #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)	\  (((OPC) & (FEAT)) != 0) enum aarch64_operand_class{  AARCH64_OPND_CLASS_NIL,  AARCH64_OPND_CLASS_INT_REG,  AARCH64_OPND_CLASS_MODIFIED_REG,  AARCH64_OPND_CLASS_FP_REG,  AARCH64_OPND_CLASS_SIMD_REG,  AARCH64_OPND_CLASS_SIMD_ELEMENT,  AARCH64_OPND_CLASS_SISD_REG,  AARCH64_OPND_CLASS_SIMD_REGLIST,  AARCH64_OPND_CLASS_CP_REG,  AARCH64_OPND_CLASS_ADDRESS,  AARCH64_OPND_CLASS_IMMEDIATE,  AARCH64_OPND_CLASS_SYSTEM,  AARCH64_OPND_CLASS_COND,}; /* Operand code that helps both parsing and coding.   Keep AARCH64_OPERANDS synced.  */ enum aarch64_opnd{  AARCH64_OPND_NIL,	/* no operand---MUST BE FIRST!*/   AARCH64_OPND_Rd,	/* Integer register as destination.  */  AARCH64_OPND_Rn,	/* Integer register as source.  */  AARCH64_OPND_Rm,	/* Integer register as source.  */  AARCH64_OPND_Rt,	/* Integer register used in ld/st instructions.  */  AARCH64_OPND_Rt2,	/* Integer register used in ld/st pair instructions.  */  AARCH64_OPND_Rs,	/* Integer register used in ld/st exclusive.  */  AARCH64_OPND_Ra,	/* Integer register used in ddp_3src instructions.  */  AARCH64_OPND_Rt_SYS,	/* Integer register used in system instructions.  */   AARCH64_OPND_Rd_SP,	/* Integer Rd or SP.  */  AARCH64_OPND_Rn_SP,	/* Integer Rn or SP.  */  AARCH64_OPND_Rm_EXT,	/* Integer Rm extended.  */  AARCH64_OPND_Rm_SFT,	/* Integer Rm shifted.  */   AARCH64_OPND_Fd,	/* Floating-point Fd.  */  AARCH64_OPND_Fn,	/* Floating-point Fn.  */  AARCH64_OPND_Fm,	/* Floating-point Fm.  */  AARCH64_OPND_Fa,	/* Floating-point Fa.  */  AARCH64_OPND_Ft,	/* Floating-point Ft.  */  AARCH64_OPND_Ft2,	/* Floating-point Ft2.  */   AARCH64_OPND_Sd,	/* AdvSIMD Scalar Sd.  */  AARCH64_OPND_Sn,	/* AdvSIMD Scalar Sn.  */  AARCH64_OPND_Sm,	/* AdvSIMD Scalar Sm.  */   AARCH64_OPND_Vd,	/* AdvSIMD Vector Vd.  */  AARCH64_OPND_Vn,	/* AdvSIMD Vector Vn.  */  AARCH64_OPND_Vm,	/* AdvSIMD Vector Vm.  */  AARCH64_OPND_VdD1,	/* AdvSIMD <Vd>.D[1]; for FMOV only.  */  AARCH64_OPND_VnD1,	/* AdvSIMD <Vn>.D[1]; for FMOV only.  */  AARCH64_OPND_Ed,	/* AdvSIMD Vector Element Vd.  */  AARCH64_OPND_En,	/* AdvSIMD Vector Element Vn.  */  AARCH64_OPND_Em,	/* AdvSIMD Vector Element Vm.  */  AARCH64_OPND_LVn,	/* AdvSIMD Vector register list used in e.g. TBL.  */  AARCH64_OPND_LVt,	/* AdvSIMD Vector register list used in ld/st.  */  AARCH64_OPND_LVt_AL,	/* AdvSIMD Vector register list for loading single			   structure to all lanes.  */  AARCH64_OPND_LEt,	/* AdvSIMD Vector Element list.  */   AARCH64_OPND_Cn,	/* Co-processor register in CRn field.  */  AARCH64_OPND_Cm,	/* Co-processor register in CRm field.  */   AARCH64_OPND_IDX,	/* AdvSIMD EXT index operand.  */  AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */  AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */  AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */  AARCH64_OPND_SIMD_IMM_SFT,	/* AdvSIMD modified immediate with shift.  */  AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */  AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction			   (no encoding).  */  AARCH64_OPND_IMM0,	/* Immediate for #0.  */  AARCH64_OPND_FPIMM0,	/* Immediate for #0.0.  */  AARCH64_OPND_FPIMM,	/* Floating-point Immediate.  */  AARCH64_OPND_IMMR,	/* Immediate #<immr> in e.g. BFM.  */  AARCH64_OPND_IMMS,	/* Immediate #<imms> in e.g. BFM.  */  AARCH64_OPND_WIDTH,	/* Immediate #<width> in e.g. BFI.  */  AARCH64_OPND_IMM,	/* Immediate.  */  AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */  AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */  AARCH64_OPND_UIMM4,	/* Unsigned 4-bit immediate in the CRm field.  */  AARCH64_OPND_UIMM7,	/* Unsigned 7-bit immediate in the CRm:op2 fields.  */  AARCH64_OPND_BIT_NUM,	/* Immediate.  */  AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */  AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */  AARCH64_OPND_NZCV,	/* Flag bit specifier giving an alternative value for			   each condition flag.  */   AARCH64_OPND_LIMM,	/* Logical Immediate.  */  AARCH64_OPND_AIMM,	/* Arithmetic immediate.  */  AARCH64_OPND_HALF,	/* #<imm16>{, LSL #<shift>} operand in move wide.  */  AARCH64_OPND_FBITS,	/* FP #<fbits> operand in e.g. SCVTF */  AARCH64_OPND_IMM_MOV,	/* Immediate operand for the MOV alias.  */   AARCH64_OPND_COND,	/* Standard condition as the last operand.  */  AARCH64_OPND_COND1,	/* Same as the above, but excluding AL and NV.  */   AARCH64_OPND_ADDR_ADRP,	/* Memory address for ADRP */  AARCH64_OPND_ADDR_PCREL14,	/* 14-bit PC-relative address for e.g. TBZ.  */  AARCH64_OPND_ADDR_PCREL19,	/* 19-bit PC-relative address for e.g. LDR.  */  AARCH64_OPND_ADDR_PCREL21,	/* 21-bit PC-relative address for e.g. ADR.  */  AARCH64_OPND_ADDR_PCREL26,	/* 26-bit PC-relative address for e.g. BL.  */   AARCH64_OPND_ADDR_SIMPLE,	/* Address of ld/st exclusive.  */  AARCH64_OPND_ADDR_REGOFF,	/* Address of register offset.  */  AARCH64_OPND_ADDR_SIMM7,	/* Address of signed 7-bit immediate.  */  AARCH64_OPND_ADDR_SIMM9,	/* Address of signed 9-bit immediate.  */  AARCH64_OPND_ADDR_SIMM9_2,	/* Same as the above, but the immediate is				   negative or unaligned and there is				   no writeback allowed.  This operand code				   is only used to support the programmer-				   friendly feature of using LDR/STR as the				   the mnemonic name for LDUR/STUR instructions				   wherever there is no ambiguity.  */  AARCH64_OPND_ADDR_UIMM12,	/* Address of unsigned 12-bit immediate.  */  AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */  AARCH64_OPND_SIMD_ADDR_POST,	/* Address of ld/st multiple post-indexed.  */   AARCH64_OPND_SYSREG,		/* System register operand.  */  AARCH64_OPND_PSTATEFIELD,	/* PSTATE field name operand.  */  AARCH64_OPND_SYSREG_AT,	/* System register <at_op> operand.  */  AARCH64_OPND_SYSREG_DC,	/* System register <dc_op> operand.  */  AARCH64_OPND_SYSREG_IC,	/* System register <ic_op> operand.  */  AARCH64_OPND_SYSREG_TLBI,	/* System register <tlbi_op> operand.  */  AARCH64_OPND_BARRIER,		/* Barrier operand.  */  AARCH64_OPND_BARRIER_ISB,	/* Barrier operand for ISB.  */  AARCH64_OPND_PRFOP,		/* Prefetch operation.  */}; /* Qualifier constrains an operand.  It either specifies a variant of an   operand type or limits values available to an operand type.    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */ enum aarch64_opnd_qualifier{  /* Indicating no further qualification on an operand.  */  AARCH64_OPND_QLF_NIL,   /* Qualifying an operand which is a general purpose (integer) register;     indicating the operand data size or a specific register.  */  AARCH64_OPND_QLF_W,	/* Wn, WZR or WSP.  */  AARCH64_OPND_QLF_X,	/* Xn, XZR or XSP.  */  AARCH64_OPND_QLF_WSP,	/* WSP.  */  AARCH64_OPND_QLF_SP,	/* SP.  */   /* Qualifying an operand which is a floating-point register, a SIMD     vector element or a SIMD vector element list; indicating operand data     size or the size of each SIMD vector element in the case of a SIMD     vector element list.     These qualifiers are also used to qualify an address operand to     indicate the size of data element a load/store instruction is     accessing.     They are also used for the immediate shift operand in e.g. SSHR.  Such     a use is only for the ease of operand encoding/decoding and qualifier     sequence matching; such a use should not be applied widely; use the value     constraint qualifiers for immediate operands wherever possible.  */  AARCH64_OPND_QLF_S_B,  AARCH64_OPND_QLF_S_H,  AARCH64_OPND_QLF_S_S,  AARCH64_OPND_QLF_S_D,  AARCH64_OPND_QLF_S_Q,   /* Qualifying an operand which is a SIMD vector register or a SIMD vector     register list; indicating register shape.     They are also used for the immediate shift operand in e.g. SSHR.  Such     a use is only for the ease of operand encoding/decoding and qualifier     sequence matching; such a use should not be applied widely; use the value     constraint qualifiers for immediate operands wherever possible.  */  AARCH64_OPND_QLF_V_8B,  AARCH64_OPND_QLF_V_16B,  AARCH64_OPND_QLF_V_4H,  AARCH64_OPND_QLF_V_8H,  AARCH64_OPND_QLF_V_2S,  AARCH64_OPND_QLF_V_4S,  AARCH64_OPND_QLF_V_1D,  AARCH64_OPND_QLF_V_2D,  AARCH64_OPND_QLF_V_1Q,   /* Constraint on value.  */  AARCH64_OPND_QLF_imm_0_7,  AARCH64_OPND_QLF_imm_0_15,  AARCH64_OPND_QLF_imm_0_31,  AARCH64_OPND_QLF_imm_0_63,  AARCH64_OPND_QLF_imm_1_32,  AARCH64_OPND_QLF_imm_1_64,   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros     or shift-ones.  */  AARCH64_OPND_QLF_LSL,  AARCH64_OPND_QLF_MSL,   /* Special qualifier helping retrieve qualifier information during the     decoding time (currently not in use).  */  AARCH64_OPND_QLF_RETRIEVE,};/* Instruction class.  */ enum aarch64_insn_class{  addsub_carry,  addsub_ext,  addsub_imm,  addsub_shift,  asimdall,  asimddiff,  asimdelem,  asimdext,  asimdimm,  asimdins,  asimdmisc,  asimdperm,  asimdsame,  asimdshf,  asimdtbl,  asisddiff,  asisdelem,  asisdlse,  asisdlsep,  asisdlso,  asisdlsop,  asisdmisc,  asisdone,  asisdpair,  asisdsame,  asisdshf,  bitfield,  branch_imm,  branch_reg,  compbranch,  condbranch,  condcmp_imm,  condcmp_reg,  condsel,  cryptoaes,  cryptosha2,  cryptosha3,  dp_1src,  dp_2src,  dp_3src,  exception,  extract,  float2fix,  float2int,  floatccmp,  floatcmp,  floatdp1,  floatdp2,  floatdp3,  floatimm,  floatsel,  ldst_immpost,  ldst_immpre,  ldst_imm9,	/* immpost or immpre */  ldst_pos,  ldst_regoff,  ldst_unpriv,  ldst_unscaled,  ldstexcl,  ldstnapair_offs,  ldstpair_off,  ldstpair_indexed,  loadlit,  log_imm,  log_shift,  movewide,  pcreladdr,  ic_system,  testbranch,}; /* Opcode enumerators.  */ enum aarch64_op{  OP_NIL,  OP_STRB_POS,  OP_LDRB_POS,  OP_LDRSB_POS,  OP_STRH_POS,  OP_LDRH_POS,  OP_LDRSH_POS,  OP_STR_POS,  OP_LDR_POS,  OP_STRF_POS,  OP_LDRF_POS,  OP_LDRSW_POS,  OP_PRFM_POS,   OP_STURB,  OP_LDURB,  OP_LDURSB,  OP_STURH,  OP_LDURH,  OP_LDURSH,  OP_STUR,  OP_LDUR,  OP_STURV,  OP_LDURV,  OP_LDURSW,  OP_PRFUM,   OP_LDR_LIT,  OP_LDRV_LIT,  OP_LDRSW_LIT,  OP_PRFM_LIT,   OP_ADD,  OP_B,  OP_BL,   OP_MOVN,  OP_MOVZ,  OP_MOVK,   OP_MOV_IMM_LOG,	/* MOV alias for moving bitmask immediate.  */  OP_MOV_IMM_WIDE,	/* MOV alias for moving wide immediate.  */  OP_MOV_IMM_WIDEN,	/* MOV alias for moving wide immediate (negated).  */   OP_MOV_V,		/* MOV alias for moving vector register.  */   OP_ASR_IMM,  OP_LSR_IMM,  OP_LSL_IMM,   OP_BIC,   OP_UBFX,  OP_BFXIL,  OP_SBFX,  OP_SBFIZ,  OP_BFI,  OP_UBFIZ,  OP_UXTB,  OP_UXTH,  OP_UXTW,   OP_CINC,  OP_CINV,  OP_CNEG,  OP_CSET,  OP_CSETM,   OP_FCVT,  OP_FCVTN,  OP_FCVTN2,  OP_FCVTL,  OP_FCVTL2,  OP_FCVTXN_S,		/* Scalar version.  */   OP_ROR_IMM,   OP_SXTL,  OP_SXTL2,  OP_UXTL,  OP_UXTL2,   OP_TOTAL_NUM,		/* Pseudo.  */}; /* Maximum number of operands an instruction can have.  */#define AARCH64_MAX_OPND_NUM 6/* Maximum number of qualifier sequences an instruction can have.  */#define AARCH64_MAX_QLF_SEQ_NUM 10/* Operand qualifier typedef; optimized for the size.  */typedef unsigned char aarch64_opnd_qualifier_t;/* Operand qualifier sequence typedef.  */typedef aarch64_opnd_qualifier_t	\	  aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; /* FIXME: improve the efficiency.  */static inline bfd_booleanempty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers){  int i;  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)    if (qualifiers[i] != AARCH64_OPND_QLF_NIL)      return FALSE;  return TRUE;} /* This structure holds information for a particular opcode.  */ struct aarch64_opcode{  /* The name of the mnemonic.  */  const char *name;   /* The opcode itself.  Those bits which will be filled in with     operands are zeroes.  */  aarch64_insn opcode;   /* The opcode mask.  This is used by the disassembler.  This is a     mask containing ones indicating those bits which must match the     opcode field, and zeroes indicating those bits which need not     match (and are presumably filled in by operands).  */  aarch64_insn mask;   /* Instruction class.  */  enum aarch64_insn_class iclass;   /* Enumerator identifier.  */  enum aarch64_op op;   /* Which architecture variant provides this instruction.  */  const aarch64_feature_set *avariant;   /* An array of operand codes.  Each code is an index into the     operand table.  They appear in the order which the operands must     appear in assembly code, and are terminated by a zero.  */  enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];   /* A list of operand qualifier code sequence.  Each operand qualifier     code qualifies the corresponding operand code.  Each operand     qualifier sequence specifies a valid opcode variant and related     constraint on operands.  */  aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];   /* Flags providing information about this instruction */  uint32_t flags;}; typedef struct aarch64_opcode aarch64_opcode;

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