/* TI C6X opcode table. Copyright 2010-2013 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* Define the INSN macro before including this file; it takes as arguments the fields from tic6x_opcode (defined in tic6x.h). The name is given as an identifier; the subsequent four operands should have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_" and "TIC6X_INSN_", respectively, prepended to them by the macro definition. Also define INSNE, which has a second argument that goes after tic6x_opcode_NAME_ to form the enumeration value for this instruction, where the value otherwise formed from the name, functional unit and format is ambiguous, but otherwise has the same arguments as INSN. */ #define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X#define tic6x_insn_format_nfu_s_branch_nop_cst \ tic6x_insn_format_s_branch_nop_cst#define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src#define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) }#define FIX(id, val) RAN(id, val, val)#define FIX0() 0, { { 0, 0, 0 } }#define FIX1(a) 1, { a }#define FIX2(a, b) 2, { a, b }#define FIX3(a, b, c) 3, { a, b, c }#define FIX4(a, b, c, d) 4, { a, b, c, d }#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } }#define OP1(a) 1, { a }#define OP2(a, b) 2, { a, b }#define OP3(a, b, c) 3, { a, b, c }#define OP4(a, b, c, d) 4, { a, b, c, d }#define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OHWCSTM1 { tic6x_operand_hw_const_minus_1, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OHWCST0 { tic6x_operand_hw_const_0, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OHWCST1 { tic6x_operand_hw_const_1, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OHWCST5 { tic6x_operand_hw_const_5, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OHWCST16 { tic6x_operand_hw_const_16, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OHWCST24 { tic6x_operand_hw_const_24, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OHWCST31 { tic6x_operand_hw_const_31, 0, tic6x_rw_none, 0, 0, 0, 0 }#define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 }#define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 }#define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 }#define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 }#define OWREG1Z { tic6x_operand_zreg, 4, tic6x_rw_write, 1, 1, 0, 0 }#define OWREG1NORS { tic6x_operand_reg_nors, 4, tic6x_rw_write, 1, 1, 0, 0 }#define ORREG1B { tic6x_operand_reg_bside, 4, tic6x_rw_write, 1, 1, 0, 0 }#define ORREG1BNORS { tic6x_operand_reg_bside_nors, 4, tic6x_rw_write, 1, 1, 0, 0 }#define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 }#define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 }#define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 }#define ORTREG1 { tic6x_operand_treg, 4, tic6x_rw_read, 1, 1, 0, 0 }#define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 }#define ORB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_read, 1, 1, 0, 0 }#define OWB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_write, 1, 1, 0, 0 }#define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 }#define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 }#define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 }#define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 }#define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 }#define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 }#define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 }#define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 }#define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 }#define OWTREG5 { tic6x_operand_treg, 4, tic6x_rw_write, 5, 5, 0, 0 }#define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 }#define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 }#define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 }#define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 }#define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 }#define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 }#define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 }#define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 }#define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 }#define ORTREGD1 { tic6x_operand_tregpair, 8, tic6x_rw_read, 1, 1, 1, 1 }#define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 }#define OWTREGD5 { tic6x_operand_tregpair, 8, tic6x_rw_write, 5, 5, 5, 5 }#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 }#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 }#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 }#define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 }#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 }#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 }#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 }#define OWILC1 { tic6x_operand_ilc, 4, tic6x_rw_write, 1, 1, 0, 0 }#define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 }#define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 }#define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 }#define ENC(id, meth, op) { \ CONCAT2(tic6x_field_,id), \ CONCAT2(tic6x_coding_,meth), \ op \ }#define ENC0() 0, { { 0, 0, 0 } }#define ENC1(a) 1, { a }#define ENC2(a, b) 2, { a, b }#define ENC3(a, b, c) 3, { a, b, c }#define ENC4(a, b, c, d) 4, { a, b, c, d }#define ENC5(a, b, c, d, e) 5, { a, b, c, d, e }#define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f }#define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g } INSN(abs, l, unary, 1cycle, C62X, 0, FIX1(FIX(op, 0)), OP2(ORXREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)), OP2(ORREGL1, OWREGL1), ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) INSN(abs2, l, unary, 1cycle, C64X, 0, FIX1(FIX(op, 0x4)), OP2(ORXREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x2c), FIX(x, 0)), OP2(ORREGD1, OWREGD12), ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), ENC(dst, reg, 1))) INSN(abssp, s, unary, 1cycle, C67X, 0, FIX1(FIX(op, 0)), OP2(ORXREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x3)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x23)), OP3(ORREG1, ORXREG1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x21)), OP3(ORXREG1, ORREGL1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x2)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x20), FIX(x, 0)), OP3(OACST, ORREGL1, OWREGL1), ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x7)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x6)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x10)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2)))INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x12)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2)))INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 0xa)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 0xb)), OP3(ORXREG1, OACST, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, scst, 1), ENC(dst, reg, 2))) /* 16 bits insn */INSN(add, l, l3_sat_0, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(add, l, l3i, 1cycle, C64XP, 0, FIX0(), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(cst, scst_l3i, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(add, l, lx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3)), OP3(OHWCSTM1, ORREG1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2)))INSN(add, s, s3_sat_0, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(add, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3)), OP3(OHWCSTM1, ORREG1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2)))INSN(add, s, sx2op, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2), ENC(src2, reg, 1), ENC(x, xpath, 1)))INSN(add, d, dx2op, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 1), ENC(srcdst, reg, 0), ENC(src2, reg, 1), ENC(srcdst, reg, 2)))INSNU(add, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x5), FIX(unit, 0x0)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))INSNU(add, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x5), FIX(unit, 0x1)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))INSNU(add, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x5), FIX(unit, 0x2)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))/**/ INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x30)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2)))INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x32)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2)))INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 3)), OP3(ORAREG1, OLCST, OWREG1), ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1), ENC(dst, reg, 2))) INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3c)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2)))INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3d)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x34)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2)))INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x36)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2)))INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 5)), OP3(ORAREG1, OLCST, OWREG1), ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1), ENC(dst, reg, 2))) INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x38)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2)))INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x3a)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2)))INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 7)), OP3(ORAREG1, OLCST, OWREG1), ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1), ENC(dst, reg, 2))) /* 16 bits insn */INSN(addaw, d, dx5, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, FIX0(), OP3(ORB15REG1, OACST, OWREG1), ENC3(ENC(s, fu, 0), ENC(cst, ucst, 1), ENC(dst, reg, 2)))INSN(addaw, d, dx5p, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, FIX1(FIX(op, 0)), OP3(ORB15REG1, OACST, OWB15REG1), ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1)))/**/ INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0, FIX1(FIX(op, 0x18)), OP3(ORREGD12, ORXREGD12, OWREGD67), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0, FIX1(FIX(op, 0x72)), OP3(ORREGD12, ORXREGD12, OWREGD67), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX0(), OP2(OLCST, OWREG1), ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) /* 16 bits insn */INSN(addk, s, sx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX0(), OP2(OACST, OWREG1), ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1)))/**/ INSN(addkpc, s, addkpc, 1cycle, C64X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY, FIX1(FIX(s, 1)), OP3(OLCST, OWREG1, OACST), ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2))) INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0, FIX1(FIX(op, 0x10)), OP3(ORREG1, ORXREG1, OWREG4), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0, FIX1(FIX(op, 0x70)), OP3(ORREG1, ORXREG1, OWREG4), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, FIX1(FIX(op, 0xc)), OP3(ORREG1, ORXREG1, OWREGD1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, FIX1(FIX(op, 0xd)), OP3(ORREG1, ORXREG1, OWREGD1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x2b)), OP3(ORREG1, ORXREG1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x29)), OP3(ORXREG1, ORREGL1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x1)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x5)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x4)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x65)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x7b)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x7a)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x1f)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x1e)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x6)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x7)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) /* 16 bits insn */INSN(and, l, l2c, 1cycle, C64XP, 0, FIX1(FIX(op, 0)), OP3(ORREG1, ORXREG1, OWREG1NORS), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))/**/ INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x7c)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x6)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2)))INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(avg2, m, compound, 1616_m, C64X, 0, FIX1(FIX(op, 0x13)), OP3(ORREG1, ORXREG1, OWREG2), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(avgu4, m, compound, 1616_m, C64X, 0, FIX1(FIX(op, 0x12)), OP3(ORREG1, ORXREG1, OWREG2), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS, FIX0(), OP1(OLCST), ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY, FIX1(FIX(s, 1)), OP1(ORXREG1),Lines 1–500 of 3677. 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/* TI C6X opcode table. Copyright 2010-2013 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* Define the INSN macro before including this file; it takes as arguments the fields from tic6x_opcode (defined in tic6x.h). The name is given as an identifier; the subsequent four operands should have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_" and "TIC6X_INSN_", respectively, prepended to them by the macro definition. Also define INSNE, which has a second argument that goes after tic6x_opcode_NAME_ to form the enumeration value for this instruction, where the value otherwise formed from the name, functional unit and format is ambiguous, but otherwise has the same arguments as INSN. */ #define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X #define tic6x_insn_format_nfu_s_branch_nop_cst \ tic6x_insn_format_s_branch_nop_cst #define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src #define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) } #define FIX(id, val) RAN(id, val, val) #define FIX0() 0, { { 0, 0, 0 } } #define FIX1(a) 1, { a } #define FIX2(a, b) 2, { a, b } #define FIX3(a, b, c) 3, { a, b, c } #define FIX4(a, b, c, d) 4, { a, b, c, d } #define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } } #define OP1(a) 1, { a } #define OP2(a, b) 2, { a, b } #define OP3(a, b, c) 3, { a, b, c } #define OP4(a, b, c, d) 4, { a, b, c, d } #define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OHWCSTM1 { tic6x_operand_hw_const_minus_1, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OHWCST0 { tic6x_operand_hw_const_0, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OHWCST1 { tic6x_operand_hw_const_1, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OHWCST5 { tic6x_operand_hw_const_5, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OHWCST16 { tic6x_operand_hw_const_16, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OHWCST24 { tic6x_operand_hw_const_24, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OHWCST31 { tic6x_operand_hw_const_31, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 } #define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 } #define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 } #define OWREG1Z { tic6x_operand_zreg, 4, tic6x_rw_write, 1, 1, 0, 0 } #define OWREG1NORS { tic6x_operand_reg_nors, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORREG1B { tic6x_operand_reg_bside, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORREG1BNORS { tic6x_operand_reg_bside_nors, 4, tic6x_rw_write, 1, 1, 0, 0 } #define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORTREG1 { tic6x_operand_treg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 } #define ORB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define OWB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 } #define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 } #define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 } #define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 } #define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 } #define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 } #define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 } #define OWTREG5 { tic6x_operand_treg, 4, tic6x_rw_write, 5, 5, 0, 0 } #define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 } #define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 } #define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 } #define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 } #define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 } #define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 } #define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 } #define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 } #define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 } #define ORTREGD1 { tic6x_operand_tregpair, 8, tic6x_rw_read, 1, 1, 1, 1 } #define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 } #define OWTREGD5 { tic6x_operand_tregpair, 8, tic6x_rw_write, 5, 5, 5, 5 } #define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 } #define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 } #define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 } #define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 } #define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 } #define OWILC1 { tic6x_operand_ilc, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 } #define ENC(id, meth, op) { \ CONCAT2(tic6x_field_,id), \ CONCAT2(tic6x_coding_,meth), \ op \ } #define ENC0() 0, { { 0, 0, 0 } } #define ENC1(a) 1, { a } #define ENC2(a, b) 2, { a, b } #define ENC3(a, b, c) 3, { a, b, c } #define ENC4(a, b, c, d) 4, { a, b, c, d } #define ENC5(a, b, c, d, e) 5, { a, b, c, d, e } #define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f } #define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g } INSN(abs, l, unary, 1cycle, C62X, 0, FIX1(FIX(op, 0)), OP2(ORXREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)), OP2(ORREGL1, OWREGL1), ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) INSN(abs2, l, unary, 1cycle, C64X, 0, FIX1(FIX(op, 0x4)), OP2(ORXREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x2c), FIX(x, 0)), OP2(ORREGD1, OWREGD12), ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0), ENC(dst, reg, 1))) INSN(abssp, s, unary, 1cycle, C67X, 0, FIX1(FIX(op, 0)), OP2(ORXREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x3)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x23)), OP3(ORREG1, ORXREG1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x21)), OP3(ORXREG1, ORREGL1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x2)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x20), FIX(x, 0)), OP3(OACST, ORREGL1, OWREGL1), ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x7)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x6)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x10)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x12)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 0xa)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 0xb)), OP3(ORXREG1, OACST, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, scst, 1), ENC(dst, reg, 2))) /* 16 bits insn */ INSN(add, l, l3_sat_0, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add, l, l3i, 1cycle, C64XP, 0, FIX0(), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(cst, scst_l3i, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add, l, lx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3)), OP3(OHWCSTM1, ORREG1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) INSN(add, s, s3_sat_0, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3)), OP3(OHWCSTM1, ORREG1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) INSN(add, s, sx2op, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2), ENC(src2, reg, 1), ENC(x, xpath, 1))) INSN(add, d, dx2op, 1cycle, C64XP, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 1), ENC(srcdst, reg, 0), ENC(src2, reg, 1), ENC(srcdst, reg, 2))) INSNU(add, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x5), FIX(unit, 0x0)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) INSNU(add, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x5), FIX(unit, 0x1)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) INSNU(add, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x5), FIX(unit, 0x2)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) /**/ INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x30)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x32)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 3)), OP3(ORAREG1, OLCST, OWREG1), ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1), ENC(dst, reg, 2))) INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3c)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x3d)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x34)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x36)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 5)), OP3(ORAREG1, OLCST, OWREG1), ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1), ENC(dst, reg, 2))) INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x38)), OP3(ORREG1, ORREG1, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x3a)), OP3(ORREG1, OACST, OWREG1), ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), FIX1(FIX(op, 7)), OP3(ORAREG1, OLCST, OWREG1), ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1), ENC(dst, reg, 2))) /* 16 bits insn */ INSN(addaw, d, dx5, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, FIX0(), OP3(ORB15REG1, OACST, OWREG1), ENC3(ENC(s, fu, 0), ENC(cst, ucst, 1), ENC(dst, reg, 2))) INSN(addaw, d, dx5p, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, FIX1(FIX(op, 0)), OP3(ORB15REG1, OACST, OWB15REG1), ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1))) /**/ INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0, FIX1(FIX(op, 0x18)), OP3(ORREGD12, ORXREGD12, OWREGD67), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0, FIX1(FIX(op, 0x72)), OP3(ORREGD12, ORXREGD12, OWREGD67), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX0(), OP2(OLCST, OWREG1), ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) /* 16 bits insn */ INSN(addk, s, sx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX0(), OP2(OACST, OWREG1), ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) /**/ INSN(addkpc, s, addkpc, 1cycle, C64X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY, FIX1(FIX(s, 1)), OP3(OLCST, OWREG1, OACST), ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2))) INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0, FIX1(FIX(op, 0x10)), OP3(ORREG1, ORXREG1, OWREG4), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0, FIX1(FIX(op, 0x70)), OP3(ORREG1, ORXREG1, OWREG4), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, FIX1(FIX(op, 0xc)), OP3(ORREG1, ORXREG1, OWREGD1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, FIX1(FIX(op, 0xd)), OP3(ORREG1, ORXREG1, OWREGD1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x2b)), OP3(ORREG1, ORXREG1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x29)), OP3(ORXREG1, ORREGL1, OWREGL1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x1)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x5)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x4)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x65)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x7b)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x7a)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x1f)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x1e)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x6)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x7)), OP3(OACST, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) /* 16 bits insn */ INSN(and, l, l2c, 1cycle, C64XP, 0, FIX1(FIX(op, 0)), OP3(ORREG1, ORXREG1, OWREG1NORS), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) /**/ INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x7c)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x6)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(avg2, m, compound, 1616_m, C64X, 0, FIX1(FIX(op, 0x13)), OP3(ORREG1, ORXREG1, OWREG2), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(avgu4, m, compound, 1616_m, C64X, 0, FIX1(FIX(op, 0x12)), OP3(ORREG1, ORXREG1, OWREG2), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS, FIX0(), OP1(OLCST), ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY, FIX1(FIX(s, 1)), OP1(ORXREG1),