/* mips.h.  Mips opcode list for GDB, the GNU debugger.   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,   2003, 2004, 2005, 2008, 2009, 2010, 2013   Free Software Foundation, Inc.   Contributed by Ralph Campbell and OSF   Commented and modified by Ian Lance Taylor, Cygnus Support    This file is part of GDB, GAS, and the GNU binutils.    GDB, GAS, and the GNU binutils are free software; you can redistribute   them and/or modify them under the terms of the GNU General Public   License as published by the Free Software Foundation; either version 3,   or (at your option) any later version.    GDB, GAS, and the GNU binutils are distributed in the hope that they   will be useful, but WITHOUT ANY WARRANTY; without even the implied   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See   the GNU General Public License for more details.    You should have received a copy of the GNU General Public License   along with this file; see the file COPYING3.  If not, write to the Free   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,   MA 02110-1301, USA.  */ #ifndef _MIPS_H_#define _MIPS_H_ #include "bfd.h" /* These are bit masks and shift counts to use to access the various   fields of an instruction.  To retrieve the X field of an   instruction, use the expression	(i >> OP_SH_X) & OP_MASK_X   To set the same field (to j), use	i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)    Make sure you use fields that are appropriate for the instruction,   of course.    The 'i' format uses OP, RS, RT and IMMEDIATE.    The 'j' format uses OP and TARGET.    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.    The 'b' format uses OP, RS, RT and DELTA.    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the   breakpoint instruction are not defined; Kane says the breakpoint   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers   only use ten bits).  An optional two-operand form of break/sdbbp   allows the lower ten bits to be set too, and MIPS32 and later   architectures allow 20 bits to be set with a signal operand   (using CODE20).    The syscall instruction uses CODE20.    The general coprocessor instructions use COPZ.  */ #define OP_MASK_OP		0x3f#define OP_SH_OP		26#define OP_MASK_RS		0x1f#define OP_SH_RS		21#define OP_MASK_FR		0x1f#define OP_SH_FR		21#define OP_MASK_FMT		0x1f#define OP_SH_FMT		21#define OP_MASK_BCC		0x7#define OP_SH_BCC		18#define OP_MASK_CODE		0x3ff#define OP_SH_CODE		16#define OP_MASK_CODE2		0x3ff#define OP_SH_CODE2		6#define OP_MASK_RT		0x1f#define OP_SH_RT		16#define OP_MASK_FT		0x1f#define OP_SH_FT		16#define OP_MASK_CACHE		0x1f#define OP_SH_CACHE		16#define OP_MASK_RD		0x1f#define OP_SH_RD		11#define OP_MASK_FS		0x1f#define OP_SH_FS		11#define OP_MASK_PREFX		0x1f#define OP_SH_PREFX		11#define OP_MASK_CCC		0x7#define OP_SH_CCC		8#define OP_MASK_CODE20		0xfffff /* 20 bit syscall/breakpoint code.  */#define OP_SH_CODE20		6#define OP_MASK_SHAMT		0x1f#define OP_SH_SHAMT		6#define OP_MASK_EXTLSB		OP_MASK_SHAMT#define OP_SH_EXTLSB		OP_SH_SHAMT#define OP_MASK_STYPE		OP_MASK_SHAMT#define OP_SH_STYPE		OP_SH_SHAMT#define OP_MASK_FD		0x1f#define OP_SH_FD		6#define OP_MASK_TARGET		0x3ffffff#define OP_SH_TARGET		0#define OP_MASK_COPZ		0x1ffffff#define OP_SH_COPZ		0#define OP_MASK_IMMEDIATE	0xffff#define OP_SH_IMMEDIATE		0#define OP_MASK_DELTA		0xffff#define OP_SH_DELTA		0#define OP_MASK_FUNCT		0x3f#define OP_SH_FUNCT		0#define OP_MASK_SPEC		0x3f#define OP_SH_SPEC		0#define OP_SH_LOCC              8       /* FP condition code.  */#define OP_SH_HICC              18      /* FP condition code.  */#define OP_MASK_CC              0x7#define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */#define OP_MASK_COP1NORM        0x1     /* a single bit.  */#define OP_SH_COP1SPEC          21      /* COP1 encodings.  */#define OP_MASK_COP1SPEC        0xf#define OP_MASK_COP1SCLR        0x4#define OP_MASK_COP1CMP         0x3#define OP_SH_COP1CMP           4#define OP_SH_FORMAT            21      /* FP short format field.  */#define OP_MASK_FORMAT          0x7#define OP_SH_TRUE              16#define OP_MASK_TRUE            0x1#define OP_SH_GE                17#define OP_MASK_GE              0x01#define OP_SH_UNSIGNED          16#define OP_MASK_UNSIGNED        0x1#define OP_SH_HINT              16#define OP_MASK_HINT            0x1f#define OP_SH_MMI               0       /* Multimedia (parallel) op.  */#define OP_MASK_MMI             0x3f#define OP_SH_MMISUB            6#define OP_MASK_MMISUB          0x1f#define OP_MASK_PERFREG		0x1f	/* Performance monitoring.  */#define OP_SH_PERFREG		1#define OP_SH_SEL		0	/* Coprocessor select field.  */#define OP_MASK_SEL		0x7	/* The sel field of mfcZ and mtcZ.  */#define OP_SH_CODE19		6       /* 19 bit wait code.  */#define OP_MASK_CODE19		0x7ffff#define OP_SH_ALN		21#define OP_MASK_ALN		0x7#define OP_SH_VSEL		21#define OP_MASK_VSEL		0x1f#define OP_MASK_VECBYTE		0x7	/* Selector field is really 4 bits,					   but 0x8-0xf don't select bytes.  */#define OP_SH_VECBYTE		22#define OP_MASK_VECALIGN	0x7	/* Vector byte-align (alni.ob) op.  */#define OP_SH_VECALIGN		21#define OP_MASK_INSMSB		0x1f	/* "ins" MSB.  */#define OP_SH_INSMSB		11#define OP_MASK_EXTMSBD		0x1f	/* "ext" MSBD.  */#define OP_SH_EXTMSBD		11 /* MIPS DSP ASE */#define OP_SH_DSPACC		11#define OP_MASK_DSPACC  	0x3#define OP_SH_DSPACC_S  	21#define OP_MASK_DSPACC_S	0x3#define OP_SH_DSPSFT		20#define OP_MASK_DSPSFT  	0x3f#define OP_SH_DSPSFT_7  	19#define OP_MASK_DSPSFT_7	0x7f#define OP_SH_SA3		21#define OP_MASK_SA3		0x7#define OP_SH_SA4		21#define OP_MASK_SA4		0xf#define OP_SH_IMM8		16#define OP_MASK_IMM8		0xff#define OP_SH_IMM10		16#define OP_MASK_IMM10		0x3ff#define OP_SH_WRDSP		11#define OP_MASK_WRDSP		0x3f#define OP_SH_RDDSP		16#define OP_MASK_RDDSP		0x3f#define OP_SH_BP		11#define OP_MASK_BP		0x3 /* MIPS MT ASE */#define OP_SH_MT_U		5#define OP_MASK_MT_U		0x1#define OP_SH_MT_H		4#define OP_MASK_MT_H		0x1#define OP_SH_MTACC_T		18#define OP_MASK_MTACC_T		0x3#define OP_SH_MTACC_D		13#define OP_MASK_MTACC_D		0x3 /* MIPS MCU ASE */#define OP_MASK_3BITPOS		0x7#define OP_SH_3BITPOS		12#define OP_MASK_OFFSET12	0xfff#define OP_SH_OFFSET12		0 #define	OP_OP_COP0		0x10#define	OP_OP_COP1		0x11#define	OP_OP_COP2		0x12#define	OP_OP_COP3		0x13#define	OP_OP_LWC1		0x31#define	OP_OP_LWC2		0x32#define	OP_OP_LWC3		0x33	/* a.k.a. pref */#define	OP_OP_LDC1		0x35#define	OP_OP_LDC2		0x36#define	OP_OP_LDC3		0x37	/* a.k.a. ld */#define	OP_OP_SWC1		0x39#define	OP_OP_SWC2		0x3a#define	OP_OP_SWC3		0x3b#define	OP_OP_SDC1		0x3d#define	OP_OP_SDC2		0x3e#define	OP_OP_SDC3		0x3f	/* a.k.a. sd */ /* MIPS VIRT ASE */#define OP_MASK_CODE10		0x3ff#define OP_SH_CODE10		11 /* Values in the 'VSEL' field.  */#define MDMX_FMTSEL_IMM_QH	0x1d#define MDMX_FMTSEL_IMM_OB	0x1e#define MDMX_FMTSEL_VEC_QH	0x15#define MDMX_FMTSEL_VEC_OB	0x16 /* UDI */#define OP_SH_UDI1		6#define OP_MASK_UDI1		0x1f#define OP_SH_UDI2		6#define OP_MASK_UDI2		0x3ff#define OP_SH_UDI3		6#define OP_MASK_UDI3		0x7fff#define OP_SH_UDI4		6#define OP_MASK_UDI4		0xfffff /* Octeon */#define OP_SH_BBITIND		16#define OP_MASK_BBITIND		0x1f#define OP_SH_CINSPOS		6#define OP_MASK_CINSPOS		0x1f#define OP_SH_CINSLM1		11#define OP_MASK_CINSLM1		0x1f#define OP_SH_SEQI		6#define OP_MASK_SEQI		0x3ff /* Loongson */#define OP_SH_OFFSET_A		6#define OP_MASK_OFFSET_A	0xff#define OP_SH_OFFSET_B		3#define OP_MASK_OFFSET_B	0xff#define OP_SH_OFFSET_C		6#define OP_MASK_OFFSET_C	0x1ff#define OP_SH_RZ		0#define OP_MASK_RZ		0x1f#define OP_SH_FZ		0#define OP_MASK_FZ		0x1f /* Every MICROMIPSOP_X definition requires a corresponding OP_X   definition, and vice versa.  This simplifies various parts   of the operand handling in GAS.  The fields below only exist   in the microMIPS encoding, so define each one to have an empty   range.  */#define OP_MASK_TRAP		0#define OP_SH_TRAP		0#define OP_MASK_OFFSET10	0#define OP_SH_OFFSET10		0#define OP_MASK_RS3		0#define OP_SH_RS3		0#define OP_MASK_MB		0#define OP_SH_MB		0#define OP_MASK_MC		0#define OP_SH_MC		0#define OP_MASK_MD		0#define OP_SH_MD		0#define OP_MASK_ME		0#define OP_SH_ME		0#define OP_MASK_MF		0#define OP_SH_MF		0#define OP_MASK_MG		0#define OP_SH_MG		0#define OP_MASK_MH		0#define OP_SH_MH		0#define OP_MASK_MJ		0#define OP_SH_MJ		0#define OP_MASK_ML		0#define OP_SH_ML		0#define OP_MASK_MM		0#define OP_SH_MM		0#define OP_MASK_MN		0#define OP_SH_MN		0#define OP_MASK_MP		0#define OP_SH_MP		0#define OP_MASK_MQ		0#define OP_SH_MQ		0#define OP_MASK_IMMA		0#define OP_SH_IMMA		0#define OP_MASK_IMMB		0#define OP_SH_IMMB		0#define OP_MASK_IMMC		0#define OP_SH_IMMC		0#define OP_MASK_IMMF		0#define OP_SH_IMMF		0#define OP_MASK_IMMG		0#define OP_SH_IMMG		0#define OP_MASK_IMMH		0#define OP_SH_IMMH		0#define OP_MASK_IMMI		0#define OP_SH_IMMI		0#define OP_MASK_IMMJ		0#define OP_SH_IMMJ		0#define OP_MASK_IMML		0#define OP_SH_IMML		0#define OP_MASK_IMMM		0#define OP_SH_IMMM		0#define OP_MASK_IMMN		0#define OP_SH_IMMN		0#define OP_MASK_IMMO		0#define OP_SH_IMMO		0#define OP_MASK_IMMP		0#define OP_SH_IMMP		0#define OP_MASK_IMMQ		0#define OP_SH_IMMQ		0#define OP_MASK_IMMU		0#define OP_SH_IMMU		0#define OP_MASK_IMMW		0#define OP_SH_IMMW		0#define OP_MASK_IMMX		0#define OP_SH_IMMX		0#define OP_MASK_IMMY		0#define OP_SH_IMMY		0 /* Enhanced VA Scheme */#define OP_SH_EVAOFFSET		7#define OP_MASK_EVAOFFSET	0x1ff /* Enumerates the various types of MIPS operand.  */enum mips_operand_type {  /* Described by mips_int_operand.  */  OP_INT,   /* Described by mips_mapped_int_operand.  */  OP_MAPPED_INT,   /* Described by mips_msb_operand.  */  OP_MSB,   /* Described by mips_reg_operand.  */  OP_REG,   /* Like OP_REG, but can be omitted if the register is the same as the     previous operand.  */  OP_OPTIONAL_REG,   /* Described by mips_reg_pair_operand.  */  OP_REG_PAIR,   /* Described by mips_pcrel_operand.  */  OP_PCREL,   /* A performance register.  The field is 5 bits in size, but the supported     values are much more restricted.  */  OP_PERF_REG,   /* The final operand in a microMIPS ADDIUSP instruction.  It mostly acts     as a normal 9-bit signed offset that is multiplied by four, but there     are four special cases:      -2 * 4 => -258 * 4     -1 * 4 => -257 * 4      0 * 4 =>  256 * 4      1 * 4 =>  257 * 4.  */  OP_ADDIUSP_INT,   /* The target of a (D)CLO or (D)CLZ instruction.  The operand spans two     5-bit register fields, both of which must be set to the destination     register.  */  OP_CLO_CLZ_DEST,   /* A register list for a microMIPS LWM or SWM instruction.  The operand     size determines whether the 16-bit or 32-bit encoding is required.  */  OP_LWM_SWM_LIST,   /* The register list for an emulated MIPS16 ENTRY or EXIT instruction.  */  OP_ENTRY_EXIT_LIST,   /* The register list and frame size for a MIPS16 SAVE or RESTORE     instruction.  */  OP_SAVE_RESTORE_LIST,   /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:      V      Meaning     -----  -------     0EEE0  8 copies of $vN[E], OB format     0EE01  4 copies of $vN[E], QH format     10110  all 8 elements of $vN, OB format     10101  all 4 elements of $vN, QH format     11110  8 copies of immediate N, OB format     11101  4 copies of immediate N, QH format.  */  OP_MDMX_IMM_REG,   /* A register operand that must match the destination register.  */  OP_REPEAT_DEST_REG,   /* A register operand that must match the previous register.  */  OP_REPEAT_PREV_REG,   /* $pc, which has no encoding in the architectural instruction.  */  OP_PC,   /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines     which.  */  OP_VU0_SUFFIX,   /* Like OP_VU0_SUFFIX, but used when the operand's value has already     been set.  Any suffix used here must match the previous value.  */  OP_VU0_MATCH_SUFFIX}; /* Enumerates the types of MIPS register.  */enum mips_reg_operand_type {  /* General registers $0-$31.  Software names like $at can also be used.  */  OP_REG_GP,   /* Floating-point registers $f0-$f31.  */  OP_REG_FP,   /* Coprocessor condition code registers $cc0-$cc7.  FPU condition codes     can also be written $fcc0-$fcc7.  */  OP_REG_CCC,   /* FPRs used in a vector capacity.  They can be written $f0-$f31     or $v0-$v31, although the latter form is not used for the VR5400     vector instructions.  */  OP_REG_VEC,   /* DSP accumulator registers $ac0-$ac3.  */  OP_REG_ACC,   /* Coprocessor registers $0-$31.  Mnemonic names like c0_cause can     also be used in some contexts.  */  OP_REG_COPRO,   /* Hardware registers $0-$31.  Mnemonic names like hwr_cpunum can     also be used in some contexts.  */  OP_REG_HW,   /* Floating-point registers $vf0-$vf31.  */  OP_REG_VF,   /* Integer registers $vi0-$vi31.  */  OP_REG_VI,   /* R5900 VU0 registers $I, $Q, $R and $ACC.  */  OP_REG_R5900_I,  OP_REG_R5900_Q,  OP_REG_R5900_R,  OP_REG_R5900_ACC}; /* Base class for all operands.  */struct mips_operand{  /* The type of the operand.  */  enum mips_operand_type type;   /* The operand occupies SIZE bits of the instruction, starting at LSB.  */  unsigned short size;  unsigned short lsb;}; /* Describes an integer operand with a regular encoding pattern.  */struct mips_int_operand{  struct mips_operand root;   /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.     The cyclically previous field value encodes 1 << SHIFT less than that,     and so on.  E.g.      - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,       but 15 encodes -1.      - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is       shifted left two places.      - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except       that 0 encodes 8.      - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3.  */  unsigned int max_val;  int bias;  unsigned int shift;   /* True if the operand should be printed as hex rather than decimal.  */  bfd_boolean print_hex;}; /* Uses a lookup table to describe a small integer operand.  */struct mips_mapped_int_operand{

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