; Adapteva EPIPHANY CPU description. -*- Scheme -*-; Copyright 1998, 1999, 2000, 2001, 2003, 2006, 2007, 2008, 2009, 2010, 2011; Free Software Foundation, Inc.;; Contributed by Embecosm on behalf of Adapteva, Inc.; This file is part of the GNU Binutils and of GDB.;; This program is free software; you can redistribute it and/or modify; it under the terms of the GNU General Public License as published by; the Free Software Foundation; either version 3 of the License, or; (at your option) any later version.;; This program is distributed in the hope that it will be useful,; but WITHOUT ANY WARRANTY; without even the implied warranty of; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License; along with this program; if not, write to the Free Software; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,; MA 02110-1301, USA. (include "simplify.inc")					; define-arch must appear first (define-arch  (name epiphany) ; name of cpu family  (comment "Adapteva, Inc. EPIPHANY family")  (default-alignment aligned)  (insn-lsb0? #t) 					; - a 16/32 bit instruction machine (the default)   (machs epiphany32)  (isas epiphany)  ) 					; Attributes. (define-attr  (for insn)  (type boolean)  (name SHORT-INSN)  (comment "instruction is a 16 bit form")  ) ;; 3 bit add/sub immediate forms - useful for relaxing into 11 bit form(define-attr  (for insn)  (type boolean)  (name IMM3)  (comment "instruction has a 3 bit immediate form")  ) ;; 8 bit mov immediate forms - useful for relaxing into 16 bit form(define-attr  (for insn)  (type boolean)  (name IMM8)  (comment "instruction has a 8 bit immediate form")  ) 					; Instruction set parameters. (define-isa  (name epiphany)  (comment "Adapteva, Inc. EPIPHANY32 ISA")   (default-insn-word-bitsize 32)  (default-insn-bitsize 32)  (base-insn-bitsize 32)  (decode-assist (3 2 1 0))  ; CGEN can figure this out  (liw-insns 1)				; # instructions fetched at once  ) 					; Cpu family definitions.  (define-cpu					; cpu names must be distinct from the architecture name and machine names.  (name epiphanybf)  (comment "Adapteva, Inc. EPIPHANY Family")  (endian little)  (word-bitsize 32)  ) (define-cpu  (name epiphanymf)  (comment "Adapteva, Inc. EPIPHANY Family")  (endian little)  (word-bitsize 32)  )  (define-mach  (name epiphany32)  (comment "Adapteva EPIPHANY")  (cpu epiphanybf)  )  					; Model descriptions. (define-model  (name epiphany32) (comment "Adapteva EPIPHANY 32/16") (attrs)  (mach epiphany32)   (unit u-exec "Execution Unit" ()	1 1 ; issue done	() ; state	() ; inputs	() ; outputs	() ; profile action (default)	)  )   					; Instruction fields.					;					; Attributes:					; XXX: what EPIPHANY attrs					; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)					; ABS-ADDR: absolute address (for reloc and disassembly purposes?)					; RESERVED: bits are not used to decode insn, must be all 0					; RELOC: there is a relocation associated with this field (define-attr  (for ifield operand)  (type boolean)  (name RELOC)  (comment "there is a reloc associated with this field (experiment)")  ) ;; define the fields of the instruction.;;   name            description              ATTR  MSB LEN(dnf f-opc	  "primary opcode"	       ()     3 4)(dnf f-opc-4-1    "secondary opcode"           ()     4 1)(dnf f-opc-6-3    "secondary opcode"           ()     6 3) ;;(dnf f-opc-8-5    "tertiary opcode"            ()     8 5) ;;(dnf f-opc-19-4   "additional opcode bits"     ()    19 4)(dnf f-condcode   "condition codes" 	       ()     7 4)(dnf f-secondary-ccs "flag for secondary ccs"  ()     7 1)(dnf f-shift      "shift amount"               ()     9 5)(dnf f-wordsize   "load/store size"            ()     6 2)(dnf f-store      "load/store flag"            ()     4 1) ;; 0==load,1==store(dnf f-opc-8-1    "opcode bits"                ()     8 1)(dnf f-opc-31-32  "all opcode set"             ()     31 32) (df f-simm8	  "branch displacement"   (PCREL-ADDR RELOC) 15 8 INT    ((value pc) (sra SI (sub SI value pc) 1))    ((value pc) (add SI (mul SI value 2) pc))) (df f-simm24     "branch displacement"	  (PCREL-ADDR RELOC) 31 24 INT    ((value pc) (sra SI (sub SI value pc) 1))    ((value pc) (add SI (mul SI value 2) pc))) (df f-sdisp3     "signed immediate 3 bit"      ()     9 3  INT #f #f) (dnf f-disp3      "address offset"             ()     9 3)(dnf f-disp8      "address offset"             ()    23 8) (dnf f-imm8      "move/add/sub imm8"           ()    12 8)(dnf f-imm-27-8  "move/add/sub imm16"          ()    27 8)(dnf f-addsubx   "+/- index address"           ()    20 1)(dnf f-subd      "+/- displ address"           ()    24 1)(dnf f-pm        "post-modify immediate"       ()    25 1) (dnf f-rm        "short rm"                    ()     9 3)   ;; RM(dnf f-rn        "short rn"                    ()    12 3)   ;; RN(dnf f-rd        "short rd"                    ()    15 3)   ;; RD (dnf f-rm-x       "extension rm"               ()    25 3)   ;; RM(dnf f-rn-x       "extension rn"               ()    28 3)   ;; RN(dnf f-rd-x       "extension rd"               ()    31 3)   ;; RD (dnf f-dc-9-1     "DC"                 (RESERVED)     9 1) (dnf f-sn        "short sn"                    ()    12 3)   ;; SN(dnf f-sd        "short sd"                    ()    15 3)   ;; SD (dnf f-sn-x       "extension sn"               ()    28 3)   ;; SN(dnf f-sd-x       "extension sd"               ()    31 3)   ;; SD   (dnf f-dc-7-4     "movts zeros"                 ()     7 4)(dnf f-trap-swi-9-1     "trap or swi"                 ()     9 1)(dnf f-gien-gidis-9-1     "gien or gidis"                 ()     9 1)  (dnf f-dc-15-3    "DC"                 (RESERVED)    15 3)(dnf f-dc-15-7    "DC"                 (RESERVED)    15 7)(dnf f-dc-15-6    "DC"                 ()            15 6)(dnf f-trap-num   "trap number"                ()    15 6) (dnf f-dc-20-1    "DC"                 (RESERVED)    20 1) (dnf f-dc-21-1    "DC"                 (RESERVED)    21 1)(dnf f-dc-21-2    "DC"                 (RESERVED)    21 2) (dnf f-dc-22-3    "DC"                 (RESERVED)    22 3)(dnf f-dc-22-2    "DC"                 (RESERVED)    22 2)(dnf f-dc-22-1    "DC"                 (RESERVED)    22 1) (dnf f-dc-25-6    "DC"                 (RESERVED)    25 6)(dnf f-dc-25-4    "DC"                 (RESERVED)    25 4)(dnf f-dc-25-2    "DC"                 (RESERVED)    25 2)(dnf f-dc-25-1    "DC"                 (RESERVED)    25 1) (dnf f-dc-28-1    "DC"                 (RESERVED)    28 1)(dnf f-dc-31-3    "DC"                 (RESERVED)    31 3) (dnmf f-disp11 "Unsigned offset for load/store" () UINT (f-disp3 f-disp8)      (sequence ()		(set (ifield f-disp8) (and (srl (ifield f-disp11) 3) (const 255)))		(set (ifield f-disp3) (and (ifield f-disp11) 7)))      (sequence ()		(set (ifield f-disp11) (or (sll (ifield f-disp8) 3)					   (ifield f-disp3)))		)      )  (dnmf f-sdisp11 "Signed offset for load/store" () INT (f-disp3 f-disp8)      (sequence ()			;encode		(set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3)))		(set (ifield f-disp3)  (and SI (ifield f-sdisp11) 7)))      (sequence ()			;decode		(set (ifield f-sdisp11)		     (sub SI (xor (and (or (sll (ifield f-disp8) 3)					   (ifield f-disp3))				       #x7ff)				  #x400)			  #x400)))      ) (dnmf f-imm16 "Short immediate for move/add/sub" () UINT (f-imm8 f-imm-27-8)      (sequence ()		(set (ifield f-imm8) (and (ifield f-imm16) #xff))		(set (ifield f-imm-27-8) (srl (ifield f-imm16) 8)))      (sequence ()		(set (ifield f-imm16) (or (sll (ifield f-imm-27-8) 8)					  (ifield f-imm8))))      )  ;; 32 bit instructions have the register number broken into two non-contiguous fields (define-pmacro (x-reg-field reg)  (define-multi-ifield    (name (.sym "f-" reg "6"))    (mode UINT)    (subfields (.sym "f-" reg "-x") (.sym "f-" reg))    (insert (sequence ()		      (set (ifield (.sym "f-" reg))   (and (ifield (.sym "f-" reg "6"))							   (const 7)))		      (set (ifield (.sym "f-" reg "-x"))  (srl (ifield (.sym "f-" reg "6"))							       (const 3)))		      ))    (extract (sequence ()		       (set (ifield (.sym "f-" reg "6")) (or (sll (ifield (.sym "f-" reg "-x"))								  (const 3))							     (ifield (.sym "f-" reg))))		       ))    )  ) (x-reg-field rd)			; f-rd6(x-reg-field rn)			; f-rn6(x-reg-field rm)			; f-rm6(x-reg-field sd)			; f-sd6(x-reg-field sn)			; f-sn6  ;;;;;;;;;;					; Enums. ;;;;;;;;;;; 					; insn-opc: bits 3..0 - major family selector(define-normal-insn-enum insn-opc "opc enums" () OP4_ f-opc  (   BRANCH16  ;; 0000   LDSTR16X  ;; 0001   FLOW16    ;; 0010   IMM16     ;; 0011   LDSTR16D  ;; 0100   LDSTR16P  ;; 0101   LSHIFT16  ;; 0110 - logical shift   DSP16     ;; 0111 - 3 reg DSP 16 bit insns   BRANCH    ;; 1000   LDSTRX    ;; 1001   ALU16     ;; 1010 - 3 reg 16 bit   IMM32     ;; 1011   LDSTRD    ;; 1100   LDSTRP    ;; 1101   ASHIFT16  ;; 1110   ASR, BITR   MISC      ;; 1111 - 32 bit shifts, 3 reg ALU, 3 reg DSP, FLOW, BITR   )  ) (define-normal-insn-enum insn-wordsize "memory access width" () OPW_ f-wordsize					; specifies the size of a memory load/store operation  (BYTE SHORT WORD DOUBLE)  ) (define-normal-insn-enum insn-memory-access "memory access direction" () OP_ f-store					; load=0, store=1  (LOAD STORE)  ) 					; enum for trap codes used by simulator(define-normal-insn-enum trap-codes "trap instruction dispatch code" () TRAP_ f-trap-num  (write read open exit pass fail close other)  ) 					; cond branch: bits 7..4					;(define-normal-insn-enum insn-cond "branch conditions" () OPC_ f-condcode  (EQ NE GTU GTEU LTEU LTU GT GTE LT LTE BEQ BNE BLT BLTE B BL)) 					; dsp 3 operand opcodes(define-normal-insn-enum insn-bop "binary operator subcodes" () OPB_ f-opc-6-3  (EOR ADD LSL SUB LSR AND ASR ORR)) 					; dsp 3 operand opcodes(define-normal-insn-enum insn-bopext "binary operator subcodes" () OPBE_ f-opc-6-3  (FEXT FDEP LFSR - - - - -))  (define-normal-insn-enum insn-fop "floating operators" () OPF_ f-opc-6-3  (ADD SUB MUL MADD MSUB FLOAT FIX FABS)) (define-normal-insn-enum insn-fopexn "extended floating operators" () OPF_ f-opc-6-3  (FRECIP FSQRT - - - - - -))    ; Immediate operation secondary opcodes(define-normal-insn-enum insn-immop "immediate operators" () OPI_ f-opc-6-3  (- ADD - SUB - - - TRAP) ; TRAP is special extension for simulator  ) 					; don't care fields(define-normal-insn-enum insn-dc-25-2 "don't cares" () OPI_25_2_ f-dc-25-2  (MBZ)) ; General Register keyword names.(define-keyword  (name gr-names)  (print-name h-registers)  (prefix "")  (values; some preferred aliases   (fp 11) (sp 13) (lr 14); the default register names   (r0  0)  (r1  1)  (r2  2)  (r3  3)  (r4  4)  (r5  5)  (r6  6)  (r7  7)   (r8  8)  (r9  9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)   (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) (r21 21) (r22 22) (r23 23)   (r24 24) (r25 25) (r26 26) (r27 27) (r28 28) (r29 29) (r30 30) (r31 31)   (r32 32) (r33 33) (r34 34) (r35 35) (r36 36) (r37 37) (r38 38) (r39 39)   (r40 40) (r41 41) (r42 42) (r43 43) (r44 44) (r45 45) (r46 46) (r47 47)   (r48 48) (r49 49) (r50 50) (r51 51) (r52 52) (r53 53) (r54 54) (r55 55)   (r56 56) (r57 57) (r58 58) (r59 59) (r60 60) (r61 61) (r62 62) (r63 63); some less popular aliases   (a1  0) (a2  1) (a3  2) (a4  3) (v1  4) (v2  5) (v3  6) (v4  7)   (v5  8) (v6  9) (v7 10) (v8 11)   (sb 9) (sl 10) (ip 12)   )  ) (define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC)) (define-normal-insn-enum disp-post-modify "postmodify displacement" () PMOD_ f-pm (DISP POST));;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;					; Hardware pieces.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; 64 general-purpose registers(define-hardware  (name h-registers)  (comment "all addressable registers")  (type register SI (64))  (attrs PROFILE CACHE-ADDR)  (indices extern-keyword gr-names)  )   ;; Same 64 registers as floating point registers(define-hardware  (name h-fpregisters)  (comment "all GPRs as float values")  (type register SF (64))  (attrs PROFILE VIRTUAL)  (indices extern-keyword gr-names)  (get (index) (subword SF (reg h-registers index) 0))  (set (index newval) (set (reg h-registers index) (subword SI newval 0)))  ) ;; define processor status bits as physical hardware (define-pmacro (psw-h-bit name cmt)  (dsh name cmt () (register BI))) (psw-h-bit h-zbit "integer zero bit")(psw-h-bit h-nbit "integer neg bit")(psw-h-bit h-cbit "integer carry bit")(psw-h-bit h-vbit "integer overflow bit")(psw-h-bit h-vsbit "integer overflow sticky")  (psw-h-bit h-bzbit "floating point zero bit")(psw-h-bit h-bnbit "floating point neg bit")(psw-h-bit h-bvbit "floating point ovfl bit")(psw-h-bit h-bubit "floating point underfl bit")(psw-h-bit h-bibit "floating point invalid bit")(psw-h-bit h-bcbit "floating point carry bit") (psw-h-bit h-bvsbit "floating point overflow sticky")(psw-h-bit h-bisbit  "floating point invalid sticky")(psw-h-bit h-busbit  "floating point underflow sticky") (psw-h-bit h-expcause0bit  "exceprion cause bit0")(psw-h-bit h-expcause1bit  "exceprion cause bit1")(psw-h-bit h-expcause2bit  "external load stalled bit")(psw-h-bit h-extFstallbit  "external fetch stalled bit") (psw-h-bit h-trmbit  "0=round to nearest, 1=trunacte select bit")(psw-h-bit h-invExcEnbit  "invalid exception enable bit")(psw-h-bit h-ovfExcEnbit  "overflow exception enable bit")(psw-h-bit h-unExcEnbit  "underflow exception enablebit ") (psw-h-bit h-timer0bit0  "timer 0 mode selection 0")(psw-h-bit h-timer0bit1  "timer 0 mode selection 1")(psw-h-bit h-timer0bit2  "timer 0 mode selection 2")(psw-h-bit h-timer0bit3  "timer 0 mode selection 3")(psw-h-bit h-timer1bit0  "timer 1 mode selection 0")(psw-h-bit h-timer1bit1  "timer 1 mode selection 1")(psw-h-bit h-timer1bit2  "timer 1 mode selection 2")(psw-h-bit h-timer1bit3  "timer 1 mode selection 3") (psw-h-bit h-mbkptEnbit  "multicore bkpt enable")(psw-h-bit h-clockGateEnbit  "clock gating enable bkpt enable")  (psw-h-bit h-coreCfgResBit12 "core config bit 12")(psw-h-bit h-coreCfgResBit13 "core config bit 13")(psw-h-bit h-coreCfgResBit14 "core config bit 14")(psw-h-bit h-coreCfgResBit15 "core config bit 15")(psw-h-bit h-coreCfgResBit16 "core config bit 16")  (psw-h-bit h-coreCfgResBit20 "core config bit 20")(psw-h-bit h-coreCfgResBit21 "core config bit 21") (psw-h-bit h-coreCfgResBit24 "core config bit 24")(psw-h-bit h-coreCfgResBit25 "core config bit 25")(psw-h-bit h-coreCfgResBit26 "core config bit 26")(psw-h-bit h-coreCfgResBit27 "core config bit 27")(psw-h-bit h-coreCfgResBit28 "core config bit 28")(psw-h-bit h-coreCfgResBit29 "core config bit 29")(psw-h-bit h-coreCfgResBit30 "core config bit 30")(psw-h-bit h-coreCfgResBit31 "core config bit 31")  (psw-h-bit h-arithmetic-modebit0  "arithmetic mode bit0")(psw-h-bit h-arithmetic-modebit1  "arithmetic mode bit1")(psw-h-bit h-arithmetic-modebit2  "arithmetic mode bit2")  (psw-h-bit h-gidisablebit "global interrupt disable bit")(psw-h-bit h-kmbit "kernel mode bit")(psw-h-bit h-caibit "core active indicator mode bit")(psw-h-bit h-sflagbit "sflag bit")  					; Define operands for each of the physical bits(define-pmacro (psw-bit name hname cmt)  (dnop name cmt (SEM-ONLY) hname f-nil)  ) (psw-bit zbit h-zbit "integer zero bit")(psw-bit nbit h-nbit "integer neg bit")(psw-bit cbit h-cbit "integer carry bit")(psw-bit vbit h-vbit "integer overflow bit") (psw-bit bzbit  h-bzbit "floating point zero bit")(psw-bit bnbit  h-bnbit "floating point neg bit")(psw-bit bvbit  h-bvbit "floating point ovfl bit")(psw-bit bcbit  h-bcbit "floating point carry bit") (psw-bit bubit h-bubit "floating point underfl bit")(psw-bit bibit h-bibit "floating point invalid bit")  (psw-bit vsbit  h-vsbit  "integer overflow sticky")(psw-bit bvsbit h-bvsbit "floating point overflow sticky")

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