; Toshiba MeP Media Engine architecture description. -*- Scheme -*-; Copyright 2011 Free Software Foundation, Inc.;; Contributed by Red Hat Inc;;; This file is part of the GNU Binutils.;; This program is free software; you can redistribute it and/or modify; it under the terms of the GNU General Public License as published by; the Free Software Foundation; either version 3 of the License, or; (at your option) any later version.;; This program is distributed in the hope that it will be useful,; but WITHOUT ANY WARRANTY; without even the implied warranty of; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License; along with this program; if not, write to the Free Software; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,; MA 02110-1301, USA. (include "simplify.inc") (define-pmacro isa-enum () (isas mep ; begin-isa-enum ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64; end-isa-enum )) (define-arch (name mep) (comment "Toshiba MeP Media Engine") (insn-lsb0? #f) ;; work around cgen limitation (machs mep h1 c5) isa-enum) (define-isa (name mep) (comment "MeP core instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32)) ; begin-isas(define-isa (name ext_core1) (comment "MeP core extension instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32)) (define-isa (name ext_cop1_16) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32)) (define-isa (name ext_cop1_32) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32)) (define-isa (name ext_cop1_48) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32)) (define-isa (name ext_cop1_64) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32)) (define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) (define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32)) (define-pmacro all-core-isa-list () mep,ext_core1); end-isas (define-cpu (name mepf) (comment "MeP family") (endian either) (insn-chunk-bitsize 16) (word-bitsize 32)) (define-mach (name mep) (comment "MeP media engine") (cpu mepf) isa-enum) (define-mach (name h1) (comment "H1 media engine") (cpu mepf) isa-enum) (define-mach (name c5) (comment "C5 media engine") (cpu mepf) isa-enum) (define-model (name mep) (comment "MeP media engine processor") (mach c5) ; mach gets changed by MeP-Integrator (unit u-exec "execution unit" () 1 1 ; issue done () () () ()) ; Branch unit (unit u-branch "Branch Unit" () 0 0 ; issue done () ; state () ; inputs ((pc)) ; outputs () ; profile action (default) ) ; Multiply unit (unit u-multiply "Multiply Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Divide unit (unit u-divide "Divide Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Stcb unit (unit u-stcb "stcb Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Ldcb unit (unit u-ldcb "ldcb Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Load gpr unit (unit u-load-gpr "Load into GPR Unit" () 0 0 ; issue done () ; state () ; inputs ((loadreg INT -1)) ; outputs () ; profile action (default) ) (unit u-ldcb-gpr "Ldcb into GPR Unit" () 0 0 ; issue done () ; state () ; inputs ((loadreg INT -1)) ; outputs () ; profile action (default) ) ; Multiply into GPR unit (unit u-mul-gpr "Multiply into GPR Unit" () 0 0 ; issue done () ; state () ; inputs ((resultreg INT -1)) ; outputs () ; profile action (default) ) ; Use gpr unit -- stalls if GPR not ready (unit u-use-gpr "Use GPR Unit" () 0 0 ; issue done () ; state ((usereg INT -1)) ; inputs () ; outputs () ; profile action (default) ) ; Use ctrl-reg unit -- stalls if CTRL-REG not ready (unit u-use-ctrl-reg "Use CTRL-REG Unit" () 0 0 ; issue done () ; state ((usereg INT -1)) ; inputs () ; outputs () ; profile action (default) ) ; Store ctrl-reg unit -- stalls if CTRL-REG not ready (unit u-store-ctrl-reg "Store CTRL-REG Unit" () 0 0 ; issue done () ; state () ; inputs ((storereg INT -1)) ; outputs () ; profile action (default) )) ; Hardware elements. (dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ()) (define-hardware (name h-gpr) (comment "General purpose registers") (attrs all-mep-isas CACHE-ADDR PROFILE) (type register SI (16)) (indices keyword "$" (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) ; "$8" is the preferred name for register 8, but "$tp", "$gp" ; and "$sp" are preferred for their respective registers. (fp 8) (tp 13) (gp 14) (sp 15) ("12" 12) ("13" 13) ("14" 14) ("15" 15)))) (define-hardware (name h-csr) (comment "Control/special registers") (attrs all-mep-isas PROFILE) (type register SI (32)) (indices keyword "$" ((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6) (hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15) (psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21) (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28); begin-extra-csr-registers (vid 22); end-extra-csr-registers )) (get (index) (c-call SI "cgen_get_csr_value" index)) (set (index newval) (c-call VOID "cgen_set_csr_value" index newval))) (define-pmacro (-reg-pair n) ((.sym n) n))(define-hardware (name h-cr64) (comment "64-bit coprocessor registers") (attrs all-mep-isas) ; This assumes that the data path of the co-pro is 64 bits. (type register DI (32)) (indices keyword "$c" (.map -reg-pair (.iota 32))) (set (index newval) (c-call VOID "h_cr64_queue_set" index newval)))(define-hardware (name h-cr64-w) (comment "64-bit coprocessor registers, pending writes") (attrs all-mep-isas) ; This assumes that the data path of the co-pro is 64 bits. (type register DI (32))) (define-hardware (name h-cr) (comment "32-bit coprocessor registers") (attrs all-mep-isas VIRTUAL) (type register SI (32)) (indices keyword "$c" (.map -reg-pair (.iota 32))) (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) (get (index) (trunc SI (c-call DI "h_cr64_get" index)))) ;; Given a coprocessor control register number N, expand to a;; name/index pair: ($ccrN N)(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n)) (define-hardware (name h-ccr) (comment "Coprocessor control registers") (attrs all-mep-isas) (type register SI (64)) (indices keyword "" (.map -ccr-reg-pair (.iota 64))) (set (index newval) (c-call VOID "h_ccr_queue_set" index newval)))(define-hardware (name h-ccr-w) (comment "Coprocessor control registers, pending writes") (attrs all-mep-isas) (type register SI (64))) ; Instruction fields. Bit numbering reversed. ; Conventions:;; N = number of bits in value; A = alignment (2 or 4, omit for 1); B = leftmost (i.e. closest to zero) bit position;; -- Generic Fields (f-*) --; N number of bits in *value* (1-24); [us] signed vs unsigned; B position of left-most bit (4-16); aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc); n opt. for noncontiguous fields; f-foo-{hi,lo} msb/lsb parts of field f-foo;; -- Operands --; pcrelNaA PC-relative branch target (signed); pcabsNaA Absolute branch target (unsigned);; [us]dispNaA [un]signed displacement; [us]immN [un]signed immediate value; addrNaA absolute address (unsigned);; Additional prefixes may be used for special cases. (dnf f-major "major opcode" (all-mep-core-isas) 0 4) (dnf f-rn "register n" (all-mep-core-isas) 4 4)(dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3)(dnf f-rm "register m" (all-mep-core-isas) 8 4)(dnf f-rl "register l" (all-mep-core-isas) 12 4)(dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2)(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3)(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4)(dnf f-ext "extended field" (all-mep-core-isas) 16 8)(dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4)(dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2)(dnf f-crn "copro register n" (all-mep-core-isas) 4 4) (df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)(df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f)(define-multi-ifield (name f-csrn) (comment "control reg") (attrs all-mep-core-isas) (mode UINT) (subfields f-csrn-hi f-csrn-lo) (insert (sequence () (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf)) (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4)))) (extract (set (ifield f-csrn) (or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo)))) ) (df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f)(df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f)(define-multi-ifield (name f-crnx) (comment "copro register n (0-31)") (attrs all-mep-core-isas) (mode UINT) (subfields f-crnx-hi f-crnx-lo) (insert (sequence () (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf)) (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4)))) (extract (set (ifield f-crnx) (or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo)))) ) ; Miscellaneous fields. (define-pmacro (dnfb n) (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1)) ; Define small fields used throughout the instruction set description.; Each field (eg. `f-N') is at single bit field at position N. (dnfb 0)(dnfb 1)(dnfb 2)(dnfb 3)(dnfb 4)(dnfb 5)(dnfb 6)(dnfb 7)(dnfb 8)(dnfb 9)(dnfb 10)(dnfb 11)(dnfb 12)(dnfb 13)(dnfb 14)(dnfb 15)(dnfb 16)(dnfb 17)(dnfb 18)(dnfb 19)(dnfb 20)(dnfb 21)(dnfb 22)(dnfb 23)(dnfb 24)(dnfb 25)(dnfb 26)(dnfb 27)(dnfb 28)(dnfb 29)(dnfb 30)(dnfb 31) ; Branch/Jump target addresses (df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT ((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (add SI (mul SI value 2) pc))) (df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT ((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (add SI (mul SI value 2) pc))) (df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT ((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (add SI (mul SI value 2) pc))) (df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f)(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f)(define-multi-ifield (name f-24s5a2n) (comment "pc-rel addr (24 bits align 2)") (attrs all-mep-core-isas PCREL-ADDR) (mode INT) (subfields f-24s5a2n-hi f-24s5a2n-lo) (insert (sequence () (set (ifield f-24s5a2n) (sub (ifield f-24s5a2n) pc)) (set (ifield f-24s5a2n-lo) (srl (and (ifield f-24s5a2n) #xfe) 1)) (set (ifield f-24s5a2n-hi) (sra INT (ifield f-24s5a2n) 8)))) (extract (set (ifield f-24s5a2n) (add SI (or (mul (ifield f-24s5a2n-hi) 256) (sll (ifield f-24s5a2n-lo) 1)) pc))) ) (df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f)(define-multi-ifield (name f-24u5a2n) (comment "abs jump target (24 bits, alignment 2)") (attrs all-mep-core-isas ABS-ADDR) (mode UINT) (subfields f-24u5a2n-hi f-24u5a2n-lo) (insert (sequence () (set (ifield f-24u5a2n-lo) (srl (and (ifield f-24u5a2n) #xff) 1)) (set (ifield f-24u5a2n-hi) (srl (ifield f-24u5a2n) 8)) )) (extract (set (ifield f-24u5a2n) (or (sll (ifield f-24u5a2n-hi) 8) (sll (ifield f-24u5a2n-lo) 1)))) ) ; Displacement fields. (df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f)(df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f)(df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT ((value pc) (srl SI value 1)) ((value pc) (mul SI value 2)))(df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2)))(df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f) ; Immediate fields. (df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f)(df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f)(df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f)(df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f)Lines 1–500 of 3082. Load more
; Toshiba MeP Media Engine architecture description. -*- Scheme -*- ; Copyright 2011 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; ; ; This file is part of the GNU Binutils. ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ; MA 02110-1301, USA. (include "simplify.inc") (define-pmacro isa-enum () (isas mep ; begin-isa-enum ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64 ; end-isa-enum ) ) (define-arch (name mep) (comment "Toshiba MeP Media Engine") (insn-lsb0? #f) ;; work around cgen limitation (machs mep h1 c5) isa-enum ) (define-isa (name mep) (comment "MeP core instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) ) ; begin-isas (define-isa (name ext_core1) (comment "MeP core extension instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) ) (define-isa (name ext_cop1_16) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) ) (define-isa (name ext_cop1_32) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) ) (define-isa (name ext_cop1_48) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) ) (define-isa (name ext_cop1_64) (comment "MeP coprocessor instruction set") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) ) (define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) (define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32)) (define-pmacro all-core-isa-list () mep,ext_core1) ; end-isas (define-cpu (name mepf) (comment "MeP family") (endian either) (insn-chunk-bitsize 16) (word-bitsize 32) ) (define-mach (name mep) (comment "MeP media engine") (cpu mepf) isa-enum ) (define-mach (name h1) (comment "H1 media engine") (cpu mepf) isa-enum ) (define-mach (name c5) (comment "C5 media engine") (cpu mepf) isa-enum ) (define-model (name mep) (comment "MeP media engine processor") (mach c5) ; mach gets changed by MeP-Integrator (unit u-exec "execution unit" () 1 1 ; issue done () () () ()) ; Branch unit (unit u-branch "Branch Unit" () 0 0 ; issue done () ; state () ; inputs ((pc)) ; outputs () ; profile action (default) ) ; Multiply unit (unit u-multiply "Multiply Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Divide unit (unit u-divide "Divide Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Stcb unit (unit u-stcb "stcb Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Ldcb unit (unit u-ldcb "ldcb Unit" () 0 0 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ; Load gpr unit (unit u-load-gpr "Load into GPR Unit" () 0 0 ; issue done () ; state () ; inputs ((loadreg INT -1)) ; outputs () ; profile action (default) ) (unit u-ldcb-gpr "Ldcb into GPR Unit" () 0 0 ; issue done () ; state () ; inputs ((loadreg INT -1)) ; outputs () ; profile action (default) ) ; Multiply into GPR unit (unit u-mul-gpr "Multiply into GPR Unit" () 0 0 ; issue done () ; state () ; inputs ((resultreg INT -1)) ; outputs () ; profile action (default) ) ; Use gpr unit -- stalls if GPR not ready (unit u-use-gpr "Use GPR Unit" () 0 0 ; issue done () ; state ((usereg INT -1)) ; inputs () ; outputs () ; profile action (default) ) ; Use ctrl-reg unit -- stalls if CTRL-REG not ready (unit u-use-ctrl-reg "Use CTRL-REG Unit" () 0 0 ; issue done () ; state ((usereg INT -1)) ; inputs () ; outputs () ; profile action (default) ) ; Store ctrl-reg unit -- stalls if CTRL-REG not ready (unit u-store-ctrl-reg "Store CTRL-REG Unit" () 0 0 ; issue done () ; state () ; inputs ((storereg INT -1)) ; outputs () ; profile action (default) ) ) ; Hardware elements. (dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ()) (define-hardware (name h-gpr) (comment "General purpose registers") (attrs all-mep-isas CACHE-ADDR PROFILE) (type register SI (16)) (indices keyword "$" (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) ; "$8" is the preferred name for register 8, but "$tp", "$gp" ; and "$sp" are preferred for their respective registers. (fp 8) (tp 13) (gp 14) (sp 15) ("12" 12) ("13" 13) ("14" 14) ("15" 15))) ) (define-hardware (name h-csr) (comment "Control/special registers") (attrs all-mep-isas PROFILE) (type register SI (32)) (indices keyword "$" ((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6) (hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15) (psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21) (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28) ; begin-extra-csr-registers (vid 22) ; end-extra-csr-registers )) (get (index) (c-call SI "cgen_get_csr_value" index)) (set (index newval) (c-call VOID "cgen_set_csr_value" index newval)) ) (define-pmacro (-reg-pair n) ((.sym n) n)) (define-hardware (name h-cr64) (comment "64-bit coprocessor registers") (attrs all-mep-isas) ; This assumes that the data path of the co-pro is 64 bits. (type register DI (32)) (indices keyword "$c" (.map -reg-pair (.iota 32))) (set (index newval) (c-call VOID "h_cr64_queue_set" index newval)) ) (define-hardware (name h-cr64-w) (comment "64-bit coprocessor registers, pending writes") (attrs all-mep-isas) ; This assumes that the data path of the co-pro is 64 bits. (type register DI (32)) ) (define-hardware (name h-cr) (comment "32-bit coprocessor registers") (attrs all-mep-isas VIRTUAL) (type register SI (32)) (indices keyword "$c" (.map -reg-pair (.iota 32))) (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) (get (index) (trunc SI (c-call DI "h_cr64_get" index))) ) ;; Given a coprocessor control register number N, expand to a ;; name/index pair: ($ccrN N) (define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n)) (define-hardware (name h-ccr) (comment "Coprocessor control registers") (attrs all-mep-isas) (type register SI (64)) (indices keyword "" (.map -ccr-reg-pair (.iota 64))) (set (index newval) (c-call VOID "h_ccr_queue_set" index newval)) ) (define-hardware (name h-ccr-w) (comment "Coprocessor control registers, pending writes") (attrs all-mep-isas) (type register SI (64)) ) ; Instruction fields. Bit numbering reversed. ; Conventions: ; ; N = number of bits in value ; A = alignment (2 or 4, omit for 1) ; B = leftmost (i.e. closest to zero) bit position ; ; -- Generic Fields (f-*) -- ; N number of bits in *value* (1-24) ; [us] signed vs unsigned ; B position of left-most bit (4-16) ; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc) ; n opt. for noncontiguous fields ; f-foo-{hi,lo} msb/lsb parts of field f-foo ; ; -- Operands -- ; pcrelNaA PC-relative branch target (signed) ; pcabsNaA Absolute branch target (unsigned) ; ; [us]dispNaA [un]signed displacement ; [us]immN [un]signed immediate value ; addrNaA absolute address (unsigned) ; ; Additional prefixes may be used for special cases. (dnf f-major "major opcode" (all-mep-core-isas) 0 4) (dnf f-rn "register n" (all-mep-core-isas) 4 4) (dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3) (dnf f-rm "register m" (all-mep-core-isas) 8 4) (dnf f-rl "register l" (all-mep-core-isas) 12 4) (dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2) (dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3) (dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4) (dnf f-ext "extended field" (all-mep-core-isas) 16 8) (dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4) (dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2) (dnf f-crn "copro register n" (all-mep-core-isas) 4 4) (df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f) (df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f) (define-multi-ifield (name f-csrn) (comment "control reg") (attrs all-mep-core-isas) (mode UINT) (subfields f-csrn-hi f-csrn-lo) (insert (sequence () (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf)) (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4)))) (extract (set (ifield f-csrn) (or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo)))) ) (df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f) (df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f) (define-multi-ifield (name f-crnx) (comment "copro register n (0-31)") (attrs all-mep-core-isas) (mode UINT) (subfields f-crnx-hi f-crnx-lo) (insert (sequence () (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf)) (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4)))) (extract (set (ifield f-crnx) (or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo)))) ) ; Miscellaneous fields. (define-pmacro (dnfb n) (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1)) ; Define small fields used throughout the instruction set description. ; Each field (eg. `f-N') is at single bit field at position N. (dnfb 0) (dnfb 1) (dnfb 2) (dnfb 3) (dnfb 4) (dnfb 5) (dnfb 6) (dnfb 7) (dnfb 8) (dnfb 9) (dnfb 10) (dnfb 11) (dnfb 12) (dnfb 13) (dnfb 14) (dnfb 15) (dnfb 16) (dnfb 17) (dnfb 18) (dnfb 19) (dnfb 20) (dnfb 21) (dnfb 22) (dnfb 23) (dnfb 24) (dnfb 25) (dnfb 26) (dnfb 27) (dnfb 28) (dnfb 29) (dnfb 30) (dnfb 31) ; Branch/Jump target addresses (df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT ((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (add SI (mul SI value 2) pc))) (df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT ((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (add SI (mul SI value 2) pc))) (df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT ((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (add SI (mul SI value 2) pc))) (df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f) (df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f) (define-multi-ifield (name f-24s5a2n) (comment "pc-rel addr (24 bits align 2)") (attrs all-mep-core-isas PCREL-ADDR) (mode INT) (subfields f-24s5a2n-hi f-24s5a2n-lo) (insert (sequence () (set (ifield f-24s5a2n) (sub (ifield f-24s5a2n) pc)) (set (ifield f-24s5a2n-lo) (srl (and (ifield f-24s5a2n) #xfe) 1)) (set (ifield f-24s5a2n-hi) (sra INT (ifield f-24s5a2n) 8)))) (extract (set (ifield f-24s5a2n) (add SI (or (mul (ifield f-24s5a2n-hi) 256) (sll (ifield f-24s5a2n-lo) 1)) pc))) ) (df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) (df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f) (define-multi-ifield (name f-24u5a2n) (comment "abs jump target (24 bits, alignment 2)") (attrs all-mep-core-isas ABS-ADDR) (mode UINT) (subfields f-24u5a2n-hi f-24u5a2n-lo) (insert (sequence () (set (ifield f-24u5a2n-lo) (srl (and (ifield f-24u5a2n) #xff) 1)) (set (ifield f-24u5a2n-hi) (srl (ifield f-24u5a2n) 8)) )) (extract (set (ifield f-24u5a2n) (or (sll (ifield f-24u5a2n-hi) 8) (sll (ifield f-24u5a2n-lo) 1)))) ) ; Displacement fields. (df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f) (df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f) (df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT ((value pc) (srl SI value 1)) ((value pc) (mul SI value 2))) (df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2))) (df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f) ; Immediate fields. (df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f) (df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f) (df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f) (df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f)