; Fujitsu FR30 CPU description. -*- Scheme -*-; Copyright 2011 Free Software Foundation, Inc.;; Contributed by Red Hat Inc;;; This file is part of the GNU Binutils.;; This program is free software; you can redistribute it and/or modify; it under the terms of the GNU General Public License as published by; the Free Software Foundation; either version 3 of the License, or; (at your option) any later version.;; This program is distributed in the hope that it will be useful,; but WITHOUT ANY WARRANTY; without even the implied warranty of; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License; along with this program; if not, write to the Free Software; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,; MA 02110-1301, USA. (define-rtl-version 0 8) (include "simplify.inc") ; define-arch must appear first (define-arch (name fr30) ; name of cpu family (comment "Fujitsu FR30") (default-alignment forced) (insn-lsb0? #f) (machs fr30) (isas fr30)) (define-isa (name fr30) (base-insn-bitsize 16) (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. (liw-insns 1) ; The fr30 fetches 1 insn at a time. (parallel-insns 1) ; The fr30 executes 1 insn at a time.) (define-cpu ; cpu names must be distinct from the architecture name and machine names. ; The "b" suffix stands for "base" and is the convention. ; The "f" suffix stands for "family" and is the convention. (name fr30bf) (comment "Fujitsu FR30 base family") (endian big) (word-bitsize 32)) (define-mach (name fr30) (comment "Generic FR30 cpu") (cpu fr30bf)) ; Model descriptions.;(define-model (name fr30-1) (comment "fr30-1") (attrs) (mach fr30) (pipeline all "" () ((fetch) (decode) (execute) (writeback))) ; `state' is a list of variables for recording model state (state ; bit mask of h-gr registers loaded from memory by previous insn (load-regs UINT) ; bit mask of h-gr registers loaded from memory by current insn (load-regs-pending UINT) ) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state ((Ri INT -1) (Rj INT -1)) ; inputs ((Ri INT -1)) ; outputs () ; profile action (default) ) (unit u-cti "Branch Unit" () 1 1 ; issue done () ; state ((Ri INT -1)) ; inputs ((pc)) ; outputs () ; profile action (default) ) (unit u-load "Memory Load Unit" () 1 1 ; issue done () ; state ((Rj INT -1) ;(ld-mem AI) ) ; inputs ((Ri INT -1)) ; outputs () ; profile action (default) ) (unit u-store "Memory Store Unit" () 1 1 ; issue done () ; state ((Ri INT -1) (Rj INT -1)) ; inputs () ; ((st-mem AI)) ; outputs () ; profile action (default) ) (unit u-ldm "LDM Memory Load Unit" () 1 1 ; issue done () ; state ((reglist INT)) ; inputs () ; outputs () ; profile action (default) ) (unit u-stm "STM Memory Store Unit" () 1 1 ; issue done () ; state ((reglist INT)) ; inputs () ; outputs () ; profile action (default) )) ; The instruction fetch/execute cycle.;; This is how to fetch and decode an instruction.; Leave it out for now ; (define-extract (const SI 0)) ; This is how to execute a decoded instruction.; Leave it out for now ; (define-execute (const SI 0)) ; Instruction fields.;; Attributes:; PCREL-ADDR: pc relative value (for reloc and disassembly purposes); ABS-ADDR: absolute address (for reloc and disassembly purposes?); RESERVED: bits are not used to decode insn, must be all 0 (dnf f-op1 "1st 4 bits of opcode" () 0 4)(dnf f-op2 "2nd 4 bits of opcode" () 4 4)(dnf f-op3 "3rd 4 bits of opcode" () 8 4)(dnf f-op4 "4th 4 bits of opcode" () 12 4)(dnf f-op5 "5th bit of opcode" () 4 1)(dnf f-cc "condition code" () 4 4)(dnf f-ccc "coprocessor calc code" () 16 8)(dnf f-Rj "register Rj" () 8 4)(dnf f-Ri "register Ri" () 12 4)(dnf f-Rs1 "register Rs" () 8 4)(dnf f-Rs2 "register Rs" () 12 4)(dnf f-Rjc "register Rj" () 24 4)(dnf f-Ric "register Ri" () 28 4)(dnf f-CRj "coprocessor register" () 24 4)(dnf f-CRi "coprocessor register" () 28 4)(dnf f-u4 "4 bit 0 extended" () 8 4)(dnf f-u4c "4 bit 0 extended" () 12 4)(df f-i4 "4 bit sign extended" () 8 4 INT #f #f)(df f-m4 "4 bit minus extended" () 8 4 UINT ; ??? This field takes a value in the range [-16,-1] but there ; doesn't seem a way to tell CGEN that. Use an unsigned field and ; disable range checks on insertion by masking. Restore the sign ; on extraction. CGEN generated documentation for insns that use ; this field will be wrong. ((value pc) (and WI value (const #xf))) ((value pc) (or WI value (const -16))))(dnf f-u8 "8 bit unsigned" () 8 8)(dnf f-i8 "8 bit unsigned" () 4 8) (dnf f-i20-4 "upper 4 bits of i20" () 8 4)(dnf f-i20-16 "lower 16 bits of i20" () 16 16)(dnmf f-i20 "20 bit unsigned" () UINT (f-i20-4 f-i20-16) (sequence () ; insert (set (ifield f-i20-4) (srl (ifield f-i20) (const 16))) (set (ifield f-i20-16) (and (ifield f-i20) (const #xffff))) ) (sequence () ; extract (set (ifield f-i20) (or (sll (ifield f-i20-4) (const 16)) (ifield f-i20-16))) )) (dnf f-i32 "32 bit immediate" (SIGN-OPT) 16 32) (df f-udisp6 "6 bit unsigned offset" () 8 4 UINT ((value pc) (srl UWI value (const 2))) ((value pc) (sll UWI value (const 2))))(df f-disp8 "8 bit signed offset" () 4 8 INT #f #f)(df f-disp9 "9 bit signed offset" () 4 8 INT ((value pc) (sra WI value (const 1))) ((value pc) (mul WI value (const 2))))(df f-disp10 "10 bit signed offset" () 4 8 INT ((value pc) (sra WI value (const 2))) ((value pc) (mul WI value (const 4))))(df f-s10 "10 bit signed offset" () 8 8 INT ((value pc) (sra WI value (const 2))) ((value pc) (mul WI value (const 4))))(df f-u10 "10 bit unsigned offset" () 8 8 UINT ((value pc) (srl UWI value (const 2))) ((value pc) (sll UWI value (const 2))))(df f-rel9 "9 pc relative signed offset" (PCREL-ADDR) 8 8 INT ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) ((value pc) (add WI (mul WI value (const 2)) (add WI pc (const 2)))))(dnf f-dir8 "8 bit direct address" () 8 8)(df f-dir9 "9 bit direct address" () 8 8 UINT ((value pc) (srl UWI value (const 1))) ((value pc) (sll UWI value (const 1))))(df f-dir10 "10 bit direct address" () 8 8 UINT ((value pc) (srl UWI value (const 2))) ((value pc) (sll UWI value (const 2))))(df f-rel12 "12 bit pc relative signed offset" (PCREL-ADDR) 5 11 INT ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) ((value pc) (add WI (mul WI value (const 2)) (add WI pc (const 2))))) (dnf f-reglist_hi_st "8 bit register mask for stm" () 8 8)(dnf f-reglist_low_st "8 bit register mask for stm" () 8 8)(dnf f-reglist_hi_ld "8 bit register mask for ldm" () 8 8)(dnf f-reglist_low_ld "8 bit register mask for ldm" () 8 8) ; Enums. ; insn-op1: bits 0-3; FIXME: should use die macro or some such(define-normal-insn-enum insn-op1 "insn op1 enums" () OP1_ f-op1 ("0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F")) ; insn-op2: bits 4-7; FIXME: should use die macro or some such(define-normal-insn-enum insn-op2 "insn op2 enums" () OP2_ f-op2 ("0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F")) ; insn-op3: bits 8-11; FIXME: should use die macro or some such(define-normal-insn-enum insn-op3 "insn op3 enums" () OP3_ f-op3 ("0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F")) ; insn-op4: bits 12-15; FIXME: should use die macro or some such(define-normal-insn-enum insn-op4 "insn op4 enums" () OP4_ f-op4 ("0")) ; insn-op5: bit 4 (5th bit origin 0); FIXME: should use die macro or some such(define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5 ("0" "1")) ; insn-cc: condition codes; FIXME: should use die macro or some such(define-normal-insn-enum insn-cc "insn cc enums" () CC_ f-cc ("ra" "no" "eq" "ne" "c" "nc" "n" "p" "v" "nv" "lt" "ge" "le" "gt" "ls" "hi")) ; Hardware pieces.; These entries list the elements of the raw hardware.; They're also used to provide tables and other elements of the assembly; language. (dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) (define-keyword (name gr-names) (enum-prefix H-GR-) (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15) (ac 13) (fp 14) (sp 15))) (define-hardware (name h-gr) (comment "general registers") (attrs PROFILE CACHE-ADDR) (type register WI (16)) (indices extern-keyword gr-names)) (define-keyword (name cr-names) (enum-prefix H-CR-) (values (cr0 0) (cr1 1) (cr2 2) (cr3 3) (cr4 4) (cr5 5) (cr6 6) (cr7 7) (cr8 8) (cr9 9) (cr10 10) (cr11 11) (cr12 12) (cr13 13) (cr14 14) (cr15 15))) (define-hardware (name h-cr) (comment "coprocessor registers") (attrs) (type register WI (16)) (indices extern-keyword cr-names)) (define-keyword (name dr-names) (enum-prefix H-DR-) (values (tbr 0) (rp 1) (ssp 2) (usp 3) (mdh 4) (mdl 5))) (define-hardware (name h-dr) (comment "dedicated registers") (type register WI (6)) (indices extern-keyword dr-names) (get (index) (c-call WI "@cpu@_h_dr_get_handler" index)) (set (index newval) (c-call VOID "@cpu@_h_dr_set_handler" index newval))) (define-hardware (name h-ps) (comment "processor status") (type register UWI) (indices keyword "" ((ps 0))) (get () (c-call UWI "@cpu@_h_ps_get_handler")) (set (newval) (c-call VOID "@cpu@_h_ps_set_handler" newval))) (dnh h-r13 "General Register 13 explicitly required" () (register WI) (keyword "" ((r13 0))) () ()) (dnh h-r14 "General Register 14 explicitly required" () (register WI) (keyword "" ((r14 0))) () ()) (dnh h-r15 "General Register 15 explicitly required" () (register WI) (keyword "" ((r15 0))) () ()) ; These bits are actually part of the PS register but are accessed more; often than the entire register, so define them directly. We can assemble; the PS register from its components when necessary. (dsh h-nbit "negative bit" () (register BI))(dsh h-zbit "zero bit" () (register BI))(dsh h-vbit "overflow bit" () (register BI))(dsh h-cbit "carry bit" () (register BI))(dsh h-ibit "interrupt enable bit" () (register BI))(define-hardware (name h-sbit) (comment "stack bit") (type register BI) (get () (c-call BI "@cpu@_h_sbit_get_handler")) (set (newval) (c-call VOID "@cpu@_h_sbit_set_handler" newval)))(dsh h-tbit "trace trap bit" () (register BI))(dsh h-d0bit "division 0 bit" () (register BI))(dsh h-d1bit "division 1 bit" () (register BI)) ; These represent sub-registers within the program status register (define-hardware (name h-ccr) (comment "condition code bits") (type register UQI) (get () (c-call UQI "@cpu@_h_ccr_get_handler")) (set (newval) (c-call VOID "@cpu@_h_ccr_set_handler" newval)))(define-hardware (name h-scr) (comment "system condition bits") (type register UQI) (get () (c-call UQI "@cpu@_h_scr_get_handler")) (set (newval) (c-call VOID "@cpu@_h_scr_set_handler" newval)))(define-hardware (name h-ilm) (comment "interrupt level mask") (type register UQI) (get () (c-call UQI "@cpu@_h_ilm_get_handler")) (set (newval) (c-call VOID "@cpu@_h_ilm_set_handler" newval))) ; Instruction Operands.; These entries provide a layer between the assembler and the raw hardware; description, and are used to refer to hardware elements in the semantic; code. Usually there's a bit of over-specification, but in more complicated; instruction sets there isn't. ; FR30 specific operand attributes: (define-attr (for operand) (type boolean) (name HASH-PREFIX) (comment "immediates have an optional '#' prefix")) ; ??? Convention says this should be o-sr, but then the insn definitions; should refer to o-sr which is clumsy. The "o-" could be implicit, but; then it should be implicit for all the symbols here, but then there would; be confusion between (f-)simm8 and (h-)simm8.; So for now the rule is exactly as it appears here. (dnop Ri "destination register" () h-gr f-Ri)(dnop Rj "source register" () h-gr f-Rj)(dnop Ric "target register coproc insn" () h-gr f-Ric)(dnop Rjc "source register coproc insn" () h-gr f-Rjc)(dnop CRi "coprocessor register" () h-cr f-CRi)(dnop CRj "coprocessor register" () h-cr f-CRj)(dnop Rs1 "dedicated register" () h-dr f-Rs1)(dnop Rs2 "dedicated register" () h-dr f-Rs2)(dnop R13 "General Register 13" () h-r13 f-nil)(dnop R14 "General Register 14" () h-r14 f-nil)(dnop R15 "General Register 15" () h-r15 f-nil)(dnop ps "Program Status register" () h-ps f-nil)(dnop u4 "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4)(dnop u4c "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4c)(dnop u8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-u8)(dnop i8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-i8)(dnop udisp6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-udisp6)(dnop disp8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-disp8)(dnop disp9 "9 bit signed immediate" (HASH-PREFIX) h-sint f-disp9)(dnop disp10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-disp10) (dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10)(dnop u10 "10 bit unsigned immediate" (HASH-PREFIX) h-uint f-u10)(dnop i32 "32 bit immediate" (HASH-PREFIX) h-uint f-i32) (define-operand (name m4) (comment "4 bit negative immediate") (attrs HASH-PREFIX) (type h-sint) (index f-m4) (handlers (print "m4"))) (define-operand (name i20) (comment "20 bit immediate") (attrs HASH-PREFIX) (type h-uint) (index f-i20)) (dnop dir8 "8 bit direct address" () h-uint f-dir8)(dnop dir9 "9 bit direct address" () h-uint f-dir9)(dnop dir10 "10 bit direct address" () h-uint f-dir10) (dnop label9 "9 bit pc relative address" () h-iaddr f-rel9)(dnop label12 "12 bit pc relative address" () h-iaddr f-rel12) (define-operand (name reglist_low_ld) (comment "8 bit low register mask for ldm") (attrs) (type h-uint) (index f-reglist_low_ld) (handlers (parse "low_register_list_ld") (print "low_register_list_ld"))) (define-operand (name reglist_hi_ld) (comment "8 bit high register mask for ldm") (attrs) (type h-uint) (index f-reglist_hi_ld) (handlers (parse "hi_register_list_ld") (print "hi_register_list_ld"))) (define-operand (name reglist_low_st) (comment "8 bit low register mask for stm") (attrs) (type h-uint) (index f-reglist_low_st) (handlers (parse "low_register_list_st") (print "low_register_list_st"))Lines 1–500 of 1863. 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; Fujitsu FR30 CPU description. -*- Scheme -*- ; Copyright 2011 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; ; ; This file is part of the GNU Binutils. ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ; MA 02110-1301, USA. (define-rtl-version 0 8) (include "simplify.inc") ; define-arch must appear first (define-arch (name fr30) ; name of cpu family (comment "Fujitsu FR30") (default-alignment forced) (insn-lsb0? #f) (machs fr30) (isas fr30) ) (define-isa (name fr30) (base-insn-bitsize 16) (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. (liw-insns 1) ; The fr30 fetches 1 insn at a time. (parallel-insns 1) ; The fr30 executes 1 insn at a time. ) (define-cpu ; cpu names must be distinct from the architecture name and machine names. ; The "b" suffix stands for "base" and is the convention. ; The "f" suffix stands for "family" and is the convention. (name fr30bf) (comment "Fujitsu FR30 base family") (endian big) (word-bitsize 32) ) (define-mach (name fr30) (comment "Generic FR30 cpu") (cpu fr30bf) ) ; Model descriptions. ; (define-model (name fr30-1) (comment "fr30-1") (attrs) (mach fr30) (pipeline all "" () ((fetch) (decode) (execute) (writeback))) ; `state' is a list of variables for recording model state (state ; bit mask of h-gr registers loaded from memory by previous insn (load-regs UINT) ; bit mask of h-gr registers loaded from memory by current insn (load-regs-pending UINT) ) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state ((Ri INT -1) (Rj INT -1)) ; inputs ((Ri INT -1)) ; outputs () ; profile action (default) ) (unit u-cti "Branch Unit" () 1 1 ; issue done () ; state ((Ri INT -1)) ; inputs ((pc)) ; outputs () ; profile action (default) ) (unit u-load "Memory Load Unit" () 1 1 ; issue done () ; state ((Rj INT -1) ;(ld-mem AI) ) ; inputs ((Ri INT -1)) ; outputs () ; profile action (default) ) (unit u-store "Memory Store Unit" () 1 1 ; issue done () ; state ((Ri INT -1) (Rj INT -1)) ; inputs () ; ((st-mem AI)) ; outputs () ; profile action (default) ) (unit u-ldm "LDM Memory Load Unit" () 1 1 ; issue done () ; state ((reglist INT)) ; inputs () ; outputs () ; profile action (default) ) (unit u-stm "STM Memory Store Unit" () 1 1 ; issue done () ; state ((reglist INT)) ; inputs () ; outputs () ; profile action (default) ) ) ; The instruction fetch/execute cycle. ; ; This is how to fetch and decode an instruction. ; Leave it out for now ; (define-extract (const SI 0)) ; This is how to execute a decoded instruction. ; Leave it out for now ; (define-execute (const SI 0)) ; Instruction fields. ; ; Attributes: ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) ; ABS-ADDR: absolute address (for reloc and disassembly purposes?) ; RESERVED: bits are not used to decode insn, must be all 0 (dnf f-op1 "1st 4 bits of opcode" () 0 4) (dnf f-op2 "2nd 4 bits of opcode" () 4 4) (dnf f-op3 "3rd 4 bits of opcode" () 8 4) (dnf f-op4 "4th 4 bits of opcode" () 12 4) (dnf f-op5 "5th bit of opcode" () 4 1) (dnf f-cc "condition code" () 4 4) (dnf f-ccc "coprocessor calc code" () 16 8) (dnf f-Rj "register Rj" () 8 4) (dnf f-Ri "register Ri" () 12 4) (dnf f-Rs1 "register Rs" () 8 4) (dnf f-Rs2 "register Rs" () 12 4) (dnf f-Rjc "register Rj" () 24 4) (dnf f-Ric "register Ri" () 28 4) (dnf f-CRj "coprocessor register" () 24 4) (dnf f-CRi "coprocessor register" () 28 4) (dnf f-u4 "4 bit 0 extended" () 8 4) (dnf f-u4c "4 bit 0 extended" () 12 4) (df f-i4 "4 bit sign extended" () 8 4 INT #f #f) (df f-m4 "4 bit minus extended" () 8 4 UINT ; ??? This field takes a value in the range [-16,-1] but there ; doesn't seem a way to tell CGEN that. Use an unsigned field and ; disable range checks on insertion by masking. Restore the sign ; on extraction. CGEN generated documentation for insns that use ; this field will be wrong. ((value pc) (and WI value (const #xf))) ((value pc) (or WI value (const -16))) ) (dnf f-u8 "8 bit unsigned" () 8 8) (dnf f-i8 "8 bit unsigned" () 4 8) (dnf f-i20-4 "upper 4 bits of i20" () 8 4) (dnf f-i20-16 "lower 16 bits of i20" () 16 16) (dnmf f-i20 "20 bit unsigned" () UINT (f-i20-4 f-i20-16) (sequence () ; insert (set (ifield f-i20-4) (srl (ifield f-i20) (const 16))) (set (ifield f-i20-16) (and (ifield f-i20) (const #xffff))) ) (sequence () ; extract (set (ifield f-i20) (or (sll (ifield f-i20-4) (const 16)) (ifield f-i20-16))) ) ) (dnf f-i32 "32 bit immediate" (SIGN-OPT) 16 32) (df f-udisp6 "6 bit unsigned offset" () 8 4 UINT ((value pc) (srl UWI value (const 2))) ((value pc) (sll UWI value (const 2))) ) (df f-disp8 "8 bit signed offset" () 4 8 INT #f #f) (df f-disp9 "9 bit signed offset" () 4 8 INT ((value pc) (sra WI value (const 1))) ((value pc) (mul WI value (const 2))) ) (df f-disp10 "10 bit signed offset" () 4 8 INT ((value pc) (sra WI value (const 2))) ((value pc) (mul WI value (const 4))) ) (df f-s10 "10 bit signed offset" () 8 8 INT ((value pc) (sra WI value (const 2))) ((value pc) (mul WI value (const 4))) ) (df f-u10 "10 bit unsigned offset" () 8 8 UINT ((value pc) (srl UWI value (const 2))) ((value pc) (sll UWI value (const 2))) ) (df f-rel9 "9 pc relative signed offset" (PCREL-ADDR) 8 8 INT ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) ((value pc) (add WI (mul WI value (const 2)) (add WI pc (const 2)))) ) (dnf f-dir8 "8 bit direct address" () 8 8) (df f-dir9 "9 bit direct address" () 8 8 UINT ((value pc) (srl UWI value (const 1))) ((value pc) (sll UWI value (const 1))) ) (df f-dir10 "10 bit direct address" () 8 8 UINT ((value pc) (srl UWI value (const 2))) ((value pc) (sll UWI value (const 2))) ) (df f-rel12 "12 bit pc relative signed offset" (PCREL-ADDR) 5 11 INT ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) ((value pc) (add WI (mul WI value (const 2)) (add WI pc (const 2)))) ) (dnf f-reglist_hi_st "8 bit register mask for stm" () 8 8) (dnf f-reglist_low_st "8 bit register mask for stm" () 8 8) (dnf f-reglist_hi_ld "8 bit register mask for ldm" () 8 8) (dnf f-reglist_low_ld "8 bit register mask for ldm" () 8 8) ; Enums. ; insn-op1: bits 0-3 ; FIXME: should use die macro or some such (define-normal-insn-enum insn-op1 "insn op1 enums" () OP1_ f-op1 ("0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F") ) ; insn-op2: bits 4-7 ; FIXME: should use die macro or some such (define-normal-insn-enum insn-op2 "insn op2 enums" () OP2_ f-op2 ("0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F") ) ; insn-op3: bits 8-11 ; FIXME: should use die macro or some such (define-normal-insn-enum insn-op3 "insn op3 enums" () OP3_ f-op3 ("0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F") ) ; insn-op4: bits 12-15 ; FIXME: should use die macro or some such (define-normal-insn-enum insn-op4 "insn op4 enums" () OP4_ f-op4 ("0") ) ; insn-op5: bit 4 (5th bit origin 0) ; FIXME: should use die macro or some such (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5 ("0" "1") ) ; insn-cc: condition codes ; FIXME: should use die macro or some such (define-normal-insn-enum insn-cc "insn cc enums" () CC_ f-cc ("ra" "no" "eq" "ne" "c" "nc" "n" "p" "v" "nv" "lt" "ge" "le" "gt" "ls" "hi") ) ; Hardware pieces. ; These entries list the elements of the raw hardware. ; They're also used to provide tables and other elements of the assembly ; language. (dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) (define-keyword (name gr-names) (enum-prefix H-GR-) (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15) (ac 13) (fp 14) (sp 15)) ) (define-hardware (name h-gr) (comment "general registers") (attrs PROFILE CACHE-ADDR) (type register WI (16)) (indices extern-keyword gr-names) ) (define-keyword (name cr-names) (enum-prefix H-CR-) (values (cr0 0) (cr1 1) (cr2 2) (cr3 3) (cr4 4) (cr5 5) (cr6 6) (cr7 7) (cr8 8) (cr9 9) (cr10 10) (cr11 11) (cr12 12) (cr13 13) (cr14 14) (cr15 15)) ) (define-hardware (name h-cr) (comment "coprocessor registers") (attrs) (type register WI (16)) (indices extern-keyword cr-names) ) (define-keyword (name dr-names) (enum-prefix H-DR-) (values (tbr 0) (rp 1) (ssp 2) (usp 3) (mdh 4) (mdl 5)) ) (define-hardware (name h-dr) (comment "dedicated registers") (type register WI (6)) (indices extern-keyword dr-names) (get (index) (c-call WI "@cpu@_h_dr_get_handler" index)) (set (index newval) (c-call VOID "@cpu@_h_dr_set_handler" index newval)) ) (define-hardware (name h-ps) (comment "processor status") (type register UWI) (indices keyword "" ((ps 0))) (get () (c-call UWI "@cpu@_h_ps_get_handler")) (set (newval) (c-call VOID "@cpu@_h_ps_set_handler" newval)) ) (dnh h-r13 "General Register 13 explicitly required" () (register WI) (keyword "" ((r13 0))) () () ) (dnh h-r14 "General Register 14 explicitly required" () (register WI) (keyword "" ((r14 0))) () () ) (dnh h-r15 "General Register 15 explicitly required" () (register WI) (keyword "" ((r15 0))) () () ) ; These bits are actually part of the PS register but are accessed more ; often than the entire register, so define them directly. We can assemble ; the PS register from its components when necessary. (dsh h-nbit "negative bit" () (register BI)) (dsh h-zbit "zero bit" () (register BI)) (dsh h-vbit "overflow bit" () (register BI)) (dsh h-cbit "carry bit" () (register BI)) (dsh h-ibit "interrupt enable bit" () (register BI)) (define-hardware (name h-sbit) (comment "stack bit") (type register BI) (get () (c-call BI "@cpu@_h_sbit_get_handler")) (set (newval) (c-call VOID "@cpu@_h_sbit_set_handler" newval)) ) (dsh h-tbit "trace trap bit" () (register BI)) (dsh h-d0bit "division 0 bit" () (register BI)) (dsh h-d1bit "division 1 bit" () (register BI)) ; These represent sub-registers within the program status register (define-hardware (name h-ccr) (comment "condition code bits") (type register UQI) (get () (c-call UQI "@cpu@_h_ccr_get_handler")) (set (newval) (c-call VOID "@cpu@_h_ccr_set_handler" newval)) ) (define-hardware (name h-scr) (comment "system condition bits") (type register UQI) (get () (c-call UQI "@cpu@_h_scr_get_handler")) (set (newval) (c-call VOID "@cpu@_h_scr_set_handler" newval)) ) (define-hardware (name h-ilm) (comment "interrupt level mask") (type register UQI) (get () (c-call UQI "@cpu@_h_ilm_get_handler")) (set (newval) (c-call VOID "@cpu@_h_ilm_set_handler" newval)) ) ; Instruction Operands. ; These entries provide a layer between the assembler and the raw hardware ; description, and are used to refer to hardware elements in the semantic ; code. Usually there's a bit of over-specification, but in more complicated ; instruction sets there isn't. ; FR30 specific operand attributes: (define-attr (for operand) (type boolean) (name HASH-PREFIX) (comment "immediates have an optional '#' prefix") ) ; ??? Convention says this should be o-sr, but then the insn definitions ; should refer to o-sr which is clumsy. The "o-" could be implicit, but ; then it should be implicit for all the symbols here, but then there would ; be confusion between (f-)simm8 and (h-)simm8. ; So for now the rule is exactly as it appears here. (dnop Ri "destination register" () h-gr f-Ri) (dnop Rj "source register" () h-gr f-Rj) (dnop Ric "target register coproc insn" () h-gr f-Ric) (dnop Rjc "source register coproc insn" () h-gr f-Rjc) (dnop CRi "coprocessor register" () h-cr f-CRi) (dnop CRj "coprocessor register" () h-cr f-CRj) (dnop Rs1 "dedicated register" () h-dr f-Rs1) (dnop Rs2 "dedicated register" () h-dr f-Rs2) (dnop R13 "General Register 13" () h-r13 f-nil) (dnop R14 "General Register 14" () h-r14 f-nil) (dnop R15 "General Register 15" () h-r15 f-nil) (dnop ps "Program Status register" () h-ps f-nil) (dnop u4 "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4) (dnop u4c "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4c) (dnop u8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-u8) (dnop i8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-i8) (dnop udisp6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-udisp6) (dnop disp8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-disp8) (dnop disp9 "9 bit signed immediate" (HASH-PREFIX) h-sint f-disp9) (dnop disp10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-disp10) (dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) (dnop u10 "10 bit unsigned immediate" (HASH-PREFIX) h-uint f-u10) (dnop i32 "32 bit immediate" (HASH-PREFIX) h-uint f-i32) (define-operand (name m4) (comment "4 bit negative immediate") (attrs HASH-PREFIX) (type h-sint) (index f-m4) (handlers (print "m4")) ) (define-operand (name i20) (comment "20 bit immediate") (attrs HASH-PREFIX) (type h-uint) (index f-i20) ) (dnop dir8 "8 bit direct address" () h-uint f-dir8) (dnop dir9 "9 bit direct address" () h-uint f-dir9) (dnop dir10 "10 bit direct address" () h-uint f-dir10) (dnop label9 "9 bit pc relative address" () h-iaddr f-rel9) (dnop label12 "12 bit pc relative address" () h-iaddr f-rel12) (define-operand (name reglist_low_ld) (comment "8 bit low register mask for ldm") (attrs) (type h-uint) (index f-reglist_low_ld) (handlers (parse "low_register_list_ld") (print "low_register_list_ld")) ) (define-operand (name reglist_hi_ld) (comment "8 bit high register mask for ldm") (attrs) (type h-uint) (index f-reglist_hi_ld) (handlers (parse "hi_register_list_ld") (print "hi_register_list_ld")) ) (define-operand (name reglist_low_st) (comment "8 bit low register mask for stm") (attrs) (type h-uint) (index f-reglist_low_st) (handlers (parse "low_register_list_st") (print "low_register_list_st"))