; Hitachi SHcompact instruction set description. -*- Scheme -*-;; Copyright 2000, 2007, 2009 Free Software Foundation, Inc.;; Contributed by Red Hat Inc; developed under contract from Hitachi; Semiconductor (America) Inc.;; This file is part of the GNU Binutils.;; This program is free software; you can redistribute it and/or modify; it under the terms of the GNU General Public License as published by; the Free Software Foundation; either version 3 of the License, or; (at your option) any later version.;; This program is distributed in the hope that it will be useful,; but WITHOUT ANY WARRANTY; without even the implied warranty of; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License; along with this program; if not, write to the Free Software; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,; MA 02110-1301, USA. ; dshcf -- define-normal-sh-compact-field (define-pmacro (dshcf xname xcomment ignored xstart xlength) (dnf xname xcomment ((ISA compact)) xstart xlength)) ; dshcop -- define-normal-sh-compact-operand (define-pmacro (dshcop xname xcomment ignored xhardware xfield) (dnop xname xcomment ((ISA compact)) xhardware xfield)) ; SHcompact-specific attributes. (define-attr (for insn) (type boolean) (name ILLSLOT) (comment "instruction may not appear in a delay slot")) (define-attr (for insn) (type boolean) (name FP-INSN) (comment "floating point instruction")) (define-keyword (name frc-names) (attrs (ISA compact)) (print-name h-frc) (values (fr0 0) (fr1 1) (fr2 2) (fr3 3) (fr4 4) (fr5 5) (fr6 6) (fr7 7) (fr8 8) (fr9 9) (fr10 10) (fr11 11) (fr12 12) (fr13 13) (fr14 14) (fr15 15))) (define-keyword (name drc-names) (attrs (ISA compact)) (print-name h-drc) (values (dr0 0) (dr2 2) (dr4 4) (dr6 6) (dr8 8) (dr10 10) (dr12 12) (dr14 14))) (define-keyword (name xf-names) (attrs (ISA compact)) (print-name h-xf) (values (xf0 0) (xf1 1) (xf2 2) (xf3 3) (xf4 4) (xf5 5) (xf6 6) (xf7 7) (xf8 8) (xf9 9) (xf10 10) (xf11 11) (xf12 12) (xf13 13) (xf14 14) (xf15 15))) ; Hardware specific to the SHcompact mode. (define-pmacro (front) (mul 16 frbit))(define-pmacro (back) (mul 16 (not frbit))) (define-hardware (name h-frc) (comment "Single precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword frc-names) (type register SF (16)) (get (index) (reg h-fr (add (front) index))) (set (index newval) (set (reg h-fr (add (front) index)) newval))) (define-hardware (name h-drc) (comment "Double precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword drc-names) (type register DF (8)) (get (index) (reg h-dr (add (front) index))) (set (index newval) (set (reg h-dr (add (front) index)) newval))) (define-hardware (name h-xf) (comment "Extended single precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword xf-names) (type register SF (16)) (get (index) (reg h-fr (add (back) index))) (set (index newval) (set (reg h-fr (add (back) index)) newval))) (define-hardware (name h-xd) (comment "Extended double precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword frc-names) (type register DF (8)) (get (index) (reg h-dr (add (back) index))) (set (index newval) (set (reg h-dr (add (back) index)) newval))) (define-hardware (name h-fvc) (comment "Single precision floating point vectors") (attrs VIRTUAL (ISA compact)) (indices keyword "" ((fv0 0) (fv4 4) (fv8 8) (fv12 12))) (type register SF (4)) (get (index) (reg h-fr (add (front) index))) (set (index newval) (set (reg h-fr (add (front) index)) newval))) (define-hardware (name h-fpccr) (comment "SHcompact floating point status/control register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21))) (set (newvalue) (sequence () (set (reg h-fpscr) newvalue) (set prbit (and (srl newvalue 19) 1)) (set szbit (and (srl newvalue 20) 1)) (set frbit (and (srl newvalue 21) 1))))) (define-hardware (name h-gbr) (comment "Global base register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 16) 1)) (set (newval) (set (raw-reg h-gr 16) (ext DI newval)))) (define-hardware (name h-pr) (comment "Procedure link register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 18) 1)) (set (newval) (set (raw-reg h-gr 18) (ext DI newval)))) (define-hardware (name h-macl) (comment "Multiple-accumulate low register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 17) 1)) (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval)))) (define-hardware (name h-mach) (comment "Multiply-accumulate high register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 17) 0)) (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1))))) (define-hardware (name h-tbit) (comment "Condition code flag") (attrs VIRTUAL (ISA compact)) (type register BI) (get () (and BI (raw-reg h-gr 19) 1)) (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval))))) (dshcf f-op4 "Opcode (4 bits)" () 15 4)(dshcf f-op8 "Opcode (8 bits)" () 15 8)(dshcf f-op16 "Opcode (16 bits)" () 15 16) (dshcf f-sub4 "Sub opcode (4 bits)" () 3 4)(dshcf f-sub8 "Sub opcode (8 bits)" () 7 8)(dshcf f-sub10 "Sub opcode (10 bits)" () 9 10) (dshcf f-rn "Register selector n" () 11 4)(dshcf f-rm "Register selector m" () 7 4) (dshcf f-8-1 "One bit at bit 8" () 8 1) (df f-disp8 "Displacement (8 bits)" ((ISA compact) PCREL-ADDR) 7 8 INT ((value pc) (sra SI value 1)) ((value pc) (add SI (sll SI value 1) (add pc 4)))) (df f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT ((value pc) (sra SI value 1)) ((value pc) (add SI (sll SI value 1) (add pc 4)))) (dshcf f-imm8 "Immediate (8 bits)" () 7 8)(dshcf f-imm4 "Immediate (4 bits)" () 3 4) (df f-imm4x2 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT ((value pc) (srl SI value 1)) ((value pc) (sll SI value 1))) (df f-imm4x4 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2))) (df f-imm8x2 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT ((value pc) (sra SI value 1)) ((value pc) (sll SI value 1))) (df f-imm8x4 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT ((value pc) (sra SI value 2)) ((value pc) (sll SI value 2))) (df f-dn "Double selector n" ((ISA compact)) 11 3 UINT ((value pc) (srl SI value 1)) ((value pc) (sll SI value 1))) (df f-dm "Double selector m" ((ISA compact)) 7 3 UINT ((value pc) (srl SI value 1)) ((value pc) (sll SI value 1))) (df f-vn "Vector selector n" ((ISA compact)) 11 2 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2))) (df f-vm "Vector selector m" ((ISA compact)) 9 2 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2))) (df f-xn "Extended selector n" ((ISA compact)) 11 3 UINT ((value pc) (srl SI value 1)) ((value pc) (add SI (sll SI value 1) 1))) (df f-xm "Extended selector m" ((ISA compact)) 7 3 UINT ((value pc) (srl SI value 1)) ((value pc) (add SI (sll SI value 1) 1))) ; Operands. (dshcop rm "Left general purpose register" () h-grc f-rm)(dshcop rn "Right general purpose register" () h-grc f-rn)(dshcop r0 "Register 0" () h-grc 0) (dshcop frn "Single precision register" () h-frc f-rn)(dshcop frm "Single precision register" () h-frc f-rm) (dshcop fvn "Left floating point vector" () h-fvc f-vn)(dshcop fvm "Right floating point vector" () h-fvc f-vm) (dshcop drn "Left double precision register" () h-drc f-dn)(dshcop drm "Right double precision register" () h-drc f-dm) (dshcop imm4 "Immediate value (4 bits)" () h-sint f-imm4)(dshcop imm8 "Immediate value (8 bits)" () h-sint f-imm8)(dshcop uimm8 "Immediate value (8 bits unsigned)" () h-uint f-imm8) (dshcop imm4x2 "Immediate value (4 bits, 2x scale)" () h-uint f-imm4x2)(dshcop imm4x4 "Immediate value (4 bits, 4x scale)" () h-uint f-imm4x4)(dshcop imm8x2 "Immediate value (8 bits, 2x scale)" () h-uint f-imm8x2)(dshcop imm8x4 "Immediate value (8 bits, 4x scale)" () h-uint f-imm8x4) (dshcop disp8 "Displacement (8 bits)" () h-iaddr f-disp8)(dshcop disp12 "Displacement (12 bits)" () h-iaddr f-disp12) (dshcop rm64 "Register m (64 bits)" () h-gr f-rm)(dshcop rn64 "Register n (64 bits)" () h-gr f-rn) (dshcop gbr "Global base register" () h-gbr f-nil)(dshcop pr "Procedure link register" () h-pr f-nil) (dshcop fpscr "Floating point status/control register" () h-fpccr f-nil) (dshcop tbit "Condition code flag" () h-tbit f-nil)(dshcop sbit "Multiply-accumulate saturation flag" () h-sbit f-nil)(dshcop mbit "Divide-step M flag" () h-mbit f-nil)(dshcop qbit "Divide-step Q flag" () h-qbit f-nil)(dshcop fpul "Floating point ???" () h-fr 32) (dshcop frbit "Floating point register bank bit" () h-frbit f-nil)(dshcop szbit "Floating point transfer size bit" () h-szbit f-nil)(dshcop prbit "Floating point precision bit" () h-prbit f-nil) (dshcop macl "Multiply-accumulate low register" () h-macl f-nil)(dshcop mach "Multiply-accumulate high register" () h-mach f-nil) (define-operand (name fsdm) (comment "bar") (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd"))) (define-operand (name fsdn) (comment "bar") (attrs (ISA compact)) (type h-frc) (index f-rn)) ; Cover macro to dni to indicate these are all SHcompact instructions.; dshmi: define-normal-sh-compact-insn (define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics) (define-insn (name (.sym xname -compact)) (comment xcomment) (.splice attrs (.unsplice xattrs) (ISA compact)) (syntax xsyntax) (format xformat) (semantics xsemantics))) (define-pmacro (dr operand) (reg h-dr (index-of operand)))(define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1)))) (dshci add "Add" () "add $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 12)) (set rn (add rn rm))) (dshci addi "Add immediate" () "add #$imm8, $rn" (+ (f-op4 7) rn imm8) (set rn (add rn (ext SI (and QI imm8 255))))) (dshci addc "Add with carry" () "addc $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 14)) (sequence ((BI flag)) (set flag (add-cflag rn rm tbit)) (set rn (addc rn rm tbit)) (set tbit flag))) (dshci addv "Add with overflow" () "addv $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 15)) (sequence ((BI t)) (set t (add-oflag rn rm 0)) (set rn (add rn rm)) (set tbit t))) (dshci and "Bitwise AND" () "and $rm64, $rn64" (+ (f-op4 2) rn64 rm64 (f-sub4 9)) (set rn64 (and rm64 rn64))) (dshci andi "Bitwise AND immediate" () "and #$uimm8, r0" (+ (f-op8 #xc9) uimm8) (set r0 (and r0 (zext DI uimm8)))) (dshci andb "Bitwise AND memory byte" () "and.b #$imm8, @(r0, gbr)" (+ (f-op8 #xcd) imm8) (sequence ((DI addr) (UQI data)) (set addr (add r0 gbr)) (set data (and (mem UQI addr) imm8)) (set (mem UQI addr) data))) (dshci bf "Conditional branch" () "bf $disp8" (+ (f-op8 #x8b) disp8) (if (not tbit) (set pc disp8))) (dshci bfs "Conditional branch with delay slot" () "bf/s $disp8" (+ (f-op8 #x8f) disp8) (if (not tbit) (delay 1 (set pc disp8)))) (dshci bra "Branch" () "bra $disp12" (+ (f-op4 10) disp12) (delay 1 (set pc disp12))) (dshci braf "Branch far" () "braf $rn" (+ (f-op4 0) rn (f-sub8 35)) (delay 1 (set pc (add (ext DI rn) (add pc 4))))) (dshci brk "Breakpoint" () "brk" (+ (f-op16 59)) (c-call "sh64_break" pc)) (dshci bsr "Branch to subroutine" () "bsr $disp12" (+ (f-op4 11) disp12) (delay 1 (sequence () (set pr (add pc 4)) (set pc disp12)))) (dshci bsrf "Branch to far subroutine" () "bsrf $rn" (+ (f-op4 0) rn (f-sub8 3)) (delay 1 (sequence () (set pr (add pc 4)) (set pc (add (ext DI rn) (add pc 4)))))) (dshci bt "Conditional branch" () "bt $disp8" (+ (f-op8 #x89) disp8) (if tbit (set pc disp8))) (dshci bts "Conditional branch with delay slot" () "bt/s $disp8" (+ (f-op8 #x8d) disp8) (if tbit (delay 1 (set pc disp8)))) (dshci clrmac "Clear MACL and MACH" () "clrmac" (+ (f-op16 40)) (sequence () (set macl 0) (set mach 0))) (dshci clrs "Clear S-bit" () "clrs" (+ (f-op16 72)) (set sbit 0)) (dshci clrt "Clear T-bit" () "clrt" (+ (f-op16 8)) (set tbit 0)) (dshci cmpeq "Compare if equal" () "cmp/eq $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 0)) (set tbit (eq rm rn))) (dshci cmpeqi "Compare if equal (immediate)" () "cmp/eq #$imm8, r0" (+ (f-op8 #x88) imm8) (set tbit (eq r0 (ext SI (and QI imm8 255))))) (dshci cmpge "Compare if greater than or equal" () "cmp/ge $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 3)) (set tbit (ge rn rm))) (dshci cmpgt "Compare if greater than" () "cmp/gt $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 7)) (set tbit (gt rn rm))) (dshci cmphi "Compare if greater than (unsigned)" () "cmp/hi $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 6)) (set tbit (gtu rn rm))) (dshci cmphs "Compare if greater than or equal (unsigned)" () "cmp/hs $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 2)) (set tbit (geu rn rm))) (dshci cmppl "Compare if greater than zero" () "cmp/pl $rn" (+ (f-op4 4) rn (f-sub8 21)) (set tbit (gt rn 0)))Lines 1–500 of 1748. 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; Hitachi SHcompact instruction set description. -*- Scheme -*- ; ; Copyright 2000, 2007, 2009 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; developed under contract from Hitachi ; Semiconductor (America) Inc. ; ; This file is part of the GNU Binutils. ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ; MA 02110-1301, USA. ; dshcf -- define-normal-sh-compact-field (define-pmacro (dshcf xname xcomment ignored xstart xlength) (dnf xname xcomment ((ISA compact)) xstart xlength)) ; dshcop -- define-normal-sh-compact-operand (define-pmacro (dshcop xname xcomment ignored xhardware xfield) (dnop xname xcomment ((ISA compact)) xhardware xfield)) ; SHcompact-specific attributes. (define-attr (for insn) (type boolean) (name ILLSLOT) (comment "instruction may not appear in a delay slot") ) (define-attr (for insn) (type boolean) (name FP-INSN) (comment "floating point instruction") ) (define-keyword (name frc-names) (attrs (ISA compact)) (print-name h-frc) (values (fr0 0) (fr1 1) (fr2 2) (fr3 3) (fr4 4) (fr5 5) (fr6 6) (fr7 7) (fr8 8) (fr9 9) (fr10 10) (fr11 11) (fr12 12) (fr13 13) (fr14 14) (fr15 15)) ) (define-keyword (name drc-names) (attrs (ISA compact)) (print-name h-drc) (values (dr0 0) (dr2 2) (dr4 4) (dr6 6) (dr8 8) (dr10 10) (dr12 12) (dr14 14)) ) (define-keyword (name xf-names) (attrs (ISA compact)) (print-name h-xf) (values (xf0 0) (xf1 1) (xf2 2) (xf3 3) (xf4 4) (xf5 5) (xf6 6) (xf7 7) (xf8 8) (xf9 9) (xf10 10) (xf11 11) (xf12 12) (xf13 13) (xf14 14) (xf15 15)) ) ; Hardware specific to the SHcompact mode. (define-pmacro (front) (mul 16 frbit)) (define-pmacro (back) (mul 16 (not frbit))) (define-hardware (name h-frc) (comment "Single precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword frc-names) (type register SF (16)) (get (index) (reg h-fr (add (front) index))) (set (index newval) (set (reg h-fr (add (front) index)) newval)) ) (define-hardware (name h-drc) (comment "Double precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword drc-names) (type register DF (8)) (get (index) (reg h-dr (add (front) index))) (set (index newval) (set (reg h-dr (add (front) index)) newval)) ) (define-hardware (name h-xf) (comment "Extended single precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword xf-names) (type register SF (16)) (get (index) (reg h-fr (add (back) index))) (set (index newval) (set (reg h-fr (add (back) index)) newval)) ) (define-hardware (name h-xd) (comment "Extended double precision floating point registers") (attrs VIRTUAL (ISA compact)) (indices extern-keyword frc-names) (type register DF (8)) (get (index) (reg h-dr (add (back) index))) (set (index newval) (set (reg h-dr (add (back) index)) newval)) ) (define-hardware (name h-fvc) (comment "Single precision floating point vectors") (attrs VIRTUAL (ISA compact)) (indices keyword "" ((fv0 0) (fv4 4) (fv8 8) (fv12 12))) (type register SF (4)) (get (index) (reg h-fr (add (front) index))) (set (index newval) (set (reg h-fr (add (front) index)) newval)) ) (define-hardware (name h-fpccr) (comment "SHcompact floating point status/control register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21))) (set (newvalue) (sequence () (set (reg h-fpscr) newvalue) (set prbit (and (srl newvalue 19) 1)) (set szbit (and (srl newvalue 20) 1)) (set frbit (and (srl newvalue 21) 1)))) ) (define-hardware (name h-gbr) (comment "Global base register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 16) 1)) (set (newval) (set (raw-reg h-gr 16) (ext DI newval))) ) (define-hardware (name h-pr) (comment "Procedure link register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 18) 1)) (set (newval) (set (raw-reg h-gr 18) (ext DI newval))) ) (define-hardware (name h-macl) (comment "Multiple-accumulate low register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 17) 1)) (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval))) ) (define-hardware (name h-mach) (comment "Multiply-accumulate high register") (attrs VIRTUAL (ISA compact)) (type register SI) (get () (subword SI (raw-reg h-gr 17) 0)) (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1)))) ) (define-hardware (name h-tbit) (comment "Condition code flag") (attrs VIRTUAL (ISA compact)) (type register BI) (get () (and BI (raw-reg h-gr 19) 1)) (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval)))) ) (dshcf f-op4 "Opcode (4 bits)" () 15 4) (dshcf f-op8 "Opcode (8 bits)" () 15 8) (dshcf f-op16 "Opcode (16 bits)" () 15 16) (dshcf f-sub4 "Sub opcode (4 bits)" () 3 4) (dshcf f-sub8 "Sub opcode (8 bits)" () 7 8) (dshcf f-sub10 "Sub opcode (10 bits)" () 9 10) (dshcf f-rn "Register selector n" () 11 4) (dshcf f-rm "Register selector m" () 7 4) (dshcf f-8-1 "One bit at bit 8" () 8 1) (df f-disp8 "Displacement (8 bits)" ((ISA compact) PCREL-ADDR) 7 8 INT ((value pc) (sra SI value 1)) ((value pc) (add SI (sll SI value 1) (add pc 4)))) (df f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT ((value pc) (sra SI value 1)) ((value pc) (add SI (sll SI value 1) (add pc 4)))) (dshcf f-imm8 "Immediate (8 bits)" () 7 8) (dshcf f-imm4 "Immediate (4 bits)" () 3 4) (df f-imm4x2 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT ((value pc) (srl SI value 1)) ((value pc) (sll SI value 1))) (df f-imm4x4 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2))) (df f-imm8x2 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT ((value pc) (sra SI value 1)) ((value pc) (sll SI value 1))) (df f-imm8x4 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT ((value pc) (sra SI value 2)) ((value pc) (sll SI value 2))) (df f-dn "Double selector n" ((ISA compact)) 11 3 UINT ((value pc) (srl SI value 1)) ((value pc) (sll SI value 1))) (df f-dm "Double selector m" ((ISA compact)) 7 3 UINT ((value pc) (srl SI value 1)) ((value pc) (sll SI value 1))) (df f-vn "Vector selector n" ((ISA compact)) 11 2 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2))) (df f-vm "Vector selector m" ((ISA compact)) 9 2 UINT ((value pc) (srl SI value 2)) ((value pc) (sll SI value 2))) (df f-xn "Extended selector n" ((ISA compact)) 11 3 UINT ((value pc) (srl SI value 1)) ((value pc) (add SI (sll SI value 1) 1))) (df f-xm "Extended selector m" ((ISA compact)) 7 3 UINT ((value pc) (srl SI value 1)) ((value pc) (add SI (sll SI value 1) 1))) ; Operands. (dshcop rm "Left general purpose register" () h-grc f-rm) (dshcop rn "Right general purpose register" () h-grc f-rn) (dshcop r0 "Register 0" () h-grc 0) (dshcop frn "Single precision register" () h-frc f-rn) (dshcop frm "Single precision register" () h-frc f-rm) (dshcop fvn "Left floating point vector" () h-fvc f-vn) (dshcop fvm "Right floating point vector" () h-fvc f-vm) (dshcop drn "Left double precision register" () h-drc f-dn) (dshcop drm "Right double precision register" () h-drc f-dm) (dshcop imm4 "Immediate value (4 bits)" () h-sint f-imm4) (dshcop imm8 "Immediate value (8 bits)" () h-sint f-imm8) (dshcop uimm8 "Immediate value (8 bits unsigned)" () h-uint f-imm8) (dshcop imm4x2 "Immediate value (4 bits, 2x scale)" () h-uint f-imm4x2) (dshcop imm4x4 "Immediate value (4 bits, 4x scale)" () h-uint f-imm4x4) (dshcop imm8x2 "Immediate value (8 bits, 2x scale)" () h-uint f-imm8x2) (dshcop imm8x4 "Immediate value (8 bits, 4x scale)" () h-uint f-imm8x4) (dshcop disp8 "Displacement (8 bits)" () h-iaddr f-disp8) (dshcop disp12 "Displacement (12 bits)" () h-iaddr f-disp12) (dshcop rm64 "Register m (64 bits)" () h-gr f-rm) (dshcop rn64 "Register n (64 bits)" () h-gr f-rn) (dshcop gbr "Global base register" () h-gbr f-nil) (dshcop pr "Procedure link register" () h-pr f-nil) (dshcop fpscr "Floating point status/control register" () h-fpccr f-nil) (dshcop tbit "Condition code flag" () h-tbit f-nil) (dshcop sbit "Multiply-accumulate saturation flag" () h-sbit f-nil) (dshcop mbit "Divide-step M flag" () h-mbit f-nil) (dshcop qbit "Divide-step Q flag" () h-qbit f-nil) (dshcop fpul "Floating point ???" () h-fr 32) (dshcop frbit "Floating point register bank bit" () h-frbit f-nil) (dshcop szbit "Floating point transfer size bit" () h-szbit f-nil) (dshcop prbit "Floating point precision bit" () h-prbit f-nil) (dshcop macl "Multiply-accumulate low register" () h-macl f-nil) (dshcop mach "Multiply-accumulate high register" () h-mach f-nil) (define-operand (name fsdm) (comment "bar") (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd"))) (define-operand (name fsdn) (comment "bar") (attrs (ISA compact)) (type h-frc) (index f-rn)) ; Cover macro to dni to indicate these are all SHcompact instructions. ; dshmi: define-normal-sh-compact-insn (define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics) (define-insn (name (.sym xname -compact)) (comment xcomment) (.splice attrs (.unsplice xattrs) (ISA compact)) (syntax xsyntax) (format xformat) (semantics xsemantics))) (define-pmacro (dr operand) (reg h-dr (index-of operand))) (define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1)))) (dshci add "Add" () "add $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 12)) (set rn (add rn rm))) (dshci addi "Add immediate" () "add #$imm8, $rn" (+ (f-op4 7) rn imm8) (set rn (add rn (ext SI (and QI imm8 255))))) (dshci addc "Add with carry" () "addc $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 14)) (sequence ((BI flag)) (set flag (add-cflag rn rm tbit)) (set rn (addc rn rm tbit)) (set tbit flag))) (dshci addv "Add with overflow" () "addv $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 15)) (sequence ((BI t)) (set t (add-oflag rn rm 0)) (set rn (add rn rm)) (set tbit t))) (dshci and "Bitwise AND" () "and $rm64, $rn64" (+ (f-op4 2) rn64 rm64 (f-sub4 9)) (set rn64 (and rm64 rn64))) (dshci andi "Bitwise AND immediate" () "and #$uimm8, r0" (+ (f-op8 #xc9) uimm8) (set r0 (and r0 (zext DI uimm8)))) (dshci andb "Bitwise AND memory byte" () "and.b #$imm8, @(r0, gbr)" (+ (f-op8 #xcd) imm8) (sequence ((DI addr) (UQI data)) (set addr (add r0 gbr)) (set data (and (mem UQI addr) imm8)) (set (mem UQI addr) data))) (dshci bf "Conditional branch" () "bf $disp8" (+ (f-op8 #x8b) disp8) (if (not tbit) (set pc disp8))) (dshci bfs "Conditional branch with delay slot" () "bf/s $disp8" (+ (f-op8 #x8f) disp8) (if (not tbit) (delay 1 (set pc disp8)))) (dshci bra "Branch" () "bra $disp12" (+ (f-op4 10) disp12) (delay 1 (set pc disp12))) (dshci braf "Branch far" () "braf $rn" (+ (f-op4 0) rn (f-sub8 35)) (delay 1 (set pc (add (ext DI rn) (add pc 4))))) (dshci brk "Breakpoint" () "brk" (+ (f-op16 59)) (c-call "sh64_break" pc)) (dshci bsr "Branch to subroutine" () "bsr $disp12" (+ (f-op4 11) disp12) (delay 1 (sequence () (set pr (add pc 4)) (set pc disp12)))) (dshci bsrf "Branch to far subroutine" () "bsrf $rn" (+ (f-op4 0) rn (f-sub8 3)) (delay 1 (sequence () (set pr (add pc 4)) (set pc (add (ext DI rn) (add pc 4)))))) (dshci bt "Conditional branch" () "bt $disp8" (+ (f-op8 #x89) disp8) (if tbit (set pc disp8))) (dshci bts "Conditional branch with delay slot" () "bt/s $disp8" (+ (f-op8 #x8d) disp8) (if tbit (delay 1 (set pc disp8)))) (dshci clrmac "Clear MACL and MACH" () "clrmac" (+ (f-op16 40)) (sequence () (set macl 0) (set mach 0))) (dshci clrs "Clear S-bit" () "clrs" (+ (f-op16 72)) (set sbit 0)) (dshci clrt "Clear T-bit" () "clrt" (+ (f-op16 8)) (set tbit 0)) (dshci cmpeq "Compare if equal" () "cmp/eq $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 0)) (set tbit (eq rm rn))) (dshci cmpeqi "Compare if equal (immediate)" () "cmp/eq #$imm8, r0" (+ (f-op8 #x88) imm8) (set tbit (eq r0 (ext SI (and QI imm8 255))))) (dshci cmpge "Compare if greater than or equal" () "cmp/ge $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 3)) (set tbit (ge rn rm))) (dshci cmpgt "Compare if greater than" () "cmp/gt $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 7)) (set tbit (gt rn rm))) (dshci cmphi "Compare if greater than (unsigned)" () "cmp/hi $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 6)) (set tbit (gtu rn rm))) (dshci cmphs "Compare if greater than or equal (unsigned)" () "cmp/hs $rm, $rn" (+ (f-op4 3) rn rm (f-sub4 2)) (set tbit (geu rn rm))) (dshci cmppl "Compare if greater than zero" () "cmp/pl $rn" (+ (f-op4 4) rn (f-sub8 21)) (set tbit (gt rn 0)))