; Morpho Technologies MT Arch description. -*- Scheme -*-; Copyright 2001, 2007, 2009 Free Software Foundation, Inc.;; Contributed by Red Hat Inc; developed under contract from; Morpho Technologies.;; This file is part of the GNU Binutils.;; This program is free software; you can redistribute it and/or modify; it under the terms of the GNU General Public License as published by; the Free Software Foundation; either version 3 of the License, or; (at your option) any later version.;; This program is distributed in the hope that it will be useful,; but WITHOUT ANY WARRANTY; without even the implied warranty of; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License; along with this program; if not, write to the Free Software; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,; MA 02110-1301, USA. (include "simplify.inc") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; define-arch must appear first(define-arch (name mt) ; name of cpu family (comment "Morpho Technologies mRISC family") (default-alignment aligned) (insn-lsb0? #t) (machs ms1 ms1-003 ms2) (isas mt)) ; Instruction set parameters. (define-isa (name mt) (comment "Morpho Technologies MT ISA") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) (parallel-insns 2)) ; Cpu family definitions. (define-cpu ; cpu names must be distinct from the architecture name and machine names. (name ms1bf) (comment "Morpho Technologies mRISC family") (endian big) (word-bitsize 32)) (define-cpu ; cpu names must be distinct from the architecture name and machine names. (name ms1-003bf) (comment "Morpho Technologies mRISC family") (endian big) (word-bitsize 32)) (define-cpu ; cpu names must be distinct from the architecture name and machine names. (name ms2bf) (comment "Morpho Technologies mRISC family") (endian big) (word-bitsize 32)) (define-mach (name ms1) (comment "Morpho Technologies mrisc") (cpu ms1bf) (isas mt)) (define-mach (name ms1-003) (comment "Morpho Technologies mrisc") (cpu ms1-003bf) (isas mt)) (define-mach (name ms2) (comment "Morpho Technologies ms2") (cpu ms2bf) (isas mt)) ; Model descriptions.; Can probably take the u-exec out. We'll see.(define-model (name ms1) (comment "Morpho Technologies mrisc") (mach ms1) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) )) (define-model (name ms1-003) (comment "Morpho Technologies mrisc") (mach ms1-003) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) )) (define-model (name ms2) (comment "Morpho Technologies ms2") (mach ms2) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) )) ; FIXME: It might simplify things to separate the execute process from the; one that updates the PC. ;;;;;;;;;;;;;;;;;;;;;;;;;; Instruction Fields ;;;;;;;;;;;;;;;;;;;;;;;;;; ; Attributes:; PCREL-ADDR: pc relative value (for reloc and disassembly purposes); ABS-ADDR: absolute address (for reloc and disassembly purposes?); RESERVED: bits are not used to decode insn, must be all 0; RELOC: there is a relocation associated with this field (experiment);; f-msys: Identify a a morphosys insns. 1 if msys, 0 if not.; f-opc: 6 bit opcode for non-morphosys instructions.; f-msopc: 6 bit opcode for morphosys instructions.; f-imm: flag to indicate use of an immediate operand. 1 if yes, 0 if no.; f-sr1: source resgister 1. (also used for MSYS insns); f-sr2: source register 2. (also used for MSYS insns); f-dr: destination register when located in bits 19:16.; f-drrr: destination register when located in bits 15:12. (also for MSYS insns); f-imm16: 16 bit immediate value when not an offset.; f-imm16a: 16 bit immediate value when it's a pc-rel offset.; f-uu4a: unused 4 bit field.; f-uu4b: second unsed 4 bit field.; f-uu1: unused 1 bit field; f-uu12: unused 12 bit field.; f-uu16: unused 16 bit field.; f-uu24: unused 24 bit field. (dnf f-msys "morphosys insn flag" () 31 1)(dnf f-opc "opcode field" () 30 6)(dnf f-imm "immedate flag" () 24 1)(dnf f-uu24 "unused 24 bits" () 23 24)(dnf f-sr1 "sr1 register field" (ABS-ADDR) 23 4)(dnf f-sr2 "sr2 register field" (ABS-ADDR) 19 4)(dnf f-dr "dr register field" (ABS-ADDR) 19 4)(dnf f-drrr "drrr register field" (ABS-ADDR) 15 4)(dnf f-imm16u "unsigned 16 bit immediate" () 15 16)(df f-imm16s "signed 16 bit immediate" () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0)))(dnf f-imm16a "pc-rel offset" (PCREL-ADDR) 15 16)(dnf f-uu4a "unused 4 bit field" () 19 4)(dnf f-uu4b "unused 4 bit field" () 23 4)(dnf f-uu12 "unused 12 bit field" () 11 12)(dnf f-uu8 "unused 8 bit field" () 15 8)(dnf f-uu16 "unused 16 bit field" () 15 16)(dnf f-uu1 "unused 1 bit field" () 7 1) ; The following ifields are used exclusively for the MorphoSys instructions.; In a few cases, a bit field is used for something in addition to what its; name suggests. For the most part, the names are meaningful though. (dnf f-msopc "opcode field" () 30 5)(dnf f-uu-26-25 "unused 26 bits" () 25 26)(dnf f-mask "mask" () 25 16)(dnf f-bankaddr "bank address" () 25 13)(dnf f-rda "rda" () 25 1)(dnf f-uu-2-25 "unused bits 25 & 24" () 25 2)(dnf f-rbbc "Omega network configuration" () 25 2)(dnf f-perm "perm" () 25 2)(dnf f-mode "mode" () 25 2)(dnf f-uu-1-24 "testing" () 24 1)(dnf f-wr "wr" () 24 1)(dnf f-fbincr "fb incr" () 23 4)(dnf f-uu-2-23 "unused bits 23 and 22" () 23 2)(dnf f-xmode "xmode" () 23 1)(dnf f-a23 "a23" () 23 1)(dnf f-mask1 "mask1" () 22 3)(dnf f-cr "cr" () 22 3)(dnf f-type "type" () 21 2)(dnf f-incamt "increment amount" () 19 8)(dnf f-cbs "cbs" () 19 2)(dnf f-uu-1-19 "unused bit 19" () 19 1)(dnf f-ball "b_all" () 19 1)(dnf f-colnum "column number" () 18 3)(dnf f-brc "b_r_c" () 18 3)(dnf f-incr "incr" () 17 6)(dnf f-fbdisp "frame buffer displacement" () 15 6)(dnf f-uu-4-15 "unused bits 15,14,13,12" () 15 4)(dnf f-length "length" () 15 3)(dnf f-uu-1-15 "unused bit 15" () 15 1)(dnf f-rc "row/column context" () 15 1)(dnf f-rcnum "starting cell of cntxt mem." () 14 3)(dnf f-rownum "row number" () 14 3)(dnf f-cbx "cbx" () 14 3)(dnf f-id "id" () 14 1)(dnf f-size "size" () 13 14)(dnf f-rownum1 "row number" () 12 3)(dnf f-uu-3-11 "unused 3 bits (11-9)" () 11 3)(dnf f-rc1 "row/column context" () 11 1)(dnf f-ccb "ccb" () 11 1)(dnf f-cbrb "data-bus orientation" () 10 1)(dnf f-cdb "cdb" () 10 1)(dnf f-rownum2 "row number" () 9 3)(dnf f-cell "cell" () 9 3)(dnf f-uu-3-9 "unused 3 bits (9-7)" () 9 3)(dnf f-contnum "context number" () 8 9)(dnf f-uu-1-6 "unused bit 6" () 6 1)(dnf f-dup "dup" () 6 1)(dnf f-rc2 "rc2" () 6 1)(dnf f-ctxdisp "context displacement" () 5 6) ; additional fields in ms2(dnf f-imm16l "loop count" () 23 16)(df f-loopo "loop offset" () 7 8 UINT ((value pc) (srl SI value 2)) ((value pc) (add SI (sll value 2) 8)) )(dnf f-cb1sel "cb1 select" () 25 3)(dnf f-cb2sel "cb2 select" () 22 3)(dnf f-cb1incr "cb1 increment" (SIGNED) 19 6)(dnf f-cb2incr "cb2 increment" (SIGNED) 13 6)(dnf f-rc3 "row/colum context" () 7 1) ; The following is just for a test(dnf f-msysfrsr2 "sr2 for msys" () 19 4)(dnf f-brc2 "b_r_c2" () 14 3)(dnf f-ball2 "b_all2" () 15 1) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Enumerations Of Instruction Fields ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; insn-msys: bit 31. 1 for Morphosys Insns, 0 if not.(define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys (NO YES)) ; insn-opc: bits 30 through 25 . Non-MorphoSys Instructions; Note - the documentation is wrong for the encoding of the DBNZ; instruction. It is actually 011110. See Issue 67699.(define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc (ADD ADDU SUB SUBU MUL - - - AND OR XOR NAND NOR XNOR LDUI - LSL LSR ASR - - - - - BRLT BRLE BREQ JMP JAL BRNEQ DBNZ LOOP LDW STW - - - - - - - - - - - - - - EI DI SI RETI BREAK IFLUSH - - )) ; insn-msopc: bits 30 through 26 . MorphoSys Instructions(define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc (LDCTXT LDFB STFB FBCB MFBCB FBCCI FBRCI FBCRI FBRRI MFBCCI MFBRCI MFBCRI MFBRRI FBCBDR RCFBCB MRCFBCB CBCAST DUPCBCAST WFBI WFB RCRISC FBCBINC RCXMODE INTLVR WFBINC MWFBINC WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS - - - - - - - - )) ; insn-imm: bit 24. Immediate operand indicator.(define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm ; This bit specifies whether and immediate operand will be present. ; It's 1 if there is, 0 if there is not. (NO YES));;;;;;;;;;;;;;;;;; Attributes ;;;;;;;;;;;;;;;;;; ; Might not need this. Keep if for the sim just in case.;(define-attr; (for insn); (type boolean); (name EXT-SKIP-INSN); (comment "instruction is a PAGE, LOADL or LOADH instruction");) (define-attr (for insn) (type boolean) (name LOAD-DELAY) (comment "insn has a load delay")) (define-attr (for insn) (type boolean) (name MEMORY-ACCESS) (comment "insn performs a memory access")) (define-attr (for insn) (type boolean) (name AL-INSN) (comment "insn is an arithmetic or logic insn.")) (define-attr (for insn) (type boolean) (name IO-INSN) (comment "insn performs an I/O operation")) (define-attr (for insn) (type boolean) (name BR-INSN) (comment "insn performs an I/O operation")) (define-attr (for insn) (type boolean) (name JAL-HAZARD) (comment "insn has jal-like hazard")) (define-pmacro (define-reg-use-attr regfield) (define-attr (for insn) (type boolean) (name (.sym "USES-" (.upcase regfield))) (comment ("insn accesses register operand " regfield)))) (define-reg-use-attr "frdr")(define-reg-use-attr "frdrrr")(define-reg-use-attr "frsr1")(define-reg-use-attr "frsr2") ; Might not need this. Keep it for the sim just in case.(define-attr (for insn) (type boolean) (name SKIPA) (comment "instruction is a SKIP instruction")) ;;;;;;;;;;;;;;;;;;;;; ;; Hardware Pieces ;;;;;;;;;;;;;;;;;;;;;;; ;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n)) ; These are the 16 registers that the chip has. In later versions; where there will be more registers, this will need to be expanded.; Note that there are two entries for the registers with two names.(define-hardware (name h-spr) (comment "special-purpose registers") (type register SI (16)) (indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5) ("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12) ("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15))); (get (index) (and (raw-reg h-spr) #xffffffff)); (set (index value) (set (raw-reg h-spr) (and value #xffffffff)))) ; This is the program counter.(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) (define-keyword (name msys-syms) (print-name h-nil) (prefix "") (values (DUP 1) (XX 0))) ;;;;;;;;;;;;;;;; Operands ;;;;;;;;;;;;;;;; (define-operand (name frsr1) (comment "register") (attrs) (type h-spr) (index f-sr1) )(define-operand (name frsr2) (comment "register") (attrs) (type h-spr) (index f-sr2) )(define-operand (name frdr) (comment "register") (attrs) (type h-spr) (index f-dr) )(define-operand (name frdrrr) (comment "register") (attrs) (type h-spr) (index f-drrr) )(define-operand (name imm16) (comment "immediate value - sign extd") (attrs) (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))(define-operand (name imm16z) (comment "immediate value - zero extd") (attrs) (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex")))(define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR) (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel"))) ; Operands for MorphoSys Instructions (define-operand (name rc) (comment "rc") (attrs) (type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex"))) (define-operand (name rcnum) (comment "rcnum") (attrs) (type h-uint) (index f-rcnum) (handlers (print "dollarhex"))) (define-operand (name contnum) (comment "context number") (attrs) (type h-uint) (index f-contnum) (handlers (print "dollarhex"))) (define-operand (name rbbc) (comment "omega network configuration") (attrs) (type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex"))) (define-operand (name colnum) (comment "column number") (attrs) (type h-uint) (index f-colnum) (handlers (print "dollarhex"))) (define-operand (name rownum) (comment "row number") (attrs) (type h-uint) (index f-rownum) (handlers (print "dollarhex"))) (define-operand (name rownum1) (comment "row number") (attrs) (type h-uint) (index f-rownum1) (handlers (print "dollarhex"))) (define-operand (name rownum2) (comment "row number") (attrs) (type h-uint) (index f-rownum2) (handlers (print "dollarhex"))) (define-operand (name rc1) (comment "rc1") (attrs) (type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex"))) (define-operand (name rc2) (comment "rc2") (attrs) (type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex"))) (define-operand (name cbrb) (comment "data-bus orientation") (attrs) (type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex"))) (define-operand (name cell) (comment "cell") (attrs) (type h-uint) (index f-cell) (handlers (print "dollarhex"))) (define-operand (name dup) (comment "dup") (attrs) (type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex"))) (define-operand (name ctxdisp) (comment "context displacement") (attrs) (type h-uint) (index f-ctxdisp) (handlers (print "dollarhex"))) (define-operand (name fbdisp) (comment "frame buffer displacement") (attrs) (type h-uint) (index f-fbdisp) (handlers (print "dollarhex"))) (define-operand (name type) (comment "type") (attrs) (type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex"))) (define-operand (name mask) (comment "mask") (attrs) (type h-uint) (index f-mask) (handlers (print "dollarhex"))) (define-operand (name bankaddr) (comment "bank address") (attrs) (type h-uint) (index f-bankaddr) (handlers (print "dollarhex"))) (define-operand (name incamt) (comment "increment amount") (attrs) (type h-uint) (index f-incamt) (handlers (print "dollarhex"))) (define-operand (name xmode) (comment "xmode") (attrs) (type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex"))) (define-operand (name mask1) (comment "mask1") (attrs) (type h-uint) (index f-mask1) (handlers (print "dollarhex"))) (define-operand (name ball) (comment "b_all") (attrs) (type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex"))) (define-operand (name brc) (comment "b_r_c") (attrs) (type h-uint) (index f-brc) (handlers (print "dollarhex"))) (define-operand (name rda) (comment "rd") (attrs) (type h-uint) (index f-rda) (handlers (print "dollarhex"))) (define-operand (name wr) (comment "wr") (attrs) Lines 1–500 of 1352. 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; Morpho Technologies MT Arch description. -*- Scheme -*- ; Copyright 2001, 2007, 2009 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; developed under contract from ; Morpho Technologies. ; ; This file is part of the GNU Binutils. ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ; MA 02110-1301, USA. (include "simplify.inc") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; define-arch must appear first (define-arch (name mt) ; name of cpu family (comment "Morpho Technologies mRISC family") (default-alignment aligned) (insn-lsb0? #t) (machs ms1 ms1-003 ms2) (isas mt) ) ; Instruction set parameters. (define-isa (name mt) (comment "Morpho Technologies MT ISA") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) (parallel-insns 2) ) ; Cpu family definitions. (define-cpu ; cpu names must be distinct from the architecture name and machine names. (name ms1bf) (comment "Morpho Technologies mRISC family") (endian big) (word-bitsize 32) ) (define-cpu ; cpu names must be distinct from the architecture name and machine names. (name ms1-003bf) (comment "Morpho Technologies mRISC family") (endian big) (word-bitsize 32) ) (define-cpu ; cpu names must be distinct from the architecture name and machine names. (name ms2bf) (comment "Morpho Technologies mRISC family") (endian big) (word-bitsize 32) ) (define-mach (name ms1) (comment "Morpho Technologies mrisc") (cpu ms1bf) (isas mt) ) (define-mach (name ms1-003) (comment "Morpho Technologies mrisc") (cpu ms1-003bf) (isas mt) ) (define-mach (name ms2) (comment "Morpho Technologies ms2") (cpu ms2bf) (isas mt) ) ; Model descriptions. ; Can probably take the u-exec out. We'll see. (define-model (name ms1) (comment "Morpho Technologies mrisc") (mach ms1) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ) (define-model (name ms1-003) (comment "Morpho Technologies mrisc") (mach ms1-003) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ) (define-model (name ms2) (comment "Morpho Technologies ms2") (mach ms2) (unit u-exec "Execution Unit" () 1 1 ; issue done () ; state () ; inputs () ; outputs () ; profile action (default) ) ) ; FIXME: It might simplify things to separate the execute process from the ; one that updates the PC. ;;;;;;;;;;;;;;;;;;;;;;;; ;; Instruction Fields ;; ;;;;;;;;;;;;;;;;;;;;;;;; ; Attributes: ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) ; ABS-ADDR: absolute address (for reloc and disassembly purposes?) ; RESERVED: bits are not used to decode insn, must be all 0 ; RELOC: there is a relocation associated with this field (experiment) ; ; f-msys: Identify a a morphosys insns. 1 if msys, 0 if not. ; f-opc: 6 bit opcode for non-morphosys instructions. ; f-msopc: 6 bit opcode for morphosys instructions. ; f-imm: flag to indicate use of an immediate operand. 1 if yes, 0 if no. ; f-sr1: source resgister 1. (also used for MSYS insns) ; f-sr2: source register 2. (also used for MSYS insns) ; f-dr: destination register when located in bits 19:16. ; f-drrr: destination register when located in bits 15:12. (also for MSYS insns) ; f-imm16: 16 bit immediate value when not an offset. ; f-imm16a: 16 bit immediate value when it's a pc-rel offset. ; f-uu4a: unused 4 bit field. ; f-uu4b: second unsed 4 bit field. ; f-uu1: unused 1 bit field ; f-uu12: unused 12 bit field. ; f-uu16: unused 16 bit field. ; f-uu24: unused 24 bit field. (dnf f-msys "morphosys insn flag" () 31 1) (dnf f-opc "opcode field" () 30 6) (dnf f-imm "immedate flag" () 24 1) (dnf f-uu24 "unused 24 bits" () 23 24) (dnf f-sr1 "sr1 register field" (ABS-ADDR) 23 4) (dnf f-sr2 "sr2 register field" (ABS-ADDR) 19 4) (dnf f-dr "dr register field" (ABS-ADDR) 19 4) (dnf f-drrr "drrr register field" (ABS-ADDR) 15 4) (dnf f-imm16u "unsigned 16 bit immediate" () 15 16) (df f-imm16s "signed 16 bit immediate" () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0))) (dnf f-imm16a "pc-rel offset" (PCREL-ADDR) 15 16) (dnf f-uu4a "unused 4 bit field" () 19 4) (dnf f-uu4b "unused 4 bit field" () 23 4) (dnf f-uu12 "unused 12 bit field" () 11 12) (dnf f-uu8 "unused 8 bit field" () 15 8) (dnf f-uu16 "unused 16 bit field" () 15 16) (dnf f-uu1 "unused 1 bit field" () 7 1) ; The following ifields are used exclusively for the MorphoSys instructions. ; In a few cases, a bit field is used for something in addition to what its ; name suggests. For the most part, the names are meaningful though. (dnf f-msopc "opcode field" () 30 5) (dnf f-uu-26-25 "unused 26 bits" () 25 26) (dnf f-mask "mask" () 25 16) (dnf f-bankaddr "bank address" () 25 13) (dnf f-rda "rda" () 25 1) (dnf f-uu-2-25 "unused bits 25 & 24" () 25 2) (dnf f-rbbc "Omega network configuration" () 25 2) (dnf f-perm "perm" () 25 2) (dnf f-mode "mode" () 25 2) (dnf f-uu-1-24 "testing" () 24 1) (dnf f-wr "wr" () 24 1) (dnf f-fbincr "fb incr" () 23 4) (dnf f-uu-2-23 "unused bits 23 and 22" () 23 2) (dnf f-xmode "xmode" () 23 1) (dnf f-a23 "a23" () 23 1) (dnf f-mask1 "mask1" () 22 3) (dnf f-cr "cr" () 22 3) (dnf f-type "type" () 21 2) (dnf f-incamt "increment amount" () 19 8) (dnf f-cbs "cbs" () 19 2) (dnf f-uu-1-19 "unused bit 19" () 19 1) (dnf f-ball "b_all" () 19 1) (dnf f-colnum "column number" () 18 3) (dnf f-brc "b_r_c" () 18 3) (dnf f-incr "incr" () 17 6) (dnf f-fbdisp "frame buffer displacement" () 15 6) (dnf f-uu-4-15 "unused bits 15,14,13,12" () 15 4) (dnf f-length "length" () 15 3) (dnf f-uu-1-15 "unused bit 15" () 15 1) (dnf f-rc "row/column context" () 15 1) (dnf f-rcnum "starting cell of cntxt mem." () 14 3) (dnf f-rownum "row number" () 14 3) (dnf f-cbx "cbx" () 14 3) (dnf f-id "id" () 14 1) (dnf f-size "size" () 13 14) (dnf f-rownum1 "row number" () 12 3) (dnf f-uu-3-11 "unused 3 bits (11-9)" () 11 3) (dnf f-rc1 "row/column context" () 11 1) (dnf f-ccb "ccb" () 11 1) (dnf f-cbrb "data-bus orientation" () 10 1) (dnf f-cdb "cdb" () 10 1) (dnf f-rownum2 "row number" () 9 3) (dnf f-cell "cell" () 9 3) (dnf f-uu-3-9 "unused 3 bits (9-7)" () 9 3) (dnf f-contnum "context number" () 8 9) (dnf f-uu-1-6 "unused bit 6" () 6 1) (dnf f-dup "dup" () 6 1) (dnf f-rc2 "rc2" () 6 1) (dnf f-ctxdisp "context displacement" () 5 6) ; additional fields in ms2 (dnf f-imm16l "loop count" () 23 16) (df f-loopo "loop offset" () 7 8 UINT ((value pc) (srl SI value 2)) ((value pc) (add SI (sll value 2) 8)) ) (dnf f-cb1sel "cb1 select" () 25 3) (dnf f-cb2sel "cb2 select" () 22 3) (dnf f-cb1incr "cb1 increment" (SIGNED) 19 6) (dnf f-cb2incr "cb2 increment" (SIGNED) 13 6) (dnf f-rc3 "row/colum context" () 7 1) ; The following is just for a test (dnf f-msysfrsr2 "sr2 for msys" () 19 4) (dnf f-brc2 "b_r_c2" () 14 3) (dnf f-ball2 "b_all2" () 15 1) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; Enumerations Of Instruction Fields ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; insn-msys: bit 31. 1 for Morphosys Insns, 0 if not. (define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys (NO YES) ) ; insn-opc: bits 30 through 25 . Non-MorphoSys Instructions ; Note - the documentation is wrong for the encoding of the DBNZ ; instruction. It is actually 011110. See Issue 67699. (define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc (ADD ADDU SUB SUBU MUL - - - AND OR XOR NAND NOR XNOR LDUI - LSL LSR ASR - - - - - BRLT BRLE BREQ JMP JAL BRNEQ DBNZ LOOP LDW STW - - - - - - - - - - - - - - EI DI SI RETI BREAK IFLUSH - - ) ) ; insn-msopc: bits 30 through 26 . MorphoSys Instructions (define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc (LDCTXT LDFB STFB FBCB MFBCB FBCCI FBRCI FBCRI FBRRI MFBCCI MFBRCI MFBCRI MFBRRI FBCBDR RCFBCB MRCFBCB CBCAST DUPCBCAST WFBI WFB RCRISC FBCBINC RCXMODE INTLVR WFBINC MWFBINC WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS - - - - - - - - ) ) ; insn-imm: bit 24. Immediate operand indicator. (define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm ; This bit specifies whether and immediate operand will be present. ; It's 1 if there is, 0 if there is not. (NO YES) ) ;;;;;;;;;;;;;;;; ;; Attributes ;; ;;;;;;;;;;;;;;;; ; Might not need this. Keep if for the sim just in case. ;(define-attr ; (for insn) ; (type boolean) ; (name EXT-SKIP-INSN) ; (comment "instruction is a PAGE, LOADL or LOADH instruction") ;) (define-attr (for insn) (type boolean) (name LOAD-DELAY) (comment "insn has a load delay") ) (define-attr (for insn) (type boolean) (name MEMORY-ACCESS) (comment "insn performs a memory access") ) (define-attr (for insn) (type boolean) (name AL-INSN) (comment "insn is an arithmetic or logic insn.") ) (define-attr (for insn) (type boolean) (name IO-INSN) (comment "insn performs an I/O operation") ) (define-attr (for insn) (type boolean) (name BR-INSN) (comment "insn performs an I/O operation") ) (define-attr (for insn) (type boolean) (name JAL-HAZARD) (comment "insn has jal-like hazard") ) (define-pmacro (define-reg-use-attr regfield) (define-attr (for insn) (type boolean) (name (.sym "USES-" (.upcase regfield))) (comment ("insn accesses register operand " regfield)))) (define-reg-use-attr "frdr") (define-reg-use-attr "frdrrr") (define-reg-use-attr "frsr1") (define-reg-use-attr "frsr2") ; Might not need this. Keep it for the sim just in case. (define-attr (for insn) (type boolean) (name SKIPA) (comment "instruction is a SKIP instruction") ) ;;;;;;;;;;;;;;;;;;;;; ;; Hardware Pieces ;; ;;;;;;;;;;;;;;;;;;;;; ;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n)) ; These are the 16 registers that the chip has. In later versions ; where there will be more registers, this will need to be expanded. ; Note that there are two entries for the registers with two names. (define-hardware (name h-spr) (comment "special-purpose registers") (type register SI (16)) (indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5) ("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12) ("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15))) ; (get (index) (and (raw-reg h-spr) #xffffffff)) ; (set (index value) (set (raw-reg h-spr) (and value #xffffffff))) ) ; This is the program counter. (dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) (define-keyword (name msys-syms) (print-name h-nil) (prefix "") (values (DUP 1) (XX 0)) ) ;;;;;;;;;;;;;; ;; Operands ;; ;;;;;;;;;;;;;; (define-operand (name frsr1) (comment "register") (attrs) (type h-spr) (index f-sr1) ) (define-operand (name frsr2) (comment "register") (attrs) (type h-spr) (index f-sr2) ) (define-operand (name frdr) (comment "register") (attrs) (type h-spr) (index f-dr) ) (define-operand (name frdrrr) (comment "register") (attrs) (type h-spr) (index f-drrr) ) (define-operand (name imm16) (comment "immediate value - sign extd") (attrs) (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex"))) (define-operand (name imm16z) (comment "immediate value - zero extd") (attrs) (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex"))) (define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR) (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel"))) ; Operands for MorphoSys Instructions (define-operand (name rc) (comment "rc") (attrs) (type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex"))) (define-operand (name rcnum) (comment "rcnum") (attrs) (type h-uint) (index f-rcnum) (handlers (print "dollarhex"))) (define-operand (name contnum) (comment "context number") (attrs) (type h-uint) (index f-contnum) (handlers (print "dollarhex"))) (define-operand (name rbbc) (comment "omega network configuration") (attrs) (type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex"))) (define-operand (name colnum) (comment "column number") (attrs) (type h-uint) (index f-colnum) (handlers (print "dollarhex"))) (define-operand (name rownum) (comment "row number") (attrs) (type h-uint) (index f-rownum) (handlers (print "dollarhex"))) (define-operand (name rownum1) (comment "row number") (attrs) (type h-uint) (index f-rownum1) (handlers (print "dollarhex"))) (define-operand (name rownum2) (comment "row number") (attrs) (type h-uint) (index f-rownum2) (handlers (print "dollarhex"))) (define-operand (name rc1) (comment "rc1") (attrs) (type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex"))) (define-operand (name rc2) (comment "rc2") (attrs) (type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex"))) (define-operand (name cbrb) (comment "data-bus orientation") (attrs) (type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex"))) (define-operand (name cell) (comment "cell") (attrs) (type h-uint) (index f-cell) (handlers (print "dollarhex"))) (define-operand (name dup) (comment "dup") (attrs) (type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex"))) (define-operand (name ctxdisp) (comment "context displacement") (attrs) (type h-uint) (index f-ctxdisp) (handlers (print "dollarhex"))) (define-operand (name fbdisp) (comment "frame buffer displacement") (attrs) (type h-uint) (index f-fbdisp) (handlers (print "dollarhex"))) (define-operand (name type) (comment "type") (attrs) (type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex"))) (define-operand (name mask) (comment "mask") (attrs) (type h-uint) (index f-mask) (handlers (print "dollarhex"))) (define-operand (name bankaddr) (comment "bank address") (attrs) (type h-uint) (index f-bankaddr) (handlers (print "dollarhex"))) (define-operand (name incamt) (comment "increment amount") (attrs) (type h-uint) (index f-incamt) (handlers (print "dollarhex"))) (define-operand (name xmode) (comment "xmode") (attrs) (type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex"))) (define-operand (name mask1) (comment "mask1") (attrs) (type h-uint) (index f-mask1) (handlers (print "dollarhex"))) (define-operand (name ball) (comment "b_all") (attrs) (type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex"))) (define-operand (name brc) (comment "b_r_c") (attrs) (type h-uint) (index f-brc) (handlers (print "dollarhex"))) (define-operand (name rda) (comment "rd") (attrs) (type h-uint) (index f-rda) (handlers (print "dollarhex"))) (define-operand (name wr) (comment "wr") (attrs)