; Renesas M32R CPU description.  -*- Scheme -*-;; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009; Free Software Foundation, Inc.;; Contributed by Red Hat Inc; developed under contract from Mitsubishi; Electric Corporation.;; This file is part of the GNU Binutils.;; This program is free software; you can redistribute it and/or modify; it under the terms of the GNU General Public License as published by; the Free Software Foundation; either version 3 of the License, or; (at your option) any later version.;; This program is distributed in the hope that it will be useful,; but WITHOUT ANY WARRANTY; without even the implied warranty of; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License; along with this program; if not, write to the Free Software; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,; MA 02110-1301, USA. (include "simplify.inc") ; FIXME: Delete sign extension of accumulator results.; Sign extension is done when accumulator is read. ; define-arch must appear first (define-arch  (name m32r) ; name of cpu family  (comment "Renesas M32R")  (default-alignment aligned)  (insn-lsb0? #f)  (machs m32r m32rx m32r2)  (isas m32r)) ; Attributes. ; An attribute to describe which pipeline an insn runs in.; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.; These instructions have O attribute for m32rx and OS attribute for m32r2. (define-attr  (for insn)  (type enum)  (name PIPE)  (comment "parallel execution pipeline selection")  (values NONE O S OS O_OS)) ; A derived attribute that says which insns can be executed in parallel; with others.  This is a required attribute for architectures with; parallel execution. (define-attr  (for insn)  (type enum)  (name PARALLEL)  (attrs META) ; do not define in any generated file for now  (values NO YES)  (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))) ; Instruction set parameters. (define-isa  (name m32r)   ; This is 32 because 16 bit insns always appear as pairs.  ; ??? See if this can go away.  It's only used by the disassembler (right?)  ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if  ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)  (default-insn-bitsize 32)   ; Number of bytes of insn we can initially fetch.  ; The M32R is tricky in that insns are either two 16-bit insns  ; (executed sequentially or in parallel) or one 32-bit insn.  ; So on one hand the base insn size is 16 bits, but on another it's 32.  ; 32 is chosen because:  ; - if the chip were ever bi-endian it is believed that the byte order would  ;   be based on 32 bit quantities  ; - 32 bit insns are always aligned on 32 bit boundaries  ; - the pc will never stop on a 16 bit (and not 32 bit) boundary  ;   [well actually it can, but there are no branches to such places]  (base-insn-bitsize 32)   ; Used in computing bit numbers.  (default-insn-word-bitsize 32)   ; The m32r fetches 2 insns at a time.  (liw-insns 2)   ; While the m32r can execute insns in parallel, the base mach can't  ; (other than nop).  The base mach is greatly handicapped by this, but  ; we still need to cleanly handle it.  (parallel-insns 2)   ; Initial bitnumbers to decode insns by.  (decode-assist (0 1 2 3 8 9 10 11))   ; Classification of instructions that fit in the various frames.  ; wip, not currently used  (insn-types (long ; name	       31 ; length	       (eq-attr (current-insn) LENGTH 31) ; matching insns	       (0 1 2 7 8 9 10) ; decode-assist	       )	      (short	       15	       (eq-attr (current-insn) LENGTH 15) ; matching insns	       (0 1 2 7 8 9 10)	       )	      )   ; Instruction framing.  ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed  ; serially (left->right), or two 16 bit insns executed parallelly.  ; wip, not currently used  (frame long32 ; name	 ((long)) ; list of insns in frame, plus constraint	 "$0"   ; assembler	 (+ (1 1) (31 $0)) ; value	 (sequence () (execute $0)) ; action	 )  (frame serial2x16	 ((short)	  (short))	 "$0 -> $1"	 (+ (1 0) (15 $0) (1 0) (15 $1))	 (sequence ()		   (execute $0)		   (execute $1))	 )  (frame parallel2x16	 ((short (eq-attr (current-insn) PIPE "O,BOTH"))	  (short (eq-attr (current-insn) PIPE "S,BOTH")))	 "$0 || $1"	 (+ (1 0) (15 $0) (1 1) (15 $1))	 (parallel ()		   (execute $0)		   (execute $1))	 )); Cpu family definitions. ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than; define-cpu.; ??? Have define-arch provide defaults for architecture that define-cpu can; then override [reduces duplication in define-cpu].; ??? Another way to go is to delete cpu-families entirely and have one mach; able to inherit things from another mach (would also need the ability to; not only override specific inherited things but also disable some,; e.g. if an insn wasn't supported). (define-cpu  ; cpu names must be distinct from the architecture name and machine names.  ; The "b" suffix stands for "base" and is the convention.  ; The "f" suffix stands for "family" and is the convention.  (name m32rbf)  (comment "Renesas M32R base family")  (endian either)  (word-bitsize 32)  ; Override isa spec (??? keeps things simpler, though it was more true  ; in the early days and not so much now).  (parallel-insns 1)) (define-cpu  (name m32rxf)  (comment "Renesas M32Rx family")  (endian either)  (word-bitsize 32)  ; Generated files have an "x" suffix.  (file-transform "x")) (define-cpu  (name m32r2f)  (comment "Renesas M32R2 family")  (endian either)  (word-bitsize 32)  ; Generated files have an "2" suffix.  (file-transform "2")) (define-mach  (name m32r)  (comment "Generic M32R cpu")  (cpu m32rbf)) (define-mach  (name m32rx)  (comment "M32RX cpu")  (cpu m32rxf)) (define-mach  (name m32r2)  (comment "M32R2 cpu")  (cpu m32r2f)); Model descriptions. ; The meaning of this value is wip but at the moment it's intended to describe; the implementation (i.e. what -mtune=foo does in sparc gcc).;; Notes while wip:; - format of pipeline entry:;   (pipeline name (stage1-name ...) (stage2-name ...) ...);   The contents of a stage description is wip.; - each mach must have at least one model; - the default model must be the first one;- maybe have `retire' support update total cycle count to handle current;  parallel insn cycle counting problems (define-model  (name m32r/d) (comment "m32r/d") (attrs)  (mach m32r)   ;(prefetch)  ;(retire)   (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))  (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))   ; `state' is a list of variables for recording model state  (state   ; bit mask of h-gr registers, =1 means value being loaded from memory   (h-gr UINT)   )   (unit u-exec "Execution Unit" ()	1 1 ; issue done	() ; state	((sr INT -1) (dr INT -1)) ; inputs	((dr INT -1)) ; outputs	() ; profile action (default)	)  (unit u-cmp "Compare Unit" ()	1 1 ; issue done	() ; state	((src1 INT -1) (src2 INT -1)) ; inputs	() ; outputs	() ; profile action (default)	)  (unit u-mac "Multiply/Accumulate Unit" ()	1 1 ; issue done	() ; state	((src1 INT -1) (src2 INT -1)) ; inputs	() ; outputs	() ; profile action (default)	)  (unit u-cti "Branch Unit" ()	1 1 ; issue done	() ; state	((sr INT -1)) ; inputs	((pc)) ; outputs	() ; profile action (default)	)  (unit u-load "Memory Load Unit" ()	1 1 ; issue done	() ; state	((sr INT)	 ;(ld-mem AI)	 ) ; inputs	((dr INT)) ; outputs	() ; profile action (default)	)  (unit u-store "Memory Store Unit" ()	1 1 ; issue done	() ; state	((src1 INT) (src2 INT)) ; inputs	() ; ((st-mem AI)) ; outputs	() ; profile action (default)	)) (define-model  (name test) (comment "test") (attrs)  (mach m32r)  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))  (unit u-exec "Execution Unit" ()	1 1 ; issue done	() () () ())) ; Each mach must have at least one model. (define-model  (name m32rx) (comment "m32rx") (attrs)  (mach m32rx)   ; ??? It's 6 stages but I forget the details right now.  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))   (unit u-exec "Execution Unit" ()	1 1 ; issue done	() ; state	((sr INT -1) (dr INT -1)) ; inputs	((dr INT -1)) ; outputs	() ; profile action (default)	)  (unit u-cmp "Compare Unit" ()	1 1 ; issue done	() ; state	((src1 INT -1) (src2 INT -1)) ; inputs	() ; outputs	() ; profile action (default)	)  (unit u-mac "Multiply/Accumulate Unit" ()	1 1 ; issue done	() ; state	((src1 INT -1) (src2 INT -1)) ; inputs	() ; outputs	() ; profile action (default)	)  (unit u-cti "Branch Unit" ()	1 1 ; issue done	() ; state	((sr INT -1)) ; inputs	((pc)) ; outputs	() ; profile action (default)	)  (unit u-load "Memory Load Unit" ()	1 1 ; issue done	() ; state	((sr INT)) ; inputs	((dr INT)) ; outputs	() ; profile action (default)	)  (unit u-store "Memory Store Unit" ()	1 1 ; issue done	() ; state	((src1 INT) (src2 INT)) ; inputs	() ; outputs	() ; profile action (default)	)) (define-model  (name m32r2) (comment "m32r2") (attrs)  (mach m32r2)   ; ??? It's 6 stages but I forget the details right now.  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))   (unit u-exec "Execution Unit" ()	1 1 ; issue done	() ; state	((sr INT -1) (dr INT -1)) ; inputs	((dr INT -1)) ; outputs	() ; profile action (default)	)  (unit u-cmp "Compare Unit" ()	1 1 ; issue done	() ; state	((src1 INT -1) (src2 INT -1)) ; inputs	() ; outputs	() ; profile action (default)	)  (unit u-mac "Multiply/Accumulate Unit" ()	1 1 ; issue done	() ; state	((src1 INT -1) (src2 INT -1)) ; inputs	() ; outputs	() ; profile action (default)	)  (unit u-cti "Branch Unit" ()	1 1 ; issue done	() ; state	((sr INT -1)) ; inputs	((pc)) ; outputs	() ; profile action (default)	)  (unit u-load "Memory Load Unit" ()	1 1 ; issue done	() ; state	((sr INT)) ; inputs	((dr INT)) ; outputs	() ; profile action (default)	)  (unit u-store "Memory Store Unit" ()	1 1 ; issue done	() ; state	((src1 INT) (src2 INT)) ; inputs	() ; outputs	() ; profile action (default)	)); The instruction fetch/execute cycle.; This is split into two parts as sometimes more than one instruction is; decoded at once.; The `const SI' argument to decode/execute is used to distinguish; multiple instructions processed at the same time (e.g. m32r).;; ??? This is wip, and not currently used.; ??? Needs to be moved to define-isa. ; This is how to fetch and decode an instruction. ;(define-extract;  (sequence VOID;	    (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0));		(sequence VOID;			  (set-quiet USI (scratch UHI insn1) (ifetch UHI pc));			  (decode VOID pc (and UHI insn1 (const UHI #x7fff));				  (const SI 0)));		(sequence VOID;			  (set-quiet USI (scratch USI insn) (ifetch USI pc));			  (if VOID (ne USI (and USI insn (const USI #x80000000));				     (const USI 0));			      (decode VOID pc (srl USI insn (const WI 16)) (const SI 0));			      (sequence VOID;					; ??? parallel support;					(decode VOID pc (srl USI insn (const WI 16));						(const SI 0));					(decode VOID (add AI pc (const AI 2));						(and USI insn (const WI #x7fff));						(const SI 1))))));	    );) ; This is how to execute a decoded instruction. ;(define-execute;  (sequence VOID () ; () is empty option list;	     ((AI new_pc));	     (set AI new_pc (execute: AI (const 0)) #:quiet);	     (set AI pc new_pc #:direct);	     );) ; FIXME: It might simplify things to separate the execute process from the; one that updates the PC.; Instruction fields.;; Attributes:; PCREL-ADDR: pc relative value (for reloc and disassembly purposes); ABS-ADDR: absolute address (for reloc and disassembly purposes?); RESERVED: bits are not used to decode insn, must be all 0; RELOC: there is a relocation associated with this field (experiment) (define-attr  (for ifield operand)  (type boolean)  (name RELOC)  (comment "there is a reloc associated with this field (experiment)")) (dnf f-op1       "op1"                 () 0 4)(dnf f-op2       "op2"                 () 8 4)(dnf f-cond      "cond"                () 4 4)(dnf f-r1        "r1"                  () 4 4)(dnf f-r2        "r2"                  () 12 4)(df f-simm8      "simm8"               () 8 8 INT #f #f)(df f-simm16     "simm16"              () 16 16 INT #f #f)(dnf f-shift-op2 "shift op2"           () 8 3)(dnf f-uimm3     "uimm3"               () 5 3)(dnf f-uimm4     "uimm4"               () 12 4)(dnf f-uimm5     "uimm5"               () 11 5)(dnf f-uimm8     "uimm8"               () 8 8)(dnf f-uimm16    "uimm16"              () 16 16)(dnf f-uimm24    "uimm24"              (ABS-ADDR RELOC) 8 24)(dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)(df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT    ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))    ((value pc) (add WI (mul WI value (const 4)) (and WI pc (const -4)))))(df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT    ((value pc) (sra WI (sub WI value pc) (const 2)))    ((value pc) (add WI (mul WI value (const 4)) pc)))(df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT    ((value pc) (sra WI (sub WI value pc) (const 2)))    ((value pc) (add WI (mul WI value (const 4)) pc))) (dnf f-op23      "op2.3"               ()  9 3)(dnf f-op3       "op3"                 () 14 2)(dnf f-acc       "acc"                 ()  8 1)(dnf f-accs      "accs"                () 12 2)(dnf f-accd      "accd"                ()  4 2)(dnf f-bits67    "bits67"              ()  6 2)(dnf f-bit4      "bit4"                ()  4 1)(dnf f-bit14     "bit14"               () 14 1) (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")  (attrs)  (start 15) (length 1)

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