/* AArch64 assembler/disassembler support.    Copyright (C) 2009-2026 Free Software Foundation, Inc.   Contributed by ARM Ltd.    This file is part of GNU Binutils.    This program is free software; you can redistribute it and/or modify   it under the terms of the GNU General Public License as published by   the Free Software Foundation; either version 3 of the license, or   (at your option) any later version.    This program is distributed in the hope that it will be useful,   but WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the   GNU General Public License for more details.    You should have received a copy of the GNU General Public License   along with this program; see the file COPYING3. If not,   see <http://www.gnu.org/licenses/>.  */ #ifndef OPCODE_AARCH64_H#define OPCODE_AARCH64_H #include "bfd.h"#include <stdint.h>#include <assert.h>#include <stdlib.h> #include "dis-asm.h" #ifdef __cplusplusextern "C" {#endif /* The offset for pc-relative addressing is currently defined to be 0.  */#define AARCH64_PCREL_OFFSET		0 typedef uint32_t aarch64_insn; /* An enum containing all known CPU features.  The values act as bit positions   into aarch64_feature_set.  */enum aarch64_feature_bit {  /* Architecture versions.  */  AARCH64_FEATURE_V8,  AARCH64_FEATURE_V8_1A,  AARCH64_FEATURE_V8_2A,  AARCH64_FEATURE_V8_3A,  AARCH64_FEATURE_V8_4A,  AARCH64_FEATURE_V8_5A,  AARCH64_FEATURE_V8_6A,  AARCH64_FEATURE_V8_7A,  AARCH64_FEATURE_V8_8A,  AARCH64_FEATURE_V8_9A,   AARCH64_FEATURE_V9A,  AARCH64_FEATURE_V9_1A,  AARCH64_FEATURE_V9_2A,  AARCH64_FEATURE_V9_3A,  AARCH64_FEATURE_V9_4A,  AARCH64_FEATURE_V9_5A,  AARCH64_FEATURE_V9_6A,  AARCH64_FEATURE_V9_7A,   /* Armv8-A processors only - this is unset for Armv8-R.  */  AARCH64_FEATURE_V8A,  /* Armv8-R processors.  */  AARCH64_FEATURE_V8R,   /* Bfloat16 insns.  */  AARCH64_FEATURE_BFLOAT16,  /* SVE2 instructions.  */  AARCH64_FEATURE_SVE2,  AARCH64_FEATURE_SVE2_AES,  AARCH64_FEATURE_SVE2_BITPERM,  AARCH64_FEATURE_SVE2_SM4,  AARCH64_FEATURE_SVE2_SHA3,  /* Scalable Matrix Extension.  */  AARCH64_FEATURE_SME,  /* Atomic 64-byte load/store.  */  AARCH64_FEATURE_LS64,  /* v8.3 Pointer Authentication.  */  AARCH64_FEATURE_PAUTH,  /* FP instructions.  */  AARCH64_FEATURE_FP,  /* SIMD instructions.  */  AARCH64_FEATURE_SIMD,  /* CRC instructions.  */  AARCH64_FEATURE_CRC,  /* LSE instructions.  */  AARCH64_FEATURE_LSE,  /* LSFE instructions.  */  AARCH64_FEATURE_LSFE,  /* PAN instructions.  */  AARCH64_FEATURE_PAN,  /* LOR instructions.  */  AARCH64_FEATURE_LOR,  /* v8.1 SIMD instructions.  */  AARCH64_FEATURE_RDMA,  /* v8.2 FP16 instructions.  */  AARCH64_FEATURE_F16,  /* RAS Extensions.  */  AARCH64_FEATURE_RAS,  /* Statistical Profiling.  */  AARCH64_FEATURE_PROFILE,  /* SVE instructions.  */  AARCH64_FEATURE_SVE,  /* RCPC instructions.  */  AARCH64_FEATURE_RCPC,  /* RCPC2 instructions.  */  AARCH64_FEATURE_RCPC2,  /* Complex # instructions.  */  AARCH64_FEATURE_COMPNUM,  /* JavaScript conversion instructions.  */  AARCH64_FEATURE_JSCVT,  /* Dot Product instructions.  */  AARCH64_FEATURE_DOTPROD,  /* SM3 & SM4 instructions.  */  AARCH64_FEATURE_SM4,  /* SHA2 instructions.  */  AARCH64_FEATURE_SHA2,  /* SHA3 instructions.  */  AARCH64_FEATURE_SHA3,  /* AES instructions.  */  AARCH64_FEATURE_AES,  /* v8.2 FP16FML ins.  */  AARCH64_FEATURE_F16_FML,  /* v8.5 Flag Manipulation version 2.  */  AARCH64_FEATURE_FLAGMANIP,  /* FRINT[32,64][Z,X] insns.  */  AARCH64_FEATURE_FRINTTS,  /* SB instruction.  */  AARCH64_FEATURE_SB,  /* Execution and Data Prediction Restriction instructions.  */  AARCH64_FEATURE_PREDRES,  /* DC CVADP.  */  AARCH64_FEATURE_CVADP,  /* Random Number instructions.  */  AARCH64_FEATURE_RNG,  /* SSBS mechanism enabled.  */  AARCH64_FEATURE_SSBS,  /* Compare and branch instructions.  */  AARCH64_FEATURE_CMPBR,  /* Memory Tagging Extension.  */  AARCH64_FEATURE_MEMTAG,  /* Outer Cacheable Cache Maintenance Operation.  */  AARCH64_FEATURE_OCCMO,  /* Transactional Memory Extension.  */  AARCH64_FEATURE_TME,  /* XS memory attribute.  */  AARCH64_FEATURE_XS,  /* WFx instructions with timeout.  */  AARCH64_FEATURE_WFXT,  /* Standardization of memory operations.  */  AARCH64_FEATURE_MOPS,  /* Hinted conditional branches.  */  AARCH64_FEATURE_HBC,  /* Matrix Multiply instructions.  */  AARCH64_FEATURE_I8MM,  AARCH64_FEATURE_F32MM,  AARCH64_FEATURE_F64MM,  /* v8.4 Flag Manipulation.  */  AARCH64_FEATURE_FLAGM,  /* SME F64F64.  */  AARCH64_FEATURE_SME_F64F64,  /* SME I16I64.  */  AARCH64_FEATURE_SME_I16I64,  /* Common Short Sequence Compression instructions.  */  AARCH64_FEATURE_CSSC,  /* Check Feature Status Extension.  */  AARCH64_FEATURE_CHK,  /* Guarded Control Stack.  */  AARCH64_FEATURE_GCS,  /* SME2.  */  AARCH64_FEATURE_SME2,  /* Translation Hardening Extension.  */  AARCH64_FEATURE_THE,  /* LSE128.  */  AARCH64_FEATURE_LSE128,  /* LSUI - Unprivileged Load Store.  */  AARCH64_FEATURE_LSUI,  /* ARMv8.9-A RAS Extensions.  */  AARCH64_FEATURE_RASv2,  /* Address Translate Stage 1.  */  AARCH64_FEATURE_ATS1A,  /* Speculation Prediction Restriction instructions.  */  AARCH64_FEATURE_PREDRES2,  /* Instrumentation Extension.  */  AARCH64_FEATURE_ITE,  /* 128-bit page table descriptor, system registers     and instructions.  */  AARCH64_FEATURE_D128,  /* SME2.1 instructions.  */  AARCH64_FEATURE_SME2p1,  /* SVE2.1 instructions.  */  AARCH64_FEATURE_SVE2p1,  /* SVE_F16F32MM instructions.  */  AARCH64_FEATURE_SVE_F16F32MM,  /* F8F32MM instructions.  */  AARCH64_FEATURE_F8F32MM,  /* F8F16MM instructions.  */  AARCH64_FEATURE_F8F16MM,  /* SVE_PMULL128 extension. */  AARCH64_FEATURE_SVE_AES,  /* SVE AES2 instructions.  */  AARCH64_FEATURE_SVE_AES2,  /* SSVE_AES extension. */  AARCH64_FEATURE_SSVE_AES,  /* SVE_BITPERM extension. */  AARCH64_FEATURE_SVE_BITPERM,  /* SSVE_BITPERM extension. */  AARCH64_FEATURE_SSVE_BITPERM,  /* RCPC3 instructions.  */  AARCH64_FEATURE_RCPC3,  /* Checked Pointer Arithmetic instructions. */  AARCH64_FEATURE_CPA,  /* FAMINMAX instructions.  */  AARCH64_FEATURE_FAMINMAX,  /* FP8 instructions.  */  AARCH64_FEATURE_FP8,  /* LUT instructions.  */  AARCH64_FEATURE_LUT,  /* Branch Record Buffer Extension */  AARCH64_FEATURE_BRBE,  /* SME LUTv2 instructions.  */  AARCH64_FEATURE_SME_LUTv2,  /* FP8FMA instructions.  */  AARCH64_FEATURE_FP8FMA,  /* FP8DOT4 instructions.  */  AARCH64_FEATURE_FP8DOT4,  /* FP8DOT2 instructions.  */  AARCH64_FEATURE_FP8DOT2,  /* SSVE FP8FMA instructions.  */  AARCH64_FEATURE_SSVE_FP8FMA,  /* SSVE FP8DOT4 instructions.  */  AARCH64_FEATURE_SSVE_FP8DOT4,  /* SSVE FP8DOT2 instructions.  */  AARCH64_FEATURE_SSVE_FP8DOT2,  /* SME F8F32 instructions.  */  AARCH64_FEATURE_SME_F8F32,  /* SME F8F16 instructions.  */  AARCH64_FEATURE_SME_F8F16,  /* Non-widening half-precision FP16 to FP16 arithmetic for SME2.  */  AARCH64_FEATURE_SME_F16F16,  /* FEAT_SVE_BFSCALE.  */  AARCH64_FEATURE_SVE_BFSCALE,  /* SVE Z-targeting non-widening BFloat16 instructions.  */  AARCH64_FEATURE_SVE_B16B16,  /* SME non-widening BFloat16 instructions.  */  AARCH64_FEATURE_SME_B16B16,  /* SVE2.2.  */  AARCH64_FEATURE_SVE2p2,  /* SME2.2.  */  AARCH64_FEATURE_SME2p2,  /* FPRCVT instructions.  */  AARCH64_FEATURE_FPRCVT,  /* Point of Physical Storage.  */  AARCH64_FEATURE_PoPS,  /* GICv5 (Generic Interrupt Controller) CPU Interface Extension.  */  AARCH64_FEATURE_GCIE,  /* SVE FEXPA instruction in streaming mode.  */  AARCH64_FEATURE_SSVE_FEXPA,  /* SME TMOP instructions.  */  AARCH64_FEATURE_SME_TMOP,  /* SME MOP4 instructions.  */  AARCH64_FEATURE_SME_MOP4,  /* LSCP instructions.  */  AARCH64_FEATURE_LSCP,  /* +mops-go */  AARCH64_FEATURE_MOPS_GO,  /* SVE2.3.  */  AARCH64_FEATURE_SVE2p3,  /* SME2.3.  */  AARCH64_FEATURE_SME2p3,  /* F16F32DOT instructions.  */  AARCH64_FEATURE_F16F32DOT,  /* F16F32MM instructions.  */  AARCH64_FEATURE_F16F32MM,  /* F16MM instructions.  */  AARCH64_FEATURE_F16MM,  /* SVE B16MM instructions.  */  AARCH64_FEATURE_SVE_B16MM,  /* POE2 instructions.  */  AARCH64_FEATURE_POE2,  /* TEV instructions.  */  AARCH64_FEATURE_TEV,  /* MPAMv2.  */  AARCH64_FEATURE_MPAMv2,  /* MTETC.  */  AARCH64_FEATURE_MTETC,  /* TLBI Domains.  */  AARCH64_FEATURE_TLBID,   /* Virtual features.  These are used to gate instructions that are enabled     by either of two (or more) sets of command line flags.  */  /* +sve2 or +ssve-aes */  AARCH64_FEATURE_SVE2_SSVE_AES,  /* +sve or +ssve-fexpa */  AARCH64_FEATURE_SVE_SSVE_FEXPA,  /* +fp8fma+sve or +ssve-fp8fma  */  AARCH64_FEATURE_FP8FMA_SVE,  /* +fp8dot4+sve or +ssve-fp8dot4  */  AARCH64_FEATURE_FP8DOT4_SVE,  /* +fp8dot2+sve or +ssve-fp8dot2  */  AARCH64_FEATURE_FP8DOT2_SVE,  /* +sme-f16f16 or +sme-f8f16  */  AARCH64_FEATURE_SME_F16F16_F8F16,  /* +sve or +sme2p2 */  AARCH64_FEATURE_SVE_SME2p2,  /* +sve2 or +sme2 */  AARCH64_FEATURE_SVE2_SME2,  /* +sve2p1 or +sme */  AARCH64_FEATURE_SVE2p1_SME,  /* +sve2p1 or +sme2 */  AARCH64_FEATURE_SVE2p1_SME2,  /* +sve2p1 or +sme2p1 */  AARCH64_FEATURE_SVE2p1_SME2p1,  /* +sve2p2 or +sme2p2 */  AARCH64_FEATURE_SVE2p2_SME2p2,  /* +sve2p3 or +sme2p3 */  AARCH64_FEATURE_SVE2p3_SME2p3,  /* +d128 or +tlbid */  AARCH64_FEATURE_D128_TLBID,  AARCH64_NUM_FEATURES}; typedef uint64_t aarch64_feature_word;#define AARCH64_BITS_PER_FEATURE_WORD 64 #define AA64_REPLICATE(SEP, BODY, ...)	\  BODY (0, __VA_ARGS__) SEP		\  BODY (1, __VA_ARGS__) SEP		\  BODY (2, __VA_ARGS__) /* Some useful SEP operators for use with replication.  */#define REP_COMMA ,#define REP_SEMICOLON ;#define REP_OR_OR ||#define REP_AND_AND &&#define REP_PLUS + /* Not currently needed, but if an empty SEP is required define:  #define REP_NO_SEP  Then use REP_NO_SEP in the SEP field.  */ /* Used to generate one instance of VAL for each value of ELT (ELT is   not otherwise used).  */#define AA64_REPVAL(ELT, VAL) VAL /* static_assert requires C11 (or C++11) or later.  Support older   versions by disabling this check since compilers without this are   pretty uncommon these days.  */#if ((defined __STDC_VERSION__ && __STDC_VERSION__ >= 201112L)	\     || (defined __cplusplus && __cplusplus >= 201103L))static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL,				AARCH64_BITS_PER_FEATURE_WORD))	       >= AARCH64_NUM_FEATURES,	       "Insufficient repetitions in AA64_REPLICATE()");#endif /* These macros take an initial argument X that gives the index into   an aarch64_feature_set.  The macros then return the bitmask for   that array index.  */ /* A mask in which feature bit BIT is set and all other bits are clear.  */#define AARCH64_UINT64_BIT(X, BIT)			\  ((X) == (BIT) / AARCH64_BITS_PER_FEATURE_WORD		\   ? 1ULL << (BIT) % AARCH64_BITS_PER_FEATURE_WORD	\   : 0) /* A mask that includes only AARCH64_FEATURE_<NAME>.  */#define AARCH64_FEATBIT(X, NAME) \  AARCH64_UINT64_BIT (X, AARCH64_FEATURE_##NAME) /* A mask of the features that are enabled by each architecture version,   excluding those that are inherited from other architecture versions.  */#define AARCH64_ARCH_V8A_FEATURES(X)	(AARCH64_FEATBIT (X, V8A)	\					 | AARCH64_FEATBIT (X, FP)	\					 | AARCH64_FEATBIT (X, RAS)	\					 | AARCH64_FEATBIT (X, SIMD)	\					 | AARCH64_FEATBIT (X, CHK))#define AARCH64_ARCH_V8_1A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_1A)	\					 | AARCH64_FEATBIT (X, CRC)	\					 | AARCH64_FEATBIT (X, LSE)	\					 | AARCH64_FEATBIT (X, PAN)	\					 | AARCH64_FEATBIT (X, LOR)	\					 | AARCH64_FEATBIT (X, RDMA))#define AARCH64_ARCH_V8_2A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_2A))#define AARCH64_ARCH_V8_3A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_3A)	\					 | AARCH64_FEATBIT (X, PAUTH)	\					 | AARCH64_FEATBIT (X, RCPC)	\					 | AARCH64_FEATBIT (X, COMPNUM) \					 | AARCH64_FEATBIT (X, JSCVT))#define AARCH64_ARCH_V8_4A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_4A)	\					 | AARCH64_FEATBIT (X, RCPC2)	\					 | AARCH64_FEATBIT (X, DOTPROD)	\					 | AARCH64_FEATBIT (X, FLAGM)	\					 | AARCH64_FEATBIT (X, F16_FML))#define AARCH64_ARCH_V8_5A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_5A)	\					 | AARCH64_FEATBIT (X, FLAGMANIP) \					 | AARCH64_FEATBIT (X, FRINTTS)	\					 | AARCH64_FEATBIT (X, SB)	\					 | AARCH64_FEATBIT (X, PREDRES)	\					 | AARCH64_FEATBIT (X, CVADP)	\					 | AARCH64_FEATBIT (X, SSBS))#define AARCH64_ARCH_V8_6A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_6A)	\					 | AARCH64_FEATBIT (X, BFLOAT16) \					 | AARCH64_FEATBIT (X, I8MM))#define AARCH64_ARCH_V8_7A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_7A)	\					 | AARCH64_FEATBIT (X, XS)      \					 | AARCH64_FEATBIT (X, WFXT)    \					 | AARCH64_FEATBIT (X, LS64))#define AARCH64_ARCH_V8_8A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_8A)	\					 | AARCH64_FEATBIT (X, MOPS)	\					 | AARCH64_FEATBIT (X, HBC))#define AARCH64_ARCH_V8_9A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_9A)	\					 | AARCH64_FEATBIT (X, CSSC) \					 | AARCH64_FEATBIT (X, RASv2)	\					 | AARCH64_FEATBIT (X, ATS1A)	\					 | AARCH64_FEATBIT (X, PREDRES2) \					) #define AARCH64_ARCH_V9A_FEATURES(X)	(AARCH64_FEATBIT (X, V9A)	\					 | AARCH64_FEATBIT (X, F16)	\					 | AARCH64_FEATBIT (X, SVE)	\					 | AARCH64_FEATBIT (X, SVE2))#define AARCH64_ARCH_V9_1A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_1A)	\					 | AARCH64_ARCH_V8_6A_FEATURES (X))#define AARCH64_ARCH_V9_2A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_2A)	\					 | AARCH64_ARCH_V8_7A_FEATURES (X))#define AARCH64_ARCH_V9_3A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_3A)	\					 | AARCH64_ARCH_V8_8A_FEATURES (X))#define AARCH64_ARCH_V9_4A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_4A)	\					 | AARCH64_ARCH_V8_9A_FEATURES (X) \					 | AARCH64_FEATBIT (X, SVE2p1))#define AARCH64_ARCH_V9_5A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_5A)	\					 | AARCH64_FEATBIT (X, CPA)	\					 | AARCH64_FEATBIT (X, LUT)	\					 | AARCH64_FEATBIT (X, FAMINMAX)\					)#define AARCH64_ARCH_V9_6A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_6A)	\					 | AARCH64_FEATBIT (X, CMPBR)	\					 | AARCH64_FEATBIT (X, LSUI)	\					 | AARCH64_FEATBIT (X, OCCMO))#define AARCH64_ARCH_V9_7A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_7A)	\					 | AARCH64_FEATBIT (X, F16F32DOT) \					 | AARCH64_FEATBIT (X, SVE2p2)	\					 | AARCH64_FEATBIT (X, SVE2p3)) /* Architectures are the sum of the base and extensions.  */#define AARCH64_ARCH_V8A(X)	(AARCH64_FEATBIT (X, V8) \				 | AARCH64_ARCH_V8A_FEATURES (X))#define AARCH64_ARCH_V8_1A(X)	(AARCH64_ARCH_V8A (X) \				 | AARCH64_ARCH_V8_1A_FEATURES (X))#define AARCH64_ARCH_V8_2A(X)	(AARCH64_ARCH_V8_1A (X)	\				 | AARCH64_ARCH_V8_2A_FEATURES (X))#define AARCH64_ARCH_V8_3A(X)	(AARCH64_ARCH_V8_2A (X)	\				 | AARCH64_ARCH_V8_3A_FEATURES (X))#define AARCH64_ARCH_V8_4A(X)	(AARCH64_ARCH_V8_3A (X)	\				 | AARCH64_ARCH_V8_4A_FEATURES (X))#define AARCH64_ARCH_V8_5A(X)	(AARCH64_ARCH_V8_4A (X)	\				 | AARCH64_ARCH_V8_5A_FEATURES (X))#define AARCH64_ARCH_V8_6A(X)	(AARCH64_ARCH_V8_5A (X)	\				 | AARCH64_ARCH_V8_6A_FEATURES (X))#define AARCH64_ARCH_V8_7A(X)	(AARCH64_ARCH_V8_6A (X)	\				 | AARCH64_ARCH_V8_7A_FEATURES (X))#define AARCH64_ARCH_V8_8A(X)	(AARCH64_ARCH_V8_7A (X)	\				 | AARCH64_ARCH_V8_8A_FEATURES (X))#define AARCH64_ARCH_V8_9A(X)	(AARCH64_ARCH_V8_8A (X)	\				 | AARCH64_ARCH_V8_9A_FEATURES (X))#define AARCH64_ARCH_V8R(X)	((AARCH64_ARCH_V8_4A (X)	\				  | AARCH64_FEATBIT (X, V8R))	\				 & ~AARCH64_FEATBIT (X, V8A)	\				 & ~AARCH64_FEATBIT (X, LOR)) #define AARCH64_ARCH_V9A(X)	(AARCH64_ARCH_V8_5A (X) \				 | AARCH64_ARCH_V9A_FEATURES (X))#define AARCH64_ARCH_V9_1A(X)	(AARCH64_ARCH_V9A (X) \				 | AARCH64_ARCH_V9_1A_FEATURES (X))#define AARCH64_ARCH_V9_2A(X)	(AARCH64_ARCH_V9_1A (X) \				 | AARCH64_ARCH_V9_2A_FEATURES (X))#define AARCH64_ARCH_V9_3A(X)	(AARCH64_ARCH_V9_2A (X) \				 | AARCH64_ARCH_V9_3A_FEATURES (X))#define AARCH64_ARCH_V9_4A(X)	(AARCH64_ARCH_V9_3A (X) \				 | AARCH64_ARCH_V9_4A_FEATURES (X))#define AARCH64_ARCH_V9_5A(X)	(AARCH64_ARCH_V9_4A (X) \				 | AARCH64_ARCH_V9_5A_FEATURES (X))#define AARCH64_ARCH_V9_6A(X)	(AARCH64_ARCH_V9_5A (X) \				 | AARCH64_ARCH_V9_6A_FEATURES (X))#define AARCH64_ARCH_V9_7A(X)	(AARCH64_ARCH_V9_6A (X) \				 | AARCH64_ARCH_V9_7A_FEATURES (X)) #define AARCH64_ARCH_NONE(X)	0 /* CPU-specific features.  */typedef struct {  aarch64_feature_word flags[AA64_REPLICATE (REP_PLUS, AA64_REPVAL, 1)];} aarch64_feature_set; #define AARCH64_CPU_HAS_FEATURE_BODY(ELT, CPU, FEAT)	\

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