/* mips.h.  Mips opcode list for GDB, the GNU debugger.   Copyright (C) 1993-2026 Free Software Foundation, Inc.   Contributed by Ralph Campbell and OSF   Commented and modified by Ian Lance Taylor, Cygnus Support    This file is part of GDB, GAS, and the GNU binutils.    GDB, GAS, and the GNU binutils are free software; you can redistribute   them and/or modify them under the terms of the GNU General Public   License as published by the Free Software Foundation; either version 3,   or (at your option) any later version.    GDB, GAS, and the GNU binutils are distributed in the hope that they   will be useful, but WITHOUT ANY WARRANTY; without even the implied   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See   the GNU General Public License for more details.    You should have received a copy of the GNU General Public License   along with this file; see the file COPYING3.  If not, write to the Free   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,   MA 02110-1301, USA.  */ #ifndef _MIPS_H_#define _MIPS_H_ #include "bfd.h" #ifdef __cplusplusextern "C" {#endif /* These are bit masks and shift counts to use to access the various   fields of an instruction.  To retrieve the X field of an   instruction, use the expression	(i >> OP_SH_X) & OP_MASK_X   To set the same field (to j), use	i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)    Make sure you use fields that are appropriate for the instruction,   of course.    The 'i' format uses OP, RS, RT and IMMEDIATE.    The 'j' format uses OP and TARGET.    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.    The 'b' format uses OP, RS, RT and DELTA.    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the   breakpoint instruction are not defined; Kane says the breakpoint   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers   only use ten bits).  An optional two-operand form of break/sdbbp   allows the lower ten bits to be set too, and MIPS32 and later   architectures allow 20 bits to be set with a single operand for   the sdbbp instruction (using CODE20).    The syscall instruction uses CODE20.    The general coprocessor instructions use COPZ.  */ #define OP_MASK_OP		0x3f#define OP_SH_OP		26#define OP_MASK_RS		0x1f#define OP_SH_RS		21#define OP_MASK_BCC		0x7#define OP_SH_BCC		18#define OP_MASK_RT		0x1f#define OP_SH_RT		16#define OP_MASK_RD		0x1f#define OP_SH_RD		11#define OP_MASK_IMMEDIATE	0xffff#define OP_SH_IMMEDIATE		0 /* Values in the 'VSEL' field.  */#define MDMX_FMTSEL_IMM_QH	0x1d#define MDMX_FMTSEL_IMM_OB	0x1e#define MDMX_FMTSEL_VEC_QH	0x15#define MDMX_FMTSEL_VEC_OB	0x16 /* Enumerates the various types of MIPS operand.  */enum mips_operand_type {  /* Described by mips_int_operand.  */  OP_INT,   /* Described by mips_mapped_int_operand.  */  OP_MAPPED_INT,   /* Described by mips_msb_operand.  */  OP_MSB,   /* Described by mips_reg_operand.  */  OP_REG,   /* Like OP_REG, but can be omitted if the register is the same as the     previous operand.  */  OP_OPTIONAL_REG,   /* Described by mips_reg_pair_operand.  */  OP_REG_PAIR,   /* Described by mips_pcrel_operand.  */  OP_PCREL,   /* A performance register.  The field is 5 bits in size, but the supported     values are much more restricted.  */  OP_PERF_REG,   /* The final operand in a microMIPS ADDIUSP instruction.  It mostly acts     as a normal 9-bit signed offset that is multiplied by four, but there     are four special cases:      -2 * 4 => -258 * 4     -1 * 4 => -257 * 4      0 * 4 =>  256 * 4      1 * 4 =>  257 * 4.  */  OP_ADDIUSP_INT,   /* The target of a (D)CLO or (D)CLZ instruction.  The operand spans two     5-bit register fields, both of which must be set to the destination     register.  */  OP_CLO_CLZ_DEST,   /* A register list for a microMIPS LWM or SWM instruction.  The operand     size determines whether the 16-bit or 32-bit encoding is required.  */  OP_LWM_SWM_LIST,   /* The register list for an emulated MIPS16 ENTRY or EXIT instruction.  */  OP_ENTRY_EXIT_LIST,   /* The register list and frame size for a MIPS16 SAVE or RESTORE     instruction.  */  OP_SAVE_RESTORE_LIST,   /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:      V      Meaning     -----  -------     0EEE0  8 copies of $vN[E], OB format     0EE01  4 copies of $vN[E], QH format     10110  all 8 elements of $vN, OB format     10101  all 4 elements of $vN, QH format     11110  8 copies of immediate N, OB format     11101  4 copies of immediate N, QH format.  */  OP_MDMX_IMM_REG,   /* A register operand that must match the destination register.  */  OP_REPEAT_DEST_REG,   /* A register operand that must match the previous register.  */  OP_REPEAT_PREV_REG,   /* $pc, which has no encoding in the architectural instruction.  */  OP_PC,   /* $28, which has no encoding in the MIPS16e architectural instruction.  */  OP_REG28,   /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines     which.  */  OP_VU0_SUFFIX,   /* Like OP_VU0_SUFFIX, but used when the operand's value has already     been set.  Any suffix used here must match the previous value.  */  OP_VU0_MATCH_SUFFIX,   /* An index selected by an integer, e.g. [1].  */  OP_IMM_INDEX,   /* An index selected by a register, e.g. [$2].  */  OP_REG_INDEX,   /* The operand spans two 5-bit register fields, both of which must be set to     the source register.  */  OP_SAME_RS_RT,   /* Described by mips_prev_operand.  */  OP_CHECK_PREV,   /* A register operand that must not be zero.  */  OP_NON_ZERO_REG}; /* Enumerates the types of MIPS register.  */enum mips_reg_operand_type {  /* General registers $0-$31.  Software names like $at can also be used.  */  OP_REG_GP,   /* Floating-point registers $f0-$f31.  */  OP_REG_FP,   /* Coprocessor condition code registers $cc0-$cc7.  FPU condition codes     can also be written $fcc0-$fcc7.  */  OP_REG_CCC,   /* FPRs used in a vector capacity.  They can be written $f0-$f31     or $v0-$v31, although the latter form is not used for the VR5400     vector instructions.  */  OP_REG_VEC,   /* DSP accumulator registers $ac0-$ac3.  */  OP_REG_ACC,   /* Coprocessor registers $0-$31.  Mnemonic names like c0_cause can     also be used in some contexts.  */  OP_REG_COPRO,   /* Coprocessor control registers $0-$31.  Mnemonic names like c1_fcsr can     also be used in some contexts.  */  OP_REG_CONTROL,   /* Hardware registers $0-$31.  Mnemonic names like hwr_cpunum can     also be used in some contexts.  */  OP_REG_HW,   /* Floating-point registers $vf0-$vf31.  */  OP_REG_VF,   /* Integer registers $vi0-$vi31.  */  OP_REG_VI,   /* R5900 VU0 registers $I, $Q, $R and $ACC.  */  OP_REG_R5900_I,  OP_REG_R5900_Q,  OP_REG_R5900_R,  OP_REG_R5900_ACC,   /* MSA registers $w0-$w31.  */  OP_REG_MSA,   /* MSA control registers $0-$31.  */  OP_REG_MSA_CTRL}; /* Base class for all operands.  */struct mips_operand{  /* The type of the operand.  */  enum mips_operand_type type;   /* The operand occupies SIZE bits of the instruction, starting at LSB.  */  unsigned short size;  unsigned short lsb;}; /* Describes an integer operand with a regular encoding pattern.  */struct mips_int_operand{  struct mips_operand root;   /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.     The cyclically previous field value encodes 1 << SHIFT less than that,     and so on.  E.g.      - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,       but 15 encodes -1.      - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is       shifted left two places.      - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except       that 0 encodes 8.      - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3.  */  unsigned int max_val;  int bias;  unsigned int shift;   /* True if the operand should be printed as hex rather than decimal.  */  bool print_hex;}; /* Uses a lookup table to describe a small integer operand.  */struct mips_mapped_int_operand{  struct mips_operand root;   /* Maps each encoding value to the integer that it represents.  */  const int *int_map;   /* True if the operand should be printed as hex rather than decimal.  */  bool print_hex;}; /* An operand that encodes the most significant bit position of a bitfield.   Given a bitfield that spans bits [MSB, LSB], some operands of this type   encode MSB directly while others encode MSB - LSB.  Each operand of this   type is preceded by an integer operand that specifies LSB.    The assembly form varies between instructions.  For some instructions,   such as EXT, the operand is written as the bitfield size.  For others,   such as EXTS, it is written in raw MSB - LSB form.  */struct mips_msb_operand{  struct mips_operand root;   /* The assembly-level operand encoded by a field value of 0.  */  int bias;   /* True if the operand encodes MSB directly, false if it encodes     MSB - LSB.  */  bool add_lsb;   /* The maximum value of MSB + 1.  */  unsigned int opsize;}; /* Describes a single register operand.  */struct mips_reg_operand{  struct mips_operand root;   /* The type of register.  */  enum mips_reg_operand_type reg_type;   /* If nonnull, REG_MAP[N] gives the register associated with encoding N,     otherwise the encoding is the same as the register number.  */  const unsigned char *reg_map;}; /* Describes an operand that which must match a condition based on the   previous operand.  */struct mips_check_prev_operand{  struct mips_operand root;   bool greater_than_ok;  bool less_than_ok;  bool equal_ok;  bool zero_ok;}; /* Describes an operand that encodes a pair of registers.  */struct mips_reg_pair_operand{  struct mips_operand root;   /* The type of register.  */  enum mips_reg_operand_type reg_type;   /* Encoding N represents REG1_MAP[N], REG2_MAP[N].  */  unsigned char *reg1_map;  unsigned char *reg2_map;}; /* Describes an operand that is calculated relative to a base PC.   The base PC is usually the address of the following instruction,   but the rules for MIPS16 instructions like ADDIUPC are more complicated.  */struct mips_pcrel_operand{  /* Encodes the offset.  */  struct mips_int_operand root;   /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',     which is then added to the offset encoded by ROOT.  */  unsigned int align_log2 : 8;   /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then     reinstated.  This is true for jumps and branches and false for     PC-relative data instructions.  */  unsigned int include_isa_bit : 1;   /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.     This is true for JALX and false otherwise.  */  unsigned int flip_isa_bit : 1;}; /* Return true if the assembly syntax allows OPERAND to be omitted.  */ static inline boolmips_optional_operand_p (const struct mips_operand *operand){  return (operand->type == OP_OPTIONAL_REG	  || operand->type == OP_REPEAT_PREV_REG);} /* Return a version of INSN in which the field specified by OPERAND   has value UVAL.  */ static inline unsigned intmips_insert_operand (const struct mips_operand *operand, unsigned int insn,		     unsigned int uval){  unsigned int mask;   mask = (1 << operand->size) - 1;  insn &= ~(mask << operand->lsb);  insn |= (uval & mask) << operand->lsb;  return insn;} /* Extract OPERAND from instruction INSN.  */ static inline unsigned intmips_extract_operand (const struct mips_operand *operand, unsigned int insn){  return (insn >> operand->lsb) & ((1 << operand->size) - 1);} /* UVAL is the value encoded by OPERAND.  Return it in signed form.  */ static inline intmips_signed_operand (const struct mips_operand *operand, unsigned int uval){  unsigned int sign_bit, mask;   mask = (1 << operand->size) - 1;  sign_bit = 1 << (operand->size - 1);  return ((uval + sign_bit) & mask) - sign_bit;} /* Return the integer that OPERAND encodes as UVAL.  */ static inline intmips_decode_int_operand (const struct mips_int_operand *operand,			 unsigned int uval){  uval |= (operand->max_val - uval) & -(1 << operand->root.size);  uval += operand->bias;  uval <<= operand->shift;  return uval;} /* Return the maximum value that can be encoded by OPERAND.  */ static inline intmips_int_operand_max (const struct mips_int_operand *operand){  return (operand->max_val + operand->bias) << operand->shift;} /* Return the minimum value that can be encoded by OPERAND.  */ static inline intmips_int_operand_min (const struct mips_int_operand *operand){  unsigned int mask;   mask = (1 << operand->root.size) - 1;  return mips_int_operand_max (operand) - (mask << operand->shift);} /* Return the register that OPERAND encodes as UVAL.  */ static inline intmips_decode_reg_operand (const struct mips_reg_operand *operand,			 unsigned int uval){  if (operand->reg_map)    uval = operand->reg_map[uval];  return uval;} /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.   Return the address that it encodes.  */ static inline bfd_vmamips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,			   bfd_vma base_pc, unsigned int uval){  bfd_vma addr;   addr = base_pc & -(1 << operand->align_log2);  addr += mips_decode_int_operand (&operand->root, uval);  if (operand->include_isa_bit)    addr |= base_pc & 1;  if (operand->flip_isa_bit)    addr ^= 1;  return addr;} /* This structure holds information for a particular instruction.  */ struct mips_opcode{  /* The name of the instruction.  */  const char *name;  /* A string describing the arguments for this instruction.  */  const char *args;  /* The basic opcode for the instruction.  When assembling, this     opcode is modified by the arguments to produce the actual opcode     that is used.  If pinfo is INSN_MACRO, then this is 0.  */  unsigned long match;  /* If pinfo is not INSN_MACRO, then this is a bit mask for the     relevant portions of the opcode when disassembling.  If the     actual opcode anded with the match field equals the opcode field,     then we have found the correct instruction.  If pinfo is     INSN_MACRO, then this field is the macro identifier.  */  unsigned long mask;  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection     of bits describing the instruction, notably any relevant hazard     information.  */  unsigned long pinfo;  /* A collection of additional bits describing the instruction. */  unsigned long pinfo2;  /* A collection of bits describing the instruction sets of which this

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