/* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.   Copyright (C) 2011-2026 Free Software Foundation, Inc.   Contributed by Andrew Waterman    This file is part of GDB, GAS, and the GNU binutils.    GDB, GAS, and the GNU binutils are free software; you can redistribute   them and/or modify them under the terms of the GNU General Public   License as published by the Free Software Foundation; either version   3, or (at your option) any later version.    GDB, GAS, and the GNU binutils are distributed in the hope that they   will be useful, but WITHOUT ANY WARRANTY; without even the implied   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See   the GNU General Public License for more details.    You should have received a copy of the GNU General Public License   along with this program; see the file COPYING3. If not,   see <http://www.gnu.org/licenses/>.  */ #ifndef _RISCV_H_#define _RISCV_H_ #include "riscv-opc.h"#include <stdlib.h>#include <stdint.h> typedef uint64_t insn_t; static inline unsigned int riscv_insn_length (insn_t insn){  if ((insn & 0x3) != 0x3) /* RVC instructions.  */    return 2;  if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */    return 4;  if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */    return 6;  if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */    return 8;  /* 80- ... 176-bit instructions.  */  if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000)    return 10 + ((insn >> 11) & 0xe);  /* Maximum value returned by this function.  */#define RISCV_MAX_INSN_LEN 22  /* Longer instructions not supported at the moment.  */  return 2;} #define RVC_JUMP_BITS 11#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) #define RVC_BRANCH_BITS 8#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1)) #define EXTRACT_ITYPE_IMM(x) \  (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))#define EXTRACT_STYPE_IMM(x) \  (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))#define EXTRACT_BTYPE_IMM(x) \  ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))#define EXTRACT_UTYPE_IMM(x) \  ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))#define EXTRACT_JTYPE_IMM(x) \  ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))#define EXTRACT_CITYPE_IMM(x) \  (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))#define EXTRACT_CITYPE_LUI_IMM(x) \  (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)#define EXTRACT_CITYPE_ADDI16SP_IMM(x) \  ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))#define EXTRACT_CITYPE_LWSP_IMM(x) \  ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))#define EXTRACT_CITYPE_LDSP_IMM(x) \  ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))#define EXTRACT_CSSTYPE_IMM(x) \  (RV_X(x, 7, 6) << 0)#define EXTRACT_CSSTYPE_SWSP_IMM(x) \  ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))#define EXTRACT_CSSTYPE_SDSP_IMM(x) \  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))#define EXTRACT_CIWTYPE_IMM(x) \  (RV_X(x, 5, 8))#define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))#define EXTRACT_CLTYPE_IMM(x) \  ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))#define EXTRACT_CLTYPE_LW_IMM(x) \  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))#define EXTRACT_CLTYPE_LD_IMM(x) \  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))#define EXTRACT_CBTYPE_IMM(x) \  ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))#define EXTRACT_CJTYPE_IMM(x) \  ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))#define EXTRACT_RVV_VI_IMM(x) \  (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))#define EXTRACT_RVV_VI_UIMM(x) \  (RV_X(x, 15, 5))#define EXTRACT_RVV_VI_UIMM6(x) \  (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))#define EXTRACT_RVV_OFFSET(x) \  (RV_X(x, 29, 3))#define EXTRACT_RVV_VB_IMM(x) \  (RV_X(x, 20, 10))#define EXTRACT_RVV_VC_IMM(x) \  (RV_X(x, 20, 11))#define EXTRACT_ZCB_BYTE_UIMM(x) \  (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))#define EXTRACT_ZCB_HALFWORD_UIMM(x) \  (RV_X(x, 5, 1) << 1)#define EXTRACT_ZCMP_SPIMM(x) \  (RV_X(x, 2, 2) << 4)#define EXTRACT_ZCMT_INDEX(x) \  (RV_X(x, 2, 8))/* Vendor-specific (CORE-V) extract macros.  */#define EXTRACT_CV_IS2_UIMM5(x) \  (RV_X(x, 20, 5))#define EXTRACT_CV_IS3_UIMM5(x) \  (RV_X(x, 25, 5))#define EXTRACT_CV_BI_IMM5(x) \  (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))#define EXTRACT_CV_BITMANIP_UIMM5(x) \  (RV_X(x, 25, 5))#define EXTRACT_CV_BITMANIP_UIMM2(x) \  (RV_X(x, 25, 2))#define EXTRACT_CV_SIMD_IMM6(x) \  ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5))#define EXTRACT_CV_SIMD_UIMM6(x) \  ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1))/* Vendor-specific (MIPS) extract macros.  */#define EXTRACT_MIPS_LWP_IMM(x) \  (RV_X(x, 22, 5) << 2)#define EXTRACT_MIPS_LDP_IMM(x) \  (RV_X(x, 23, 4) << 3)#define EXTRACT_MIPS_SWP_IMM(x) \  ((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2))#define EXTRACT_MIPS_SDP_IMM(x) \  ((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3)) #define ENCODE_ITYPE_IMM(x) \  (RV_X(x, 0, 12) << 20)#define ENCODE_STYPE_IMM(x) \  ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))#define ENCODE_BTYPE_IMM(x) \  ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))#define ENCODE_UTYPE_IMM(x) \  (RV_X(x, 12, 20) << 12)#define ENCODE_JTYPE_IMM(x) \  ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))#define ENCODE_CITYPE_IMM(x) \  ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))#define ENCODE_CITYPE_LUI_IMM(x) \  ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)#define ENCODE_CITYPE_ADDI16SP_IMM(x) \  ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))#define ENCODE_CITYPE_LWSP_IMM(x) \  ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))#define ENCODE_CITYPE_LDSP_IMM(x) \  ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))#define ENCODE_CSSTYPE_IMM(x) \  (RV_X(x, 0, 6) << 7)#define ENCODE_CSSTYPE_SWSP_IMM(x) \  ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))#define ENCODE_CSSTYPE_SDSP_IMM(x) \  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))#define ENCODE_CIWTYPE_IMM(x) \  (RV_X(x, 0, 8) << 5)#define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))#define ENCODE_CLTYPE_IMM(x) \  ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))#define ENCODE_CLTYPE_LW_IMM(x) \  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))#define ENCODE_CLTYPE_LD_IMM(x) \  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))#define ENCODE_CBTYPE_IMM(x) \  ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))#define ENCODE_CJTYPE_IMM(x) \  ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))#define ENCODE_RVV_VB_IMM(x) \  (RV_X(x, 0, 10) << 20)#define ENCODE_RVV_VC_IMM(x) \  (RV_X(x, 0, 11) << 20)#define ENCODE_RVV_VI_UIMM6(x) \  (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)#define ENCODE_ZCB_BYTE_UIMM(x) \  ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))#define ENCODE_ZCB_HALFWORD_UIMM(x) \  (RV_X(x, 1, 1) << 5)#define ENCODE_ZCMP_SPIMM(x) \  (RV_X(x, 4, 2) << 2)#define ENCODE_ZCMT_INDEX(x) \  (RV_X(x, 0, 8) << 2)/* Vendor-specific (CORE-V) encode macros.  */#define ENCODE_CV_IS2_UIMM5(x) \  (RV_X(x, 0, 5) << 20)#define ENCODE_CV_IS3_UIMM5(x) \  (RV_X(x, 0, 5) << 25)#define ENCODE_CV_BITMANIP_UIMM5(x) \  (RV_X(x, 0, 5) << 25)#define ENCODE_CV_BITMANIP_UIMM2(x) \  (RV_X(x, 0, 2) << 25)#define ENCODE_CV_SIMD_IMM6(x) \  ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))#define ENCODE_CV_SIMD_UIMM6(x) \  ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))/* Vendor-specific (MIPS) encode macros.  */#define ENCODE_MIPS_LWP_IMM(x) \  (RV_X(x, 2, 5) << 22)#define ENCODE_MIPS_LDP_IMM(x) \  (RV_X(x, 3, 4) << 23)#define ENCODE_MIPS_SWP_IMM(x) \  ((RV_X(x, 5, 2) << 25) | (RV_X(x, 2, 3) << 9))#define ENCODE_MIPS_SDP_IMM(x) \  ((RV_X(x, 5, 2) << 25) | (RV_X(x, 3, 2) << 10)) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))#define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))#define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))#define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))#define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \				 && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))#define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \				      && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))#define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))#define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))#define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))#define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))#define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))#define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))#define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))#define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))#define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))#define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))#define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))#define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))#define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))#define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))#define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x)) #define RISCV_RTYPE(insn, rd, rs1, rs2) \  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))#define RISCV_ITYPE(insn, rd, rs1, imm) \  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))#define RISCV_STYPE(insn, rs1, rs2, imm) \  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))#define RISCV_BTYPE(insn, rs1, rs2, target) \  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))#define RISCV_UTYPE(insn, rd, bigimm) \  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))#define RISCV_JTYPE(insn, rd, target) \  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target)) #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)#define RVC_NOP MATCH_C_ADDI #define RISCV_CONST_HIGH_PART(VALUE) \  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS#define RISCV_JUMP_ALIGN_BITS 1#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) #define RISCV_IMM_BITS 12#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)#define RISCV_RVC_IMM_REACH (1LL << 6)#define RISCV_BRANCH_BITS RISCV_IMM_BITS#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) /* RV fields.  */ #define OP_MASK_OP		0x7f#define OP_SH_OP		0#define OP_MASK_RS2		0x1f#define OP_SH_RS2		20#define OP_MASK_RS1		0x1f#define OP_SH_RS1		15#define OP_MASK_RS3		0x1fU#define OP_SH_RS3		27#define OP_MASK_RD		0x1f#define OP_SH_RD		7#define OP_MASK_SHAMT		0x3f#define OP_SH_SHAMT		20#define OP_MASK_SHAMTW		0x1f#define OP_SH_SHAMTW		20#define OP_MASK_RM		0x7#define OP_SH_RM		12#define OP_MASK_PRED		0xf#define OP_SH_PRED		24#define OP_MASK_SUCC		0xf#define OP_SH_SUCC		20#define OP_MASK_AQ		0x1#define OP_SH_AQ		26#define OP_MASK_RL		0x1#define OP_SH_RL		25 #define OP_MASK_CSR		0xfffU#define OP_SH_CSR		20 #define OP_MASK_FUNCT3		0x7#define OP_SH_FUNCT3		12#define OP_MASK_FUNCT7		0x7fU#define OP_SH_FUNCT7		25#define OP_MASK_FUNCT2		0x3#define OP_SH_FUNCT2		25 /* RVC fields.  */ #define OP_MASK_OP2		0x3#define OP_SH_OP2		0 #define OP_MASK_CRS2		0x1f#define OP_SH_CRS2		2#define OP_MASK_CRS1S		0x7#define OP_SH_CRS1S		7#define OP_MASK_CRS2S		0x7#define OP_SH_CRS2S		2 #define OP_MASK_CFUNCT6		0x3f#define OP_SH_CFUNCT6		10#define OP_MASK_CFUNCT4		0xf#define OP_SH_CFUNCT4		12#define OP_MASK_CFUNCT3		0x7#define OP_SH_CFUNCT3		13#define OP_MASK_CFUNCT2		0x3#define OP_SH_CFUNCT2		5 /* Scalar crypto fields. */ #define OP_SH_BS        30#define OP_MASK_BS      3#define OP_SH_RNUM      20#define OP_MASK_RNUM    0xf /* RVV fields.  */ #define OP_MASK_VD		0x1f#define OP_SH_VD		7#define OP_MASK_VS1		0x1f#define OP_SH_VS1		15#define OP_MASK_VS2		0x1f#define OP_SH_VS2		20#define OP_MASK_VIMM		0x1f#define OP_SH_VIMM		15#define OP_MASK_VMASK		0x1#define OP_SH_VMASK		25#define OP_MASK_VFUNCT6		0x3f#define OP_SH_VFUNCT6		26#define OP_MASK_VLMUL		0x7#define OP_SH_VLMUL		0#define OP_MASK_VSEW		0x7#define OP_SH_VSEW		3#define OP_MASK_VTA		0x1#define OP_SH_VTA		6#define OP_MASK_VMA		0x1#define OP_SH_VMA		7#define OP_MASK_VWD		0x1#define OP_SH_VWD		26 #define OP_MASK_XTHEADVLMUL	0x3#define OP_SH_XTHEADVLMUL	0#define OP_MASK_XTHEADVSEW	0x7#define OP_SH_XTHEADVSEW	2#define OP_MASK_XTHEADVEDIV	0x3#define OP_SH_XTHEADVEDIV	5#define OP_MASK_XTHEADVTYPE_RES	0xf#define OP_SH_XTHEADVTYPE_RES	7 /* Zc fields.  */#define OP_MASK_REG_LIST	0xf#define OP_SH_REG_LIST		4#define ZCMP_SP_ALIGNMENT	16#define OP_MASK_SREG1		0x7#define OP_SH_SREG1		7#define OP_MASK_SREG2		0x7#define OP_SH_SREG2		2 #define NVECR 32#define NVECM 1 /* SiFive fields.  */#define OP_MASK_XSO2            0x3#define OP_SH_XSO2              26#define OP_MASK_XSO1            0x1#define OP_SH_XSO1              26 /* MIPS fields.  */#define OP_MASK_MIPS_IMM9		0x1ff#define OP_SH_MIPS_IMM9		20#define OP_MASK_MIPS_HINT		0x1f#define OP_SH_MIPS_HINT		7#define OP_MASK_MIPS_LWP_OFFSET     0x1f#define OP_SH_MIPS_LWP_OFFSET       22#define OP_MASK_MIPS_LDP_OFFSET     0xf#define OP_SH_MIPS_LDP_OFFSET       23#define OP_MASK_MIPS_SWP_OFFSET9    0x7#define OP_SH_MIPS_SWP_OFFSET9      9#define OP_MASK_MIPS_SWP_OFFSET25   0x3#define OP_SH_MIPS_SWP_OFFSET25     25#define OP_MASK_MIPS_SDP_OFFSET10   0x3#define OP_SH_MIPS_SDP_OFFSET10     10#define OP_MASK_MIPS_SDP_OFFSET25   0x3#define OP_SH_MIPS_SDP_OFFSET25     25 /* ABI names for selected x-registers.  */ #define X_ZERO 0#define X_RA 1#define X_SP 2#define X_GP 3#define X_TP 4#define X_T0 5#define X_T1 6#define X_T2 7#define X_S0 8#define X_S1 9#define X_A0 10#define X_A1 11#define X_S2 18#define X_S7 23#define X_S10 26#define X_S11 27#define X_T3 28 #define NGPR 32#define NFPR 32 /* These fake label defines are use by both the assembler, and   libopcodes.  The assembler uses this when it needs to generate a fake   label, and libopcodes uses it to hide the fake labels in its output.  */#define RISCV_FAKE_LABEL_NAME ".L0 "#define RISCV_FAKE_LABEL_CHAR ' ' /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in   VALUE << SHIFT.  VALUE is evaluated exactly once.  */#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \  (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \	      | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) /* Extract bits MASK << SHIFT from STRUCT and shift them right   SHIFT places.  */#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \  (((STRUCT) >> (SHIFT)) & (MASK)) /* Extract the operand given by FIELD from integer INSN.  */#define EXTRACT_OPERAND(FIELD, INSN) \  ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)) /* Extract an unsigned immediate operand on position s with n bits.  */#define EXTRACT_U_IMM(n, s, l) \  RV_X (l, s, n) /* Extract an signed immediate operand on position s with n bits.  */#define EXTRACT_S_IMM(n, s, l) \  RV_X_SIGNED (l, s, n) /* Validate that unsigned n-bit immediate is within bounds.  */#define VALIDATE_U_IMM(v, n) \  ((unsigned long) v < (1UL << n)) /* Validate that signed n-bit immediate is within bounds.  */#define VALIDATE_S_IMM(v, n) \  (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1))) /* The maximal number of subset can be required.  */#define MAX_SUBSET_NUM 4 /* The range of sregs.  */#define RISCV_SREG_0_7(REGNO) \	((REGNO == X_S0 || REGNO == X_S1) \	 || (REGNO >= X_S2 && REGNO <= X_S7)) /* All RISC-V instructions belong to at least one of these classes.  */enum riscv_insn_class{  INSN_CLASS_NONE,   INSN_CLASS_I,  INSN_CLASS_ZCA,  INSN_CLASS_M,  INSN_CLASS_F,  INSN_CLASS_D,  INSN_CLASS_Q,

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