/* nds32.h -- Header file for nds32 opcode table Copyright (C) 2012-2026 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef OPCODE_NDS32_H#define OPCODE_NDS32_H /* Registers. */#define REG_R0 (0)#define REG_R5 (5)#define REG_R8 (8)#define REG_R10 (10)#define REG_R12 (12)#define REG_R15 (15)#define REG_R16 (16)#define REG_R20 (20)#define REG_TA (15)#define REG_TP (25)#define REG_FP (28)#define REG_GP (29)#define REG_LP (30)#define REG_SP (31) /* Macros for extracting fields or making an instruction. */static const int nds32_r45map[] ATTRIBUTE_UNUSED ={ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19}; static const int nds32_r54map[] ATTRIBUTE_UNUSED ={ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, -1, -1, -1, -1, 12, 13, 14, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}; #define N32_BIT(n) (1u << (n))#define __MASK(n) (N32_BIT (n) - 1)#define __MF(v, off, bs) (((v) & __MASK (bs)) << (off))#define __GF(v, off, bs) (((v) >> off) & __MASK (bs))#define __SEXT(v, bs) \ ((((v) & __MASK ((bs))) ^ N32_BIT ((bs) - 1)) - N32_BIT ((bs) - 1)) /* Make nds32 instructions. */ #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \ | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \ | __MF (rd5, 5, 5) | __MF (sub5, 0, 5))#define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \ (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \ | __MF (sub10, 0, 10))#define N32_TYPE2(op6, rt5, ra5, imm15) \ (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15))#define N32_TYPE1(op6, rt5, imm20) \ (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20))#define N32_TYPE0(op6, imm25) \ (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25))#define N32_ALU1(sub, rt, ra, rb) \ N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub)#define N32_ALU1_SH(sub, rt, ra, rb, rd) \ N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub)#define N32_ALU2(sub, rt, ra, rb) \ N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub)#define N32_BR1(sub, rt, ra, imm14s) \ N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14)))#define N32_BR2(sub, rt, imm16s) \ N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16)))#define N32_BR3(sub, rt, imm11s, imm8s) \ N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \ | ((imm11s & __MASK (11)) << 8) \ | (imm8s & __MASK (8)))#define N32_JI(sub, imm24s) \ N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24)))#define N32_JREG(sub, rt, rb, dtit, hint) \ N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub)#define N32_MEM(sub, rt, ra, rb, sv) \ N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub) #define N16_TYPE55(op5, rt5, ra5) \ (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \ | __MF (ra5, 0, 5))#define N16_TYPE45(op6, rt4, ra5) \ (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \ | __MF (ra5, 0, 5))#define N16_TYPE333(op6, rt3, ra3, rb3) \ (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \ | __MF (ra3, 3, 3) | __MF (rb3, 0, 3))#define N16_TYPE36(op6, rt3, imm6) \ (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \ | __MF (imm6, 0, 6))#define N16_TYPE38(op4, rt3, imm8) \ (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \ | __MF (imm8, 0, 8))#define N16_TYPE37(op4, rt3, ls, imm7) \ (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \ | __MF (imm7, 0, 7) | __MF (ls, 7, 1))#define N16_TYPE5(op10, imm5) \ (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))#define N16_TYPE8(op7, imm8) \ (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8))#define N16_TYPE9(op6, imm9) \ (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9))#define N16_TYPE10(op5, imm10) \ (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))#define N16_TYPE25(op8, re, imm5) \ (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \ | __MF (imm5, 0, 5)) #define N16_MISC33(sub, rt, ra) \ N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub)#define N16_BFMI333(sub, rt, ra) \ N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub) /* Get instruction fields. Macros used for handling 32-bit and 16-bit instructions are prefixed with N32_ and N16_ respectively. */ #define N32_OP6(insn) (((insn) >> 25) & 0x3f)#define N32_RT5(insn) (((insn) >> 20) & 0x1f)#define N32_RT53(insn) (N32_RT5 (insn) & 0x7)#define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)]#define N32_RA5(insn) (((insn) >> 15) & 0x1f)#define N32_RA53(insn) (N32_RA5 (insn) & 0x7)#define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)]#define N32_RB5(insn) (((insn) >> 10) & 0x1f)#define N32_UB5(insn) (((insn) >> 10) & 0x1f)#define N32_RB53(insn) (N32_RB5 (insn) & 0x7)#define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)]#define N32_RD5(insn) (((insn) >> 5) & 0x1f)#define N32_SH5(insn) (((insn) >> 5) & 0x1f)#define N32_SUB5(insn) (((insn) >> 0) & 0x1f)#define N32_SUB6(insn) (((insn) >> 0) & 0x3f)#define N32_SWID(insn) (((insn) >> 5) & 0x3ff)#define N32_IMMU(insn, bs) ((insn) & __MASK (bs))#define N32_IMMS(insn, bs) ((signed) __SEXT ((insn), (bs)))#define N32_IMM5U(insn) N32_IMMU (insn, 5)#define N32_IMM12S(insn) N32_IMMS (insn, 12)#define N32_IMM14S(insn) N32_IMMS (insn, 14)#define N32_IMM15U(insn) N32_IMMU (insn, 15)#define N32_IMM15S(insn) N32_IMMS (insn, 15)#define N32_IMM16S(insn) N32_IMMS (insn, 16)#define N32_IMM17S(insn) N32_IMMS (insn, 17)#define N32_IMM20S(insn) N32_IMMS (insn, 20)#define N32_IMM20U(insn) N32_IMMU (insn, 20)#define N32_IMM24S(insn) N32_IMMS (insn, 24) #define N16_RT5(insn) (((insn) >> 5) & 0x1f)#define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)]#define N16_RT3(insn) (((insn) >> 6) & 0x7)#define N16_RT38(insn) (((insn) >> 8) & 0x7)#define N16_RT8(insn) (((insn) >> 8) & 0x7)#define N16_RA5(insn) ((insn) & 0x1f)#define N16_RA3(insn) (((insn) >> 3) & 0x7)#define N16_RB3(insn) ((insn) & 0x7)#define N16_IMM3U(insn) N32_IMMU (insn, 3)#define N16_IMM5U(insn) N32_IMMU (insn, 5)#define N16_IMM5S(insn) N32_IMMS (insn, 5)#define N16_IMM6U(insn) N32_IMMU (insn, 6)#define N16_IMM7U(insn) N32_IMMU (insn, 7)#define N16_IMM8S(insn) N32_IMMS (insn, 8)#define N16_IMM9U(insn) N32_IMMU (insn, 9)#define N16_IMM10S(insn) N32_IMMS (insn, 10) #define IS_WITHIN_U(v, n) (((v) >> n) == 0)#define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n) /* Get fields for specific instruction. */#define N32_JREG_T(insn) (((insn) >> 8) & 0x3)#define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7)#define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf)#define N32_COP_SUB(insn) ((insn) & 0xf)#define N32_COP_CP(insn) (((insn) >> 4) & 0x3) /* Check fields. */#define N32_IS_RT3(insn) (N32_RT5 (insn) < 8)#define N32_IS_RA3(insn) (N32_RA5 (insn) < 8)#define N32_IS_RB3(insn) (N32_RB5 (insn) < 8)#define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1)#define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1)#define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1) /* These are opcodes for Nxx_TYPE macros. They are prefixed by corresponding TYPE to avoid misusing. */ enum n32_opcodes{ /* Main opcodes (OP6). */ N32_OP6_LBI = 0x0, N32_OP6_LHI, N32_OP6_LWI, N32_OP6_LDI, N32_OP6_LBI_BI, N32_OP6_LHI_BI, N32_OP6_LWI_BI, N32_OP6_LDI_BI, N32_OP6_SBI = 0x8, N32_OP6_SHI, N32_OP6_SWI, N32_OP6_SDI, N32_OP6_SBI_BI, N32_OP6_SHI_BI, N32_OP6_SWI_BI, N32_OP6_SDI_BI, N32_OP6_LBSI = 0x10, N32_OP6_LHSI, N32_OP6_LWSI, N32_OP6_DPREFI, N32_OP6_LBSI_BI, N32_OP6_LHSI_BI, N32_OP6_LWSI_BI, N32_OP6_LBGP, N32_OP6_LWC = 0x18, N32_OP6_SWC, N32_OP6_LDC, N32_OP6_SDC, N32_OP6_MEM, N32_OP6_LSMW, N32_OP6_HWGP, N32_OP6_SBGP, N32_OP6_ALU1 = 0x20, N32_OP6_ALU2, N32_OP6_MOVI, N32_OP6_SETHI, N32_OP6_JI, N32_OP6_JREG, N32_OP6_BR1, N32_OP6_BR2, N32_OP6_ADDI = 0x28, N32_OP6_SUBRI, N32_OP6_ANDI, N32_OP6_XORI, N32_OP6_ORI, N32_OP6_BR3, N32_OP6_SLTI, N32_OP6_SLTSI, N32_OP6_AEXT = 0x30, N32_OP6_CEXT, N32_OP6_MISC, N32_OP6_BITCI, N32_OP6_0x34, N32_OP6_COP, N32_OP6_0x36, N32_OP6_0x37, N32_OP6_SIMD = 0x38, /* Sub-opcodes of specific opcode. */ /* bit-24 */ N32_BR1_BEQ = 0, N32_BR1_BNE = 1, /* bit[16:19] */ N32_BR2_SOP0 = 0, N32_BR2_BEQZ = 2, N32_BR2_BNEZ = 3, N32_BR2_BGEZ = 4, N32_BR2_BLTZ = 5, N32_BR2_BGTZ = 6, N32_BR2_BLEZ = 7, N32_BR2_BGEZAL = 0xc, N32_BR2_BLTZAL = 0xd, /* bit-19 */ N32_BR3_BEQC = 0, N32_BR3_BNEC = 1, /* bit-24 */ N32_JI_J = 0, N32_JI_JAL = 1, /* bit[0:4] */ N32_JREG_JR = 0, N32_JREG_JRAL = 1, N32_JREG_JRNEZ = 2, N32_JREG_JRALNEZ = 3, /* bit[0:4] */ N32_ALU1_ADD_SLLI = 0x0, N32_ALU1_SUB_SLLI, N32_ALU1_AND_SLLI, N32_ALU1_XOR_SLLI, N32_ALU1_OR_SLLI, N32_ALU1_ADD = 0x0, N32_ALU1_SUB, N32_ALU1_AND, N32_ALU1_XOR, N32_ALU1_OR, N32_ALU1_NOR, N32_ALU1_SLT, N32_ALU1_SLTS, N32_ALU1_SLLI = 0x8, N32_ALU1_SRLI, N32_ALU1_SRAI, N32_ALU1_ROTRI, N32_ALU1_SLL, N32_ALU1_SRL, N32_ALU1_SRA, N32_ALU1_ROTR, N32_ALU1_SEB = 0x10, N32_ALU1_SEH, N32_ALU1_BITC, N32_ALU1_ZEH, N32_ALU1_WSBH, N32_ALU1_OR_SRLI, N32_ALU1_DIVSR, N32_ALU1_DIVR, N32_ALU1_SVA = 0x18, N32_ALU1_SVS, N32_ALU1_CMOVZ, N32_ALU1_CMOVN, N32_ALU1_ADD_SRLI, N32_ALU1_SUB_SRLI, N32_ALU1_AND_SRLI, N32_ALU1_XOR_SRLI, /* bit[0:5], where bit[6:9] == 0 */ N32_ALU2_MAX = 0, N32_ALU2_MIN, N32_ALU2_AVE, N32_ALU2_ABS, N32_ALU2_CLIPS, N32_ALU2_CLIP, N32_ALU2_CLO, N32_ALU2_CLZ, N32_ALU2_BSET = 0x8, N32_ALU2_BCLR, N32_ALU2_BTGL, N32_ALU2_BTST, N32_ALU2_BSE, N32_ALU2_BSP, N32_ALU2_FFB, N32_ALU2_FFMISM, N32_ALU2_ADD_SC = 0x10, N32_ALU2_SUB_SC, N32_ALU2_ADD_WC, N32_ALU2_SUB_WC, N32_ALU2_KMxy, N32_ALU2_0x15, N32_ALU2_0x16, N32_ALU2_FFZMISM, N32_ALU2_KADD = 0x18, N32_ALU2_KSUB, N32_ALU2_KSLRAW, N32_ALU2_KSLRAWu, N32_ALU2_MFUSR = 0x20, N32_ALU2_MTUSR, N32_ALU2_0x22, N32_ALU2_0x23, N32_ALU2_MUL, N32_ALU2_0x25, N32_ALU2_0x26, N32_ALU2_MULTS64 = 0x28, N32_ALU2_MULT64, N32_ALU2_MADDS64, N32_ALU2_MADD64, N32_ALU2_MSUBS64, N32_ALU2_MSUB64, N32_ALU2_DIVS, N32_ALU2_DIV, N32_ALU2_ADD64 = 0x30, N32_ALU2_MULT32, N32_ALU2_SMAL, N32_ALU2_MADD32, N32_ALU2_SUB64, N32_ALU2_MSUB32, N32_ALU2_0x36, N32_ALU2_0x37, N32_ALU2_RADD64 = 0x38, N32_ALU2_URADD64, N32_ALU2_KADD64, N32_ALU2_UKADD64, N32_ALU2_RSUB64, N32_ALU2_URSUB64, N32_ALU2_KSUB64, N32_ALU2_UKSUB64, /* bit[0:5], where bit[6:9] = 0001 */ N32_ALU2_SMAR64 = 0x0, N32_ALU2_UMAR64, N32_ALU2_SMSR64, N32_ALU2_UMSR64, N32_ALU2_KMAR64, N32_ALU2_UKMAR64, N32_ALU2_KMSR64, N32_ALU2_UKMSR64, N32_ALU2_SMALDA = 0x8, N32_ALU2_SMSLDA, N32_ALU2_SMALDS, N32_ALU2_SMALBB, N32_ALU2_FFBI = 0xe, N32_ALU2_FLMISM = 0xf, N32_ALU2_SMALXDA = 0x10, N32_ALU2_SMSLXDA, N32_ALU2_SMALXDS, N32_ALU2_SMALBT, N32_ALU2_SMALDRS = 0x1a, N32_ALU2_SMALTT, N32_ALU2_RDOV = 0x20, N32_ALU2_CLROV, N32_ALU2_MULSR64 = 0x28, N32_ALU2_MULR64 = 0x29, N32_ALU2_SMDS = 0x30, N32_ALU2_SMXDS, N32_ALU2_SMDRS, N32_ALU2_MADDR32, N32_ALU2_KMADRS, N32_ALU2_MSUBR32, N32_ALU2_KMADS, N32_ALU2_KMAXDS, /* bit[0:5], where bit[6:9] = 0010 */ N32_ALU2_KADD16 = 0x0, N32_ALU2_KSUB16, N32_ALU2_KCRAS16, N32_ALU2_KCRSA16, N32_ALU2_KADD8, N32_ALU2_KSUB8, N32_ALU2_WEXT, N32_ALU2_WEXTI, N32_ALU2_UKADD16 = 0x8, N32_ALU2_UKSUB16, N32_ALU2_UKCRAS16, N32_ALU2_UKCRSA16, N32_ALU2_UKADD8, N32_ALU2_UKSUB8, N32_ALU2_ONEOP = 0xf, N32_ALU2_SMBB = 0x10, N32_ALU2_SMBT, N32_ALU2_SMTT, N32_ALU2_KMABB = 0x15, N32_ALU2_KMABT, N32_ALU2_KMATT, N32_ALU2_KMDA = 0x18, N32_ALU2_KMXDA, N32_ALU2_KMADA, N32_ALU2_KMAXDA, N32_ALU2_KMSDA, N32_ALU2_KMSXDA, N32_ALU2_RADD16 = 0x20, N32_ALU2_RSUB16, N32_ALU2_RCRAS16, N32_ALU2_RCRSA16, N32_ALU2_RADD8, N32_ALU2_RSUB8, N32_ALU2_RADDW, N32_ALU2_RSUBW, N32_ALU2_URADD16 = 0x28, N32_ALU2_URSUB16, N32_ALU2_URCRAS16, N32_ALU2_URCRSA16, N32_ALU2_URADD8, N32_ALU2_URSUB8, N32_ALU2_URADDW, N32_ALU2_URSUBW, N32_ALU2_ADD16 = 0x30, N32_ALU2_SUB16, N32_ALU2_CRAS16, N32_ALU2_CRSA16, N32_ALU2_ADD8, N32_ALU2_SUB8, N32_ALU2_BITREV, N32_ALU2_BITREVI, N32_ALU2_SMMUL = 0x38, N32_ALU2_SMMULu, N32_ALU2_KMMAC, N32_ALU2_KMMACu, N32_ALU2_KMMSB, N32_ALU2_KMMSBu, N32_ALU2_KWMMUL, N32_ALU2_KWMMULu, /* bit[0:5], where bit[6:9] = 0011 */Lines 1–500 of 990. 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/* nds32.h -- Header file for nds32 opcode table Copyright (C) 2012-2026 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef OPCODE_NDS32_H #define OPCODE_NDS32_H /* Registers. */ #define REG_R0 (0) #define REG_R5 (5) #define REG_R8 (8) #define REG_R10 (10) #define REG_R12 (12) #define REG_R15 (15) #define REG_R16 (16) #define REG_R20 (20) #define REG_TA (15) #define REG_TP (25) #define REG_FP (28) #define REG_GP (29) #define REG_LP (30) #define REG_SP (31) /* Macros for extracting fields or making an instruction. */ static const int nds32_r45map[] ATTRIBUTE_UNUSED = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19 }; static const int nds32_r54map[] ATTRIBUTE_UNUSED = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, -1, -1, -1, -1, 12, 13, 14, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; #define N32_BIT(n) (1u << (n)) #define __MASK(n) (N32_BIT (n) - 1) #define __MF(v, off, bs) (((v) & __MASK (bs)) << (off)) #define __GF(v, off, bs) (((v) >> off) & __MASK (bs)) #define __SEXT(v, bs) \ ((((v) & __MASK ((bs))) ^ N32_BIT ((bs) - 1)) - N32_BIT ((bs) - 1)) /* Make nds32 instructions. */ #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \ | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \ | __MF (rd5, 5, 5) | __MF (sub5, 0, 5)) #define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \ (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \ | __MF (sub10, 0, 10)) #define N32_TYPE2(op6, rt5, ra5, imm15) \ (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15)) #define N32_TYPE1(op6, rt5, imm20) \ (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20)) #define N32_TYPE0(op6, imm25) \ (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25)) #define N32_ALU1(sub, rt, ra, rb) \ N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub) #define N32_ALU1_SH(sub, rt, ra, rb, rd) \ N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub) #define N32_ALU2(sub, rt, ra, rb) \ N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub) #define N32_BR1(sub, rt, ra, imm14s) \ N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14))) #define N32_BR2(sub, rt, imm16s) \ N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16))) #define N32_BR3(sub, rt, imm11s, imm8s) \ N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \ | ((imm11s & __MASK (11)) << 8) \ | (imm8s & __MASK (8))) #define N32_JI(sub, imm24s) \ N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24))) #define N32_JREG(sub, rt, rb, dtit, hint) \ N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub) #define N32_MEM(sub, rt, ra, rb, sv) \ N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub) #define N16_TYPE55(op5, rt5, ra5) \ (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \ | __MF (ra5, 0, 5)) #define N16_TYPE45(op6, rt4, ra5) \ (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \ | __MF (ra5, 0, 5)) #define N16_TYPE333(op6, rt3, ra3, rb3) \ (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \ | __MF (ra3, 3, 3) | __MF (rb3, 0, 3)) #define N16_TYPE36(op6, rt3, imm6) \ (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \ | __MF (imm6, 0, 6)) #define N16_TYPE38(op4, rt3, imm8) \ (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \ | __MF (imm8, 0, 8)) #define N16_TYPE37(op4, rt3, ls, imm7) \ (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \ | __MF (imm7, 0, 7) | __MF (ls, 7, 1)) #define N16_TYPE5(op10, imm5) \ (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5)) #define N16_TYPE8(op7, imm8) \ (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8)) #define N16_TYPE9(op6, imm9) \ (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9)) #define N16_TYPE10(op5, imm10) \ (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10)) #define N16_TYPE25(op8, re, imm5) \ (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \ | __MF (imm5, 0, 5)) #define N16_MISC33(sub, rt, ra) \ N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub) #define N16_BFMI333(sub, rt, ra) \ N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub) /* Get instruction fields. Macros used for handling 32-bit and 16-bit instructions are prefixed with N32_ and N16_ respectively. */ #define N32_OP6(insn) (((insn) >> 25) & 0x3f) #define N32_RT5(insn) (((insn) >> 20) & 0x1f) #define N32_RT53(insn) (N32_RT5 (insn) & 0x7) #define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)] #define N32_RA5(insn) (((insn) >> 15) & 0x1f) #define N32_RA53(insn) (N32_RA5 (insn) & 0x7) #define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)] #define N32_RB5(insn) (((insn) >> 10) & 0x1f) #define N32_UB5(insn) (((insn) >> 10) & 0x1f) #define N32_RB53(insn) (N32_RB5 (insn) & 0x7) #define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)] #define N32_RD5(insn) (((insn) >> 5) & 0x1f) #define N32_SH5(insn) (((insn) >> 5) & 0x1f) #define N32_SUB5(insn) (((insn) >> 0) & 0x1f) #define N32_SUB6(insn) (((insn) >> 0) & 0x3f) #define N32_SWID(insn) (((insn) >> 5) & 0x3ff) #define N32_IMMU(insn, bs) ((insn) & __MASK (bs)) #define N32_IMMS(insn, bs) ((signed) __SEXT ((insn), (bs))) #define N32_IMM5U(insn) N32_IMMU (insn, 5) #define N32_IMM12S(insn) N32_IMMS (insn, 12) #define N32_IMM14S(insn) N32_IMMS (insn, 14) #define N32_IMM15U(insn) N32_IMMU (insn, 15) #define N32_IMM15S(insn) N32_IMMS (insn, 15) #define N32_IMM16S(insn) N32_IMMS (insn, 16) #define N32_IMM17S(insn) N32_IMMS (insn, 17) #define N32_IMM20S(insn) N32_IMMS (insn, 20) #define N32_IMM20U(insn) N32_IMMU (insn, 20) #define N32_IMM24S(insn) N32_IMMS (insn, 24) #define N16_RT5(insn) (((insn) >> 5) & 0x1f) #define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)] #define N16_RT3(insn) (((insn) >> 6) & 0x7) #define N16_RT38(insn) (((insn) >> 8) & 0x7) #define N16_RT8(insn) (((insn) >> 8) & 0x7) #define N16_RA5(insn) ((insn) & 0x1f) #define N16_RA3(insn) (((insn) >> 3) & 0x7) #define N16_RB3(insn) ((insn) & 0x7) #define N16_IMM3U(insn) N32_IMMU (insn, 3) #define N16_IMM5U(insn) N32_IMMU (insn, 5) #define N16_IMM5S(insn) N32_IMMS (insn, 5) #define N16_IMM6U(insn) N32_IMMU (insn, 6) #define N16_IMM7U(insn) N32_IMMU (insn, 7) #define N16_IMM8S(insn) N32_IMMS (insn, 8) #define N16_IMM9U(insn) N32_IMMU (insn, 9) #define N16_IMM10S(insn) N32_IMMS (insn, 10) #define IS_WITHIN_U(v, n) (((v) >> n) == 0) #define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n) /* Get fields for specific instruction. */ #define N32_JREG_T(insn) (((insn) >> 8) & 0x3) #define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7) #define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf) #define N32_COP_SUB(insn) ((insn) & 0xf) #define N32_COP_CP(insn) (((insn) >> 4) & 0x3) /* Check fields. */ #define N32_IS_RT3(insn) (N32_RT5 (insn) < 8) #define N32_IS_RA3(insn) (N32_RA5 (insn) < 8) #define N32_IS_RB3(insn) (N32_RB5 (insn) < 8) #define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1) #define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1) #define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1) /* These are opcodes for Nxx_TYPE macros. They are prefixed by corresponding TYPE to avoid misusing. */ enum n32_opcodes { /* Main opcodes (OP6). */ N32_OP6_LBI = 0x0, N32_OP6_LHI, N32_OP6_LWI, N32_OP6_LDI, N32_OP6_LBI_BI, N32_OP6_LHI_BI, N32_OP6_LWI_BI, N32_OP6_LDI_BI, N32_OP6_SBI = 0x8, N32_OP6_SHI, N32_OP6_SWI, N32_OP6_SDI, N32_OP6_SBI_BI, N32_OP6_SHI_BI, N32_OP6_SWI_BI, N32_OP6_SDI_BI, N32_OP6_LBSI = 0x10, N32_OP6_LHSI, N32_OP6_LWSI, N32_OP6_DPREFI, N32_OP6_LBSI_BI, N32_OP6_LHSI_BI, N32_OP6_LWSI_BI, N32_OP6_LBGP, N32_OP6_LWC = 0x18, N32_OP6_SWC, N32_OP6_LDC, N32_OP6_SDC, N32_OP6_MEM, N32_OP6_LSMW, N32_OP6_HWGP, N32_OP6_SBGP, N32_OP6_ALU1 = 0x20, N32_OP6_ALU2, N32_OP6_MOVI, N32_OP6_SETHI, N32_OP6_JI, N32_OP6_JREG, N32_OP6_BR1, N32_OP6_BR2, N32_OP6_ADDI = 0x28, N32_OP6_SUBRI, N32_OP6_ANDI, N32_OP6_XORI, N32_OP6_ORI, N32_OP6_BR3, N32_OP6_SLTI, N32_OP6_SLTSI, N32_OP6_AEXT = 0x30, N32_OP6_CEXT, N32_OP6_MISC, N32_OP6_BITCI, N32_OP6_0x34, N32_OP6_COP, N32_OP6_0x36, N32_OP6_0x37, N32_OP6_SIMD = 0x38, /* Sub-opcodes of specific opcode. */ /* bit-24 */ N32_BR1_BEQ = 0, N32_BR1_BNE = 1, /* bit[16:19] */ N32_BR2_SOP0 = 0, N32_BR2_BEQZ = 2, N32_BR2_BNEZ = 3, N32_BR2_BGEZ = 4, N32_BR2_BLTZ = 5, N32_BR2_BGTZ = 6, N32_BR2_BLEZ = 7, N32_BR2_BGEZAL = 0xc, N32_BR2_BLTZAL = 0xd, /* bit-19 */ N32_BR3_BEQC = 0, N32_BR3_BNEC = 1, /* bit-24 */ N32_JI_J = 0, N32_JI_JAL = 1, /* bit[0:4] */ N32_JREG_JR = 0, N32_JREG_JRAL = 1, N32_JREG_JRNEZ = 2, N32_JREG_JRALNEZ = 3, /* bit[0:4] */ N32_ALU1_ADD_SLLI = 0x0, N32_ALU1_SUB_SLLI, N32_ALU1_AND_SLLI, N32_ALU1_XOR_SLLI, N32_ALU1_OR_SLLI, N32_ALU1_ADD = 0x0, N32_ALU1_SUB, N32_ALU1_AND, N32_ALU1_XOR, N32_ALU1_OR, N32_ALU1_NOR, N32_ALU1_SLT, N32_ALU1_SLTS, N32_ALU1_SLLI = 0x8, N32_ALU1_SRLI, N32_ALU1_SRAI, N32_ALU1_ROTRI, N32_ALU1_SLL, N32_ALU1_SRL, N32_ALU1_SRA, N32_ALU1_ROTR, N32_ALU1_SEB = 0x10, N32_ALU1_SEH, N32_ALU1_BITC, N32_ALU1_ZEH, N32_ALU1_WSBH, N32_ALU1_OR_SRLI, N32_ALU1_DIVSR, N32_ALU1_DIVR, N32_ALU1_SVA = 0x18, N32_ALU1_SVS, N32_ALU1_CMOVZ, N32_ALU1_CMOVN, N32_ALU1_ADD_SRLI, N32_ALU1_SUB_SRLI, N32_ALU1_AND_SRLI, N32_ALU1_XOR_SRLI, /* bit[0:5], where bit[6:9] == 0 */ N32_ALU2_MAX = 0, N32_ALU2_MIN, N32_ALU2_AVE, N32_ALU2_ABS, N32_ALU2_CLIPS, N32_ALU2_CLIP, N32_ALU2_CLO, N32_ALU2_CLZ, N32_ALU2_BSET = 0x8, N32_ALU2_BCLR, N32_ALU2_BTGL, N32_ALU2_BTST, N32_ALU2_BSE, N32_ALU2_BSP, N32_ALU2_FFB, N32_ALU2_FFMISM, N32_ALU2_ADD_SC = 0x10, N32_ALU2_SUB_SC, N32_ALU2_ADD_WC, N32_ALU2_SUB_WC, N32_ALU2_KMxy, N32_ALU2_0x15, N32_ALU2_0x16, N32_ALU2_FFZMISM, N32_ALU2_KADD = 0x18, N32_ALU2_KSUB, N32_ALU2_KSLRAW, N32_ALU2_KSLRAWu, N32_ALU2_MFUSR = 0x20, N32_ALU2_MTUSR, N32_ALU2_0x22, N32_ALU2_0x23, N32_ALU2_MUL, N32_ALU2_0x25, N32_ALU2_0x26, N32_ALU2_MULTS64 = 0x28, N32_ALU2_MULT64, N32_ALU2_MADDS64, N32_ALU2_MADD64, N32_ALU2_MSUBS64, N32_ALU2_MSUB64, N32_ALU2_DIVS, N32_ALU2_DIV, N32_ALU2_ADD64 = 0x30, N32_ALU2_MULT32, N32_ALU2_SMAL, N32_ALU2_MADD32, N32_ALU2_SUB64, N32_ALU2_MSUB32, N32_ALU2_0x36, N32_ALU2_0x37, N32_ALU2_RADD64 = 0x38, N32_ALU2_URADD64, N32_ALU2_KADD64, N32_ALU2_UKADD64, N32_ALU2_RSUB64, N32_ALU2_URSUB64, N32_ALU2_KSUB64, N32_ALU2_UKSUB64, /* bit[0:5], where bit[6:9] = 0001 */ N32_ALU2_SMAR64 = 0x0, N32_ALU2_UMAR64, N32_ALU2_SMSR64, N32_ALU2_UMSR64, N32_ALU2_KMAR64, N32_ALU2_UKMAR64, N32_ALU2_KMSR64, N32_ALU2_UKMSR64, N32_ALU2_SMALDA = 0x8, N32_ALU2_SMSLDA, N32_ALU2_SMALDS, N32_ALU2_SMALBB, N32_ALU2_FFBI = 0xe, N32_ALU2_FLMISM = 0xf, N32_ALU2_SMALXDA = 0x10, N32_ALU2_SMSLXDA, N32_ALU2_SMALXDS, N32_ALU2_SMALBT, N32_ALU2_SMALDRS = 0x1a, N32_ALU2_SMALTT, N32_ALU2_RDOV = 0x20, N32_ALU2_CLROV, N32_ALU2_MULSR64 = 0x28, N32_ALU2_MULR64 = 0x29, N32_ALU2_SMDS = 0x30, N32_ALU2_SMXDS, N32_ALU2_SMDRS, N32_ALU2_MADDR32, N32_ALU2_KMADRS, N32_ALU2_MSUBR32, N32_ALU2_KMADS, N32_ALU2_KMAXDS, /* bit[0:5], where bit[6:9] = 0010 */ N32_ALU2_KADD16 = 0x0, N32_ALU2_KSUB16, N32_ALU2_KCRAS16, N32_ALU2_KCRSA16, N32_ALU2_KADD8, N32_ALU2_KSUB8, N32_ALU2_WEXT, N32_ALU2_WEXTI, N32_ALU2_UKADD16 = 0x8, N32_ALU2_UKSUB16, N32_ALU2_UKCRAS16, N32_ALU2_UKCRSA16, N32_ALU2_UKADD8, N32_ALU2_UKSUB8, N32_ALU2_ONEOP = 0xf, N32_ALU2_SMBB = 0x10, N32_ALU2_SMBT, N32_ALU2_SMTT, N32_ALU2_KMABB = 0x15, N32_ALU2_KMABT, N32_ALU2_KMATT, N32_ALU2_KMDA = 0x18, N32_ALU2_KMXDA, N32_ALU2_KMADA, N32_ALU2_KMAXDA, N32_ALU2_KMSDA, N32_ALU2_KMSXDA, N32_ALU2_RADD16 = 0x20, N32_ALU2_RSUB16, N32_ALU2_RCRAS16, N32_ALU2_RCRSA16, N32_ALU2_RADD8, N32_ALU2_RSUB8, N32_ALU2_RADDW, N32_ALU2_RSUBW, N32_ALU2_URADD16 = 0x28, N32_ALU2_URSUB16, N32_ALU2_URCRAS16, N32_ALU2_URCRSA16, N32_ALU2_URADD8, N32_ALU2_URSUB8, N32_ALU2_URADDW, N32_ALU2_URSUBW, N32_ALU2_ADD16 = 0x30, N32_ALU2_SUB16, N32_ALU2_CRAS16, N32_ALU2_CRSA16, N32_ALU2_ADD8, N32_ALU2_SUB8, N32_ALU2_BITREV, N32_ALU2_BITREVI, N32_ALU2_SMMUL = 0x38, N32_ALU2_SMMULu, N32_ALU2_KMMAC, N32_ALU2_KMMACu, N32_ALU2_KMMSB, N32_ALU2_KMMSBu, N32_ALU2_KWMMUL, N32_ALU2_KWMMULu, /* bit[0:5], where bit[6:9] = 0011 */