/* Imagination Technologies Meta opcode table.   Copyright (C) 2013-2026 Free Software Foundation, Inc.   Contributed by Imagination Technologies Ltd.    This file is part of GDB and GAS.    GDB and GAS are free software; you can redistribute it and/or   modify it under the terms of the GNU General Public License as   published by the Free Software Foundation; either version 3, or (at   your option) any later version.    GDB and GAS are distributed in the hope that it will be useful, but   WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU   General Public License for more details.    You should have received a copy of the GNU General Public License   along with GDB or GAS; see the file COPYING3.  If not, write to the   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,   MA 02110-1301, USA.  */ #ifdef __cplusplusextern "C" {#endif enum metag_unit{  UNIT_CT,  UNIT_D0,  UNIT_D1,  UNIT_A0,  UNIT_A1,  UNIT_PC,  UNIT_RD,  UNIT_TR,  UNIT_TT,  UNIT_FX,  UNIT_DT,			/* DSP Template Table */  UNIT_ACC_D0,  UNIT_ACC_D1,  UNIT_RAM_D0,  UNIT_RAM_D1,}; typedef struct{  const char *     name;  enum metag_unit  unit;  unsigned int     no;} metag_reg; static const metag_reg metag_regtab[] =  {    { "TXENABLE",   UNIT_CT,  0 },    { "CT.0",       UNIT_CT,  0 },    { "TXMODE",     UNIT_CT,  1 },    { "CT.1",       UNIT_CT,  1 },    { "TXSTATUS",   UNIT_CT,  2 },    { "CT.2",       UNIT_CT,  2 },    { "TXRPT",      UNIT_CT,  3 },    { "CT.3",       UNIT_CT,  3 },    { "TXTIMER",    UNIT_CT,  4 },    { "CT.4",       UNIT_CT,  4 },    { "TXL1START",  UNIT_CT,  5 },    { "CT.5",       UNIT_CT,  5 },    { "TXL1END",    UNIT_CT,  6 },    { "CT.6",       UNIT_CT,  6 },    { "TXL1COUNT",  UNIT_CT,  7 },    { "CT.7",       UNIT_CT,  7 },    { "TXL2START",  UNIT_CT,  8 },    { "CT.8",       UNIT_CT,  8 },    { "TXL2END",    UNIT_CT,  9 },    { "CT.9",       UNIT_CT,  9 },    { "TXL2COUNT",  UNIT_CT, 10 },    { "CT.10",      UNIT_CT, 10 },    { "TXBPOBITS",  UNIT_CT, 11 },    { "CT.11",      UNIT_CT, 11 },    { "TXMRSIZE",   UNIT_CT, 12 },    { "CT.12",      UNIT_CT, 12 },    { "TXTIMERI",   UNIT_CT, 13 },    { "CT.13",      UNIT_CT, 13 },    { "TXDRCTRL",   UNIT_CT, 14 },    { "CT.14",      UNIT_CT, 14 },    { "TXDRSIZE",   UNIT_CT, 15 },    { "CT.15",      UNIT_CT, 15 },    { "TXCATCH0",   UNIT_CT, 16 },    { "CT.16",      UNIT_CT, 16 },    { "TXCATCH1",   UNIT_CT, 17 },    { "CT.17",      UNIT_CT, 17 },    { "TXCATCH2",   UNIT_CT, 18 },    { "CT.18",      UNIT_CT, 18 },    { "TXCATCH3",   UNIT_CT, 19 },    { "CT.19",      UNIT_CT, 19 },    { "TXDEFR",     UNIT_CT, 20 },    { "CT.20",      UNIT_CT, 20 },    { "TXCPRS",     UNIT_CT, 21 },    { "CT.21",      UNIT_CT, 21 },    { "TXCLKCTRL",  UNIT_CT, 22 },    { "CT.22",      UNIT_CT, 22 },    { "TXINTERN0",  UNIT_CT, 23 },    { "TXSTATE",    UNIT_CT, 23 },    { "CT.23",      UNIT_CT, 23 },    { "TXAMAREG0",  UNIT_CT, 24 },    { "CT.24",      UNIT_CT, 24 },    { "TXAMAREG1",  UNIT_CT, 25 },    { "CT.25",      UNIT_CT, 25 },    { "TXAMAREG2",  UNIT_CT, 26 },    { "CT.26",      UNIT_CT, 26 },    { "TXAMAREG3",  UNIT_CT, 27 },    { "CT.27",      UNIT_CT, 27 },    { "TXDIVTIME",  UNIT_CT, 28 },    { "CT.28",      UNIT_CT, 28 },    { "TXPRIVEXT",  UNIT_CT, 29 },    { "CT.29",      UNIT_CT, 29 },    { "TXTACTCYC",  UNIT_CT, 30 },    { "TXACTCYC",   UNIT_CT, 30 },    { "CT.30",      UNIT_CT, 30 },    { "TXIDLECYC",  UNIT_CT, 31 },    { "CT.31",      UNIT_CT, 31 },     { "D0Re0",      UNIT_D0,  0 },    { "D0.0",       UNIT_D0,  0 },    { "D0Ar6",      UNIT_D0,  1 },    { "D0.1",       UNIT_D0,  1 },    { "D0Ar4",      UNIT_D0,  2 },    { "D0.2",       UNIT_D0,  2 },    { "D0Ar2",      UNIT_D0,  3 },    { "D0.3",       UNIT_D0,  3 },    { "D0FrT",      UNIT_D0,  4 },    { "D0.4",       UNIT_D0,  4 },    { "D0.5",       UNIT_D0,  5 },    { "D0.6",       UNIT_D0,  6 },    { "D0.7",       UNIT_D0,  7 },    { "D0.8",       UNIT_D0,  8 },    { "D0.9",       UNIT_D0,  9 },    { "D0.10",      UNIT_D0, 10 },    { "D0.11",      UNIT_D0, 11 },    { "D0.12",      UNIT_D0, 12 },    { "D0.13",      UNIT_D0, 13 },    { "D0.14",      UNIT_D0, 14 },    { "D0.15",      UNIT_D0, 15 },    { "D0.16",      UNIT_D0, 16 },    { "D0.17",      UNIT_D0, 17 },    { "D0.18",      UNIT_D0, 18 },    { "D0.19",      UNIT_D0, 19 },    { "D0.20",      UNIT_D0, 20 },    { "D0.21",      UNIT_D0, 21 },    { "D0.22",      UNIT_D0, 22 },    { "D0.23",      UNIT_D0, 23 },    { "D0.24",      UNIT_D0, 24 },    { "D0.25",      UNIT_D0, 25 },    { "D0.26",      UNIT_D0, 26 },    { "D0.27",      UNIT_D0, 27 },    { "D0.28",      UNIT_D0, 28 },    { "D0.29",      UNIT_D0, 29 },    { "D0.30",      UNIT_D0, 30 },    { "D0.31",      UNIT_D0, 31 },     { "D1Re0",      UNIT_D1,  0 },    { "D1.0",       UNIT_D1,  0 },    { "D1Ar5",      UNIT_D1,  1 },    { "D1.1",       UNIT_D1,  1 },    { "D1Ar3",      UNIT_D1,  2 },    { "D1.2",       UNIT_D1,  2 },    { "D1Ar1",      UNIT_D1,  3 },    { "D1.3",       UNIT_D1,  3 },    { "D1RtP",      UNIT_D1,  4 },    { "D1.4",       UNIT_D1,  4 },    { "D1.5",       UNIT_D1,  5 },    { "D1.6",       UNIT_D1,  6 },    { "D1.7",       UNIT_D1,  7 },    { "D1.8",       UNIT_D1,  8 },    { "D1.9",       UNIT_D1,  9 },    { "D1.10",      UNIT_D1, 10 },    { "D1.11",      UNIT_D1, 11 },    { "D1.12",      UNIT_D1, 12 },    { "D1.13",      UNIT_D1, 13 },    { "D1.14",      UNIT_D1, 14 },    { "D1.15",      UNIT_D1, 15 },    { "D1.16",      UNIT_D1, 16 },    { "D1.17",      UNIT_D1, 17 },    { "D1.18",      UNIT_D1, 18 },    { "D1.19",      UNIT_D1, 19 },    { "D1.20",      UNIT_D1, 20 },    { "D1.21",      UNIT_D1, 21 },    { "D1.22",      UNIT_D1, 22 },    { "D1.23",      UNIT_D1, 23 },    { "D1.24",      UNIT_D1, 24 },    { "D1.25",      UNIT_D1, 25 },    { "D1.26",      UNIT_D1, 26 },    { "D1.27",      UNIT_D1, 27 },    { "D1.28",      UNIT_D1, 28 },    { "D1.29",      UNIT_D1, 29 },    { "D1.30",      UNIT_D1, 30 },    { "D1.31",      UNIT_D1, 31 },     { "A0StP",      UNIT_A0,  0 },    { "A0.0",       UNIT_A0,  0 },    { "A0FrP",      UNIT_A0,  1 },    { "A0.1",       UNIT_A0,  1 },    { "A0.2",       UNIT_A0,  2 },    { "A0.3",       UNIT_A0,  3 },    { "A0.4",       UNIT_A0,  4 },    { "A0.5",       UNIT_A0,  5 },    { "A0.6",       UNIT_A0,  6 },    { "A0.7",       UNIT_A0,  7 },    { "A0.8",       UNIT_A0,  8 },    { "A0.9",       UNIT_A0,  9 },    { "A0.10",      UNIT_A0, 10 },    { "A0.11",      UNIT_A0, 11 },    { "A0.12",      UNIT_A0, 12 },    { "A0.13",      UNIT_A0, 13 },    { "A0.14",      UNIT_A0, 14 },    { "A0.15",      UNIT_A0, 15 },    { "CPC0",       UNIT_A0, 16 },     { "A1GbP",      UNIT_A1,  0 },    { "A1.0",       UNIT_A1,  0 },    { "A1LbP",      UNIT_A1,  1 },    { "A1.1",       UNIT_A1,  1 },    { "A1.2",       UNIT_A1,  2 },    { "A1.3",       UNIT_A1,  3 },    { "A1.4",       UNIT_A1,  4 },    { "A1.5",       UNIT_A1,  5 },    { "A1.6",       UNIT_A1,  6 },    { "A1.7",       UNIT_A1,  7 },    { "A1.8",       UNIT_A1,  8 },    { "A1.9",       UNIT_A1,  9 },    { "A1.10",      UNIT_A1, 10 },    { "A1.11",      UNIT_A1, 11 },    { "A1.12",      UNIT_A1, 12 },    { "A1.13",      UNIT_A1, 13 },    { "A1.14",      UNIT_A1, 14 },    { "A1.15",      UNIT_A1, 15 },    { "CPC1",       UNIT_A1, 16 },     { "PC",         UNIT_PC,  0 },    { "PCX",        UNIT_PC,  1 },     { "RD",         UNIT_RD,  0 },    { "RA",         UNIT_RD, 16 },    { "RD",         UNIT_RD, 16 },    { "RAPF",       UNIT_RD, 17 },    { "RAM8X32",    UNIT_RD, 22 },    { "RAM8X",      UNIT_RD, 23 },    { "RABZ",       UNIT_RD, 24 },    { "RAWZ",       UNIT_RD, 25 },    { "RADZ",       UNIT_RD, 26 },    { "RABX",       UNIT_RD, 28 },    { "RAWX",       UNIT_RD, 29 },    { "RADX",       UNIT_RD, 30 },    { "RAMX",       UNIT_RD, 31 },    { "RAM16X",     UNIT_RD, 31 },     { "TXSTAT",     UNIT_TR,  0 },    { "TR.0",       UNIT_TR,  0 },    { "TXMASK",     UNIT_TR,  1 },    { "TR.1",       UNIT_TR,  1 },    { "TXSTATI",    UNIT_TR,  2 },    { "TR.2",       UNIT_TR,  2 },    { "TXMASKI",    UNIT_TR,  3 },    { "TR.3",       UNIT_TR,  3 },    { "TXPOLL",     UNIT_TR,  4 },    { "TR.4",       UNIT_TR,  4 },    { "TXGPIOI",    UNIT_TR,  5 },    { "TR.5",       UNIT_TR,  5 },    { "TXPOLLI",    UNIT_TR,  6 },    { "TR.6",       UNIT_TR,  6 },    { "TXGPIOO",    UNIT_TR,  7 },    { "TR.7",       UNIT_TR,  7 },     { "TTEXEC",     UNIT_TT,  0 },    { "TT.0",       UNIT_TT,  0 },    { "TTCTRL",     UNIT_TT,  1 },    { "TT.1",       UNIT_TT,  1 },    { "TTMARK",     UNIT_TT,  2 },    { "TT.2",       UNIT_TT,  2 },    { "TTREC",      UNIT_TT,  3 },    { "TT.3",       UNIT_TT,  3 },    { "GTEXEC",     UNIT_TT,  4 },    { "TT.4",       UNIT_TT,  4 },     { "FX.0",       UNIT_FX,  0 },    { "FX.1",       UNIT_FX,  1 },    { "FX.2",       UNIT_FX,  2 },    { "FX.3",       UNIT_FX,  3 },    { "FX.4",       UNIT_FX,  4 },    { "FX.5",       UNIT_FX,  5 },    { "FX.6",       UNIT_FX,  6 },    { "FX.7",       UNIT_FX,  7 },    { "FX.8",       UNIT_FX,  8 },    { "FX.9",       UNIT_FX,  9 },    { "FX.10",      UNIT_FX, 10 },    { "FX.11",      UNIT_FX, 11 },    { "FX.12",      UNIT_FX, 12 },    { "FX.13",      UNIT_FX, 13 },    { "FX.14",      UNIT_FX, 14 },    { "FX.15",      UNIT_FX, 15 },  }; static const metag_reg metag_dsp_regtab[] =  {    { "D0AR.0",   UNIT_RAM_D0,  0 },    { "D0AR.1",   UNIT_RAM_D0,  1 },    { "D0AW.0",   UNIT_RAM_D0,  2 },    { "D0AW.1",   UNIT_RAM_D0,  3 },    { "D0BR.0",   UNIT_RAM_D0,  4 },    { "D0BR.1",   UNIT_RAM_D0,  5 },    { "D0BW.0",   UNIT_RAM_D0,  6 },    { "D0BW.1",   UNIT_RAM_D0,  7 },    { "D0ARI.0",  UNIT_RAM_D0,  8 },    { "D0ARI.1",  UNIT_RAM_D0,  9 },    { "D0AWI.0",  UNIT_RAM_D0, 10 },    { "D0AWI.1",  UNIT_RAM_D0, 11 },    { "D0BRI.0",  UNIT_RAM_D0, 12 },    { "D0BRI.1",  UNIT_RAM_D0, 13 },    { "D0BWI.0",  UNIT_RAM_D0, 14 },    { "D0BWI.1",  UNIT_RAM_D0, 15 },     { "AC0.0",    UNIT_ACC_D0, 16 },    { "AC0.1",    UNIT_ACC_D0, 17 },    { "AC0.2",    UNIT_ACC_D0, 18 },    { "AC0.3",    UNIT_ACC_D0, 19 },     { "D1AR.0",   UNIT_RAM_D1,  0 },    { "D1AR.1",   UNIT_RAM_D1,  1 },    { "D1AW.0",   UNIT_RAM_D1,  2 },    { "D1AW.1",   UNIT_RAM_D1,  3 },    { "D1BR.0",   UNIT_RAM_D1,  4 },    { "D1BR.1",   UNIT_RAM_D1,  5 },    { "D1BW.0",   UNIT_RAM_D1,  6 },    { "D1BW.1",   UNIT_RAM_D1,  7 },    { "D1ARI.0",  UNIT_RAM_D1,  8 },    { "D1ARI.1",  UNIT_RAM_D1,  9 },    { "D1AWI.0",  UNIT_RAM_D1, 10 },    { "D1AWI.1",  UNIT_RAM_D1, 11 },    { "D1BRI.0",  UNIT_RAM_D1, 12 },    { "D1BRI.1",  UNIT_RAM_D1, 13 },    { "D1BWI.0",  UNIT_RAM_D1, 14 },    { "D1BWI.1",  UNIT_RAM_D1, 15 },     { "AC1.0",    UNIT_ACC_D1, 16 },    { "AC1.1",    UNIT_ACC_D1, 17 },    { "AC1.2",    UNIT_ACC_D1, 18 },    { "AC1.3",    UNIT_ACC_D1, 19 },     { "T0",       UNIT_DT,  0 },    { "T1",       UNIT_DT,  1 },    { "T2",       UNIT_DT,  2 },    { "T3",       UNIT_DT,  3 },    { "T4",       UNIT_DT,  4 },    { "T5",       UNIT_DT,  5 },    { "T6",       UNIT_DT,  6 },    { "T7",       UNIT_DT,  7 },    { "T8",       UNIT_DT,  8 },    { "T9",       UNIT_DT,  9 },    { "TA",       UNIT_DT, 10 },    { "TB",       UNIT_DT, 11 },    { "TC",       UNIT_DT, 12 },    { "TD",       UNIT_DT, 13 },    { "TE",       UNIT_DT, 14 },    { "TF",       UNIT_DT, 15 },  }; /* This table differs from 'metag_dsp_regtab' in that the number   fields in this table are suitable for insertion into DSPRAM   template definition instruction encodings.    The table is indexed by "load". The main benefit of this is that we   can implicitly check that the correct DSPRAM register has been used   when parsing, e.g. the read pointer only appears in the load table   and the write pointer only exists in the store table.    The ordering of the table entries might look a bit weird but it is   based on matching the longest register string. */static const metag_reg metag_dsp_tmpl_regtab[2][56] =  {    {      { "D0AW.0+D0AWI.0++", UNIT_RAM_D0, 18 },      { "D0AW.0+D0AWI.0",   UNIT_RAM_D0, 18 },      { "D0AW.0+D0AWI.1++", UNIT_RAM_D0, 19 },      { "D0AW.0+D0AWI.1",   UNIT_RAM_D0, 19 },      { "D0AW.0++",         UNIT_RAM_D0, 17 },      { "D0AW.0",           UNIT_RAM_D0, 16 },      { "D0AWI.0",          UNIT_RAM_D0, 18 },      { "D0AWI.1",          UNIT_RAM_D0, 19 },      { "D0AW.1+D0AWI.0++", UNIT_RAM_D0, 22 },      { "D0AW.1+D0AWI.0",   UNIT_RAM_D0, 22 },      { "D0AW.1+D0AWI.1++", UNIT_RAM_D0, 23 },      { "D0AW.1+D0AWI.1",   UNIT_RAM_D0, 23 },      { "D0AW.1++",         UNIT_RAM_D0, 21 },      { "D0AW.1",           UNIT_RAM_D0, 20 },      { "D0BW.0+D0BWI.0++", UNIT_RAM_D0, 26 },      { "D0BW.0+D0BWI.0",   UNIT_RAM_D0, 26 },      { "D0BW.0+D0BWI.1++", UNIT_RAM_D0, 27 },      { "D0BW.0+D0BWI.1",   UNIT_RAM_D0, 27 },      { "D0BW.0++",         UNIT_RAM_D0, 25 },      { "D0BW.0",           UNIT_RAM_D0, 24 },      { "D0BWI.0",          UNIT_RAM_D0, 18 },      { "D0BWI.1",          UNIT_RAM_D0, 19 },      { "D0BW.1+D0BWI.0++", UNIT_RAM_D0, 30 },      { "D0BW.1+D0BWI.0",   UNIT_RAM_D0, 30 },      { "D0BW.1+D0BWI.1++", UNIT_RAM_D0, 31 },      { "D0BW.1+D0BWI.1",   UNIT_RAM_D0, 31 },      { "D0BW.1++",         UNIT_RAM_D0, 29 },      { "D0BW.1",           UNIT_RAM_D0, 28 },       { "D1AW.0+D1AWI.0++", UNIT_RAM_D1, 18 },      { "D1AW.0+D1AWI.0",   UNIT_RAM_D1, 18 },      { "D1AW.0+D1AWI.1++", UNIT_RAM_D1, 19 },      { "D1AW.0+D1AWI.1",   UNIT_RAM_D1, 19 },      { "D1AW.0++",         UNIT_RAM_D1, 17 },      { "D1AW.0",           UNIT_RAM_D1, 16 },      { "D1AWI.0",          UNIT_RAM_D1, 18 },      { "D1AWI.1",          UNIT_RAM_D1, 19 },      { "D1AW.1+D1AWI.0++", UNIT_RAM_D1, 22 },      { "D1AW.1+D1AWI.0",   UNIT_RAM_D1, 22 },      { "D1AW.1+D1AWI.1++", UNIT_RAM_D1, 23 },      { "D1AW.1+D1AWI.1",   UNIT_RAM_D1, 23 },      { "D1AW.1++",         UNIT_RAM_D1, 21 },      { "D1AW.1",           UNIT_RAM_D1, 20 },      { "D1BW.0+D1BWI.0++", UNIT_RAM_D1, 26 },      { "D1BW.0+D1BWI.0",   UNIT_RAM_D1, 26 },      { "D1BW.0+D1BWI.1++", UNIT_RAM_D1, 27 },      { "D1BW.0+D1BWI.1",   UNIT_RAM_D1, 27 },      { "D1BW.0++",         UNIT_RAM_D1, 25 },      { "D1BW.0",           UNIT_RAM_D1, 24 },      { "D1BWI.0",          UNIT_RAM_D1, 18 },      { "D1BWI.1",          UNIT_RAM_D1, 19 },      { "D1BW.1+D1BWI.0++", UNIT_RAM_D1, 30 },      { "D1BW.1+D1BWI.0",   UNIT_RAM_D1, 30 },      { "D1BW.1+D1BWI.1++", UNIT_RAM_D1, 31 },      { "D1BW.1+D1BWI.1",   UNIT_RAM_D1, 31 },      { "D1BW.1++",         UNIT_RAM_D1, 29 },      { "D1BW.1",           UNIT_RAM_D1, 28 },    },     {      { "D0AR.0+D0ARI.0++", UNIT_RAM_D0, 18 },      { "D0AR.0+D0ARI.0",   UNIT_RAM_D0, 18 },      { "D0AR.0+D0ARI.1++", UNIT_RAM_D0, 19 },      { "D0AR.0+D0ARI.1",   UNIT_RAM_D0, 19 },      { "D0AR.0++",         UNIT_RAM_D0, 17 },      { "D0AR.0",           UNIT_RAM_D0, 16 },      { "D0ARI.0",          UNIT_RAM_D0, 18 },      { "D0ARI.1",          UNIT_RAM_D0, 19 },      { "D0AR.1+D0ARI.0++", UNIT_RAM_D0, 22 },      { "D0AR.1+D0ARI.0",   UNIT_RAM_D0, 22 },      { "D0AR.1+D0ARI.1++", UNIT_RAM_D0, 23 },      { "D0AR.1+D0ARI.1",   UNIT_RAM_D0, 23 },      { "D0AR.1++",         UNIT_RAM_D0, 21 },      { "D0AR.1",           UNIT_RAM_D0, 20 },      { "D0BR.0+D0BRI.0++", UNIT_RAM_D0, 26 },      { "D0BR.0+D0BRI.0",   UNIT_RAM_D0, 26 },      { "D0BR.0+D0BRI.1++", UNIT_RAM_D0, 27 },      { "D0BR.0+D0BRI.1",   UNIT_RAM_D0, 27 },      { "D0BR.0++",         UNIT_RAM_D0, 25 },      { "D0BR.0",           UNIT_RAM_D0, 24 },      { "D0BRI.0",          UNIT_RAM_D0, 18 },      { "D0BRI.1",          UNIT_RAM_D0, 19 },      { "D0BR.1+D0BRI.0++", UNIT_RAM_D0, 30 },      { "D0BR.1+D0BRI.0",   UNIT_RAM_D0, 30 },      { "D0BR.1+D0BRI.1++", UNIT_RAM_D0, 31 },      { "D0BR.1+D0BRI.1",   UNIT_RAM_D0, 31 },      { "D0BR.1++",         UNIT_RAM_D0, 29 },      { "D0BR.1",           UNIT_RAM_D0, 28 },       { "D1AR.0+D1ARI.0++", UNIT_RAM_D1, 18 },      { "D1AR.0+D1ARI.0",   UNIT_RAM_D1, 18 },      { "D1AR.0+D1ARI.1++", UNIT_RAM_D1, 19 },      { "D1AR.0+D1ARI.1",   UNIT_RAM_D1, 19 },      { "D1AR.0++",         UNIT_RAM_D1, 17 },      { "D1AR.0",           UNIT_RAM_D1, 16 },      { "D1ARI.0",          UNIT_RAM_D1, 18 },      { "D1ARI.1",          UNIT_RAM_D1, 19 },      { "D1AR.1+D1ARI.0++", UNIT_RAM_D1, 22 },      { "D1AR.1+D1ARI.0",   UNIT_RAM_D1, 22 },      { "D1AR.1+D1ARI.1++", UNIT_RAM_D1, 23 },      { "D1AR.1+D1ARI.1",   UNIT_RAM_D1, 23 },      { "D1AR.1++",         UNIT_RAM_D1, 21 },      { "D1AR.1",           UNIT_RAM_D1, 20 },      { "D1BR.0+D1BRI.0++", UNIT_RAM_D1, 26 },      { "D1BR.0+D1BRI.0",   UNIT_RAM_D1, 26 },      { "D1BR.0+D1BRI.1++", UNIT_RAM_D1, 27 },      { "D1BR.0+D1BRI.1",   UNIT_RAM_D1, 27 },      { "D1BR.0++",         UNIT_RAM_D1, 25 },      { "D1BR.0",           UNIT_RAM_D1, 24 },      { "D1BR.1+D1BRI.0++", UNIT_RAM_D1, 30 },      { "D1BR.1+D1BRI.0",   UNIT_RAM_D1, 30 },      { "D1BR.1+D1BRI.1++", UNIT_RAM_D1, 31 },      { "D1BR.1+D1BRI.1",   UNIT_RAM_D1, 31 },      { "D1BR.1++",         UNIT_RAM_D1, 29 },      { "D1BR.1",           UNIT_RAM_D1, 28 },      { "D1BRI.0",          UNIT_RAM_D1, 18 },      { "D1BRI.1",          UNIT_RAM_D1, 19 },    },  }; typedef struct{

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